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"Efficient SAT-based Boolean matching for FPGA technology mapping."

Sean Safarpour et al. (2006)

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DOI: 10.1145/1146909.1147034

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/dac/SafarpourVBY06
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Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan:
Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471

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