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"20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process."

Pratap Narayan Singh et al. (2007)

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DOI: 10.1109/CICC.2007.4405710

access: closed

type: Conference or Workshop Paper

metadata version: 2018-05-30

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Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. CICC 2007: 189-192

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