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"A Power Minimization Technique for Arithmetic Circuits by Cell Selection."

Masanori Muroyama et al. (2002)

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DOI: 10.1109/ASPDAC.2002.994933

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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  dblp key:
  - conf/vlsid/MuroyamaIHY02
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  - https://dblp.org/rec/conf/vlsid/MuroyamaIHY02
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura:
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design 2002: 268-273

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