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"A Method for Synthesizing Area Efficient Multilevel PTL Circuits."

Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien (1997)

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DOI: 10.1109/ICVD.1997.568191

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/BandyopadhyayJJ97
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/BandyopadhyayJJ97
Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien:
A Method for Synthesizing Area Efficient Multilevel PTL Circuits. VLSI Design 1997: 516-519

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