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Tae-Kwang Jang
Taekwang Jang
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2020 – today
- 2024
- [j23]Gabriele Atzeni
, Can Livanelioglu
An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance. IEEE J. Solid State Circuits 59(4): 1026-1037 (2024) - [j22]Jungho Lee
A Sub-mm3 Wireless Neural Stimulator IC for Visual Cortical Prosthesis With Optical Power Harvesting and 7.5-kb/s Data Telemetry. IEEE J. Solid State Circuits 59(4): 1110-1122 (2024) - [j21]Yongjo Kim
A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor. IEEE J. Solid State Circuits 59(10): 3253-3262 (2024) - [j20]Riccardo Vignali
Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1650-1655 (2024) - [c42]Suyang Song, Alessandro Novello, Taekwang Jang:
Challenges and Innovations in Fully Integrated DC-DC Converters for IoT and Modern Computing Platforms. CICC 2024: 1-8 - [c41]Nellie Laleni, Sahana Padma, Thomas Kämpfe, Taekwang Jang:
Single Slope ADC with Reset Counting for FeFET-based In-Memory Computing. ISCAS 2024: 1-5 - [c40]Tim Keller, Rosario M. Incandela, Xi Chen, Hesam Ghiasi, Mohsen Khodaee, Sina Arjmandpour, Jiawei Liao, H. Long, Tobias Götschi, Jonas Widmer, Taekwang Jang:
A 0.29pJ/Step Fully Discrete-Time Charge Domain Bridge-to-Digital Converter for Force Sensing in Spinal Implants Using RC Bridge. VLSI Technology and Circuits 2024: 1-2 - [i3]Qinyu Chen
A 65nm 36nJ/Decision Bio-inspired Temporal-Sparsity-Aware Digital Keyword Spotting IC with 0.6V Near-Threshold SRAM. CoRR abs/2405.03905 (2024) - 2023
- [j19]Louis Colbach, Taekwang Jang
A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation. Sensors 23(4): 1862 (2023) - [c39]Yongjo Kim, Taekwang Jang, SeongHwan Cho:
A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor. A-SSCC 2023: 1-3 - [c38]Jiawei Liao, Hesam Ghiasi, Giorgio Cristiano, Taekwang Jang:
A High-Order-Temperature-Compensated 328kHz On Chip RC Timer Using Time-Interleaved Resistors Achieving 1.5pJ/Cycle and 5.86ppm°C. CICC 2023: 1-2 - [c37]Serdar A. Yonar, Pier Andrea Francese
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ISSCC 2023: 266-267 - [c36]Gabriele Atzeni, Can Livanelioglu, Lavinia Recchioni, Sina Arjmandpour
An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance. VLSI Technology and Circuits 2023: 1-2 - [c35]Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour
A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing. VLSI Technology and Circuits 2023: 1-2 - [c34]Jungho Lee
A Wireless Neural Stimulator IC for Cortical Visual Prosthesis. VLSI Technology and Circuits 2023: 1-2 - [c33]Alessandro Novello, Gabriele Atzeni, Tim Keller
A 4.1W/mm² Peak Power Density and 77% Peak Efficiency Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators and a Resonant LC Flying Impedance in 22nm FDSOI CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j18]Li Xu
A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection. IEEE J. Solid State Circuits 57(2): 434-451 (2022) - [j17]Jongyup Lim
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and Data Telemetry. IEEE J. Solid State Circuits 57(4): 1061-1074 (2022) - [j16]Gabriele Atzeni
A 1.01 NEF Low-Noise Amplifier Using Complementary Parametric Amplification. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1065-1076 (2022) - [c32]Jiawei Liao, Lars Widmer, Xiaying Wang
An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface. AICAS 2022: 134-137 - [c31]Youngwoo Ji, Jiawei Liao, Sina Arjmandpour
A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range. ISSCC 2022: 1-3 - [c30]Can Livanelioglu
A 0.0014 mm2, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits. VLSI Technology and Circuits 2022: 62-63 - [c29]Gabriele Atzeni, Jongyup Lim, Jiawei Liao, Alessandro Novello, Jungho Lee
A 260×274 μm2 572 nW Neural Recording Micromote Using Near-Infrared Power Transfer and an RF Data Uplink. VLSI Technology and Circuits 2022: 64-65 - [c28]Gabriele Atzeni, Rosario M. Incandela, Youngwoo Ji, Alessandro Novello, Hesam Ghiasi, Giorgio Cristiano, Jiawei Liao, Qiuting Huang, Taekwang Jang
An Impedance-boosted Switched-capacitor Low-noise Amplifier Achieving 0.4 NEF. VLSI Technology and Circuits 2022: 116-117 - [i2]Jiawei Liao, Lars Widmer, Xiaying Wang, Alfio Di Mauro, Samuel R. Nason-Tomaszewski, Cynthia A. Chestek, Luca Benini, Taekwang Jang:
An Energy-Efficient Spiking Neural Network for Finger Velocity Decoding for Implantable Brain-Machine Interface. CoRR abs/2210.06287 (2022) - 2021
- [j15]Ji-Hwan Seol
Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur. IEEE J. Solid State Circuits 56(10): 2993-3007 (2021) - [j14]Alessandro Novello
A 1.25-GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators. IEEE J. Solid State Circuits 56(12): 3639-3654 (2021) - [j13]Luca Benini, Simone Benatti
Guest Editorial: IEEE TC Special Issue On Smart Edge Computing and IoT. IEEE Trans. Computers 70(8): 1146-1147 (2021) - [j12]Ahmed Elnaqib
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 156-160 (2021) - [c27]Donghyeok Cho, Nahmil Koo, Taekwang Jang
An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction. ISCAS 2021: 1-5 - [c26]Alessandro Novello
17.3 A 1.25GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators. ISSCC 2021: 260-262 - [c25]Jongyup Lim, Jungho Lee
A Light Tolerant Neural Recording IC for Near-Infrared-Powered Free Floating Motes. VLSI Circuits 2021: 1-2 - [c24]Alessandro Novello
A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c23]Li Xu
3.3 A 0.51nW 32kHz Crystal Oscillator Achieving 2ppb Allan Deviation Floor Using High-Energy-to-Noise-Ratio Pulse Injection. ISSCC 2020: 62-64 - [c22]Jongyup Lim, Eunseong Moon, Michael Barrow, Samuel R. Nason, Paras R. Patel, Parag G. Patil, Sechang Oh, Inhee Lee
26.9 A 0.19×0.17mm2 Wireless Neural Recording IC for Motor Prediction with Near-Infrared-Based Power and Data Telemetry. ISSCC 2020: 416-418 - [c21]Gabriele Atzeni, Jérémy Guichemerre, Alessandro Novello
An Energy-Efficient Low-Noise Complementary Parametric Amplifier Achieving 0.89 NEF. MWSCAS 2020: 5-8 - [c20]Giorgio Cristiano, Jiawei Liao, Alessandro Novello
A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops. VLSI Circuits 2020: 1-2 - [i1]Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini:
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL. CoRR abs/2007.07654 (2020)
2010 – 2019
- 2019
- [j11]Yimai Peng
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier. IEEE J. Solid State Circuits 54(12): 3348-3361 (2019) - [c19]Yimai Peng
An Adiabatic Sense and Set Rectifier for Improved Maximum-Power-Point Tracking in Piezoelectric Harvesting with 541% Energy Extraction Gain. ISSCC 2019: 422-424 - [c18]Ji-Hwan Seol, Dennis Sylvester, David T. Blaauw, Tae-Kwang Jang
A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur. VLSI Circuits 2019: 160- - [c17]Taewook Kang, Inhee Lee, Sechang Oh, Tae-Kwang Jang
A 1.74.12 mm3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation. VLSI Circuits 2019: 310- - 2018
- [j10]Tae-Kwang Jang
A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector. IEEE J. Solid State Circuits 53(1): 50-65 (2018) - [j9]Seokhyeon Jeong
Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for Unattended Ground Sensor Nodes. IEEE J. Solid State Circuits 53(1): 261-274 (2018) - [c16]Hyeongseok Kim, Nikolaos Chiotellis, Elnaz Ansari, Muhammad Faisal, Tae-Kwang Jang
A receiver/antenna co-design for a 1.5mJ per fix fully-integrated 10×10×6mm3 GPS logger. CICC 2018: 1-4 - [c15]Jongyup Lim
A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency Cancellation. VLSI Circuits 2018: 117-118 - [c14]Tae-Kwang Jang
A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric Amplification. VLSI Circuits 2018: 237-238 - 2017
- [j8]Taekwang Jang
Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part I - Analog Circuit Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2237-2249 (2017) - [j7]Tae-Kwang Jang
Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part II - Data Communication, Energy Harvesting, Power Management, and Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2250-2262 (2017) - [c13]Tae-Kwang Jang
8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. ISSCC 2017: 148-149 - [c12]Seokhyeon Jeong, Yu Chen, Tae-Kwang Jang
21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification. ISSCC 2017: 362-363 - 2016
- [j6]Dongmin Yoon, Tae-Kwang Jang
A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks. IEEE J. Solid State Circuits 51(2): 509-522 (2016) - [j5]Myungjoon Choi, Tae-Kwang Jang
A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs. IEEE J. Solid State Circuits 51(9): 2106-2118 (2016) - [j4]Myungjoon Choi, Tae-Kwang Jang
A Resonant Current-Mode Wireless Power Receiver and Battery Charger With -32 dBm Sensitivity for Implantable Systems. IEEE J. Solid State Circuits 51(12): 2880-2892 (2016) - [c11]Tae-Kwang Jang
5.8 A 4.7nW 13.8ppm/°C self-biased wakeup timer using a switched-resistor scheme. ISSCC 2016: 102-103 - [c10]Myungjoon Choi, Tae-Kwang Jang
21.5 A current-mode wireless power receiver with optimal resonant cycle tracking for implantable systems. ISSCC 2016: 372-373 - [c9]Tae-Kwang Jang
Millimeter-scale computing platform for next generation of Internet of Things. IEEE RFID 2016: 1-4 - [c8]Wootaek Lim, Tae-Kwang Jang
A 380pW dual mode optical wake-up receiver with ambient noise cancellation. VLSI Circuits 2016: 1-2 - 2015
- [c7]Tae-Kwang Jang
FOCUS: Key building blocks and integration strategy of a miniaturized wireless sensor node. ESSCIRC 2015: 257-262 - [c6]Myungjoon Choi, Suyoung Bang, Tae-Kwang Jang
A 99nW 70.4kHz resistive frequency locking on-chip oscillator with 27.4ppm/ºC temperature stability. VLSIC 2015: 238- - 2014
- [c5]Myungjoon Choi, Inhee Lee, Tae-Kwang Jang
A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs. ESSCIRC 2014: 119-122 - [c4]Jenlung Liu, Tae-Kwang Jang
15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. ISSCC 2014: 268-269 - 2013
- [c3]Tae-Kwang Jang
A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. ISSCC 2013: 254-255 - 2012
- [j3]Tae-Kwang Jang
A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1368-1372 (2012) - [c2]Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang
A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. ISSCC 2012: 240-242 - 2011
- [c1]Jenlung Liu, Sehyung Jeon, Tae-Kwang Jang
A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS. A-SSCC 2011: 337-340 - 2010
- [j2]Jaewook Kim, Tae-Kwang Jang
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 18-30 (2010)
2000 – 2009
- 2008
- [j1]Young-Gyu Yoon
A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3571-3581 (2008)
Coauthor Index
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