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Katell Morin-Allory
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2020 – today
- 2024
- [c42]Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Resilience Metric Characterization in Complex Digital Systems. ETS 2024: 1-4 - [c41]Damiano Zuccalà, Paul Breuil, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Fault Injection in Digital Blocks with Mined Assertions. MEMOCODE 2024: 77-86 - 2023
- [c40]Diana Kalel, Jean-Christophe Brignone, Laurent Fesquet, Katell Morin-Allory:
A Generic CDC Modeling for Data Stability Verification. ICECS 2023: 1-4 - [c39]Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory:
Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI 2023: 1-6 - [c38]Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet:
Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC 2023: 1-6 - 2021
- [c37]Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory:
FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. ISVLSI 2021: 170-175 - [c36]Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet:
A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. VLSI-SoC 2021: 1-6 - [c35]Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. VLSI-SoC 2021: 1-6 - [c34]Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle:
FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. VLSI-SoC (Selected Papers) 2021: 113-133 - 2020
- [c33]Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. DDECS 2020: 1-4 - [c32]Noureddine Ait Said
, Mounir Benabdenbi, Katell Morin-Allory:
FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. DTIS 2020: 1-6 - [c31]Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier:
High Level Fault Injection Method for Evaluating Critical System Parameter Ranges. ICECS 2020: 1-4 - [c30]Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet:
From High-Level Synthesis to Bundled-Data Circuits. SAMOS 2020: 200-212
2010 – 2019
- 2019
- [j6]Guillaume Plassan
Mining Missing Assumptions from Counter-Examples. ACM Trans. Embed. Comput. Syst. 18(1): 3:1-3:25 (2019) - [c29]Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet:
Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP 2019: 1-8 - [c28]Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels:
A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC 2019: 27-32 - 2017
- [j5]Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione
Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 869-882 (2017) - [c27]Guillaume Plassan, Katell Morin-Allory, Dominique Borrione:
Extraction of missing formal assumptions in under-constrained designs. MEMOCODE 2017: 94-103 - 2016
- [c26]Mejid Kebaili, Jean-Christophe Brignone, Katell Morin-Allory:
Clock domain crossing formal verification: a meta-model. HLDVT 2016: 136-141 - [c25]Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione:
Conclusively verifying clock-domain crossings in very large hardware designs. VLSI-SoC 2016: 1-6 - [c24]Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione:
Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. VLSI-SoC (Selected Papers) 2016: 108-129 - 2015
- [j4]Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
Efficient and Correct by Construction Assertion-Based Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2890-2901 (2015) - [c23]Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione:
Enabler-based synchronizer model for clock domain crossing static verification. FDL 2015: 11-17 - 2013
- [c22]Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
Fast prototyping from assertions: A pragmatic approach. MEMOCODE 2013: 23-32 - [c21]Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione:
SyntHorus-2: Automatic prototyping from PSL. VLSI-SoC 2013: 72-77 - 2011
- [c20]Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory:
Formal Verification of C-element Circuits. ASYNC 2011: 55-64 - [c19]Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya:
Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL 2011: 1-6 - [c18]Florent Ouchet, Katell Morin-Allory, Laurent Fesquet:
C-elements for Hardened Self-timed Circuits. PATMOS 2011: 247-256 - 2010
- [j3]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1436-1448 (2010) - [c17]Florent Ouchet, Katell Morin-Allory, Laurent Fesquet:
Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC 2010: 176-184 - [c16]Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet:
Synthesis of asynchronous monitors for critical electronic systems. DDECS 2010: 329-334
2000 – 2009
- 2009
- [c15]Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre:
High-level symbolic simulation for automatic model extraction. DDECS 2009: 218-221 - [c14]Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet:
RAT-based formal verification of QDI asynchronous controllers. FDL 2009: 1-6 - [c13]Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80 - [c12]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC 2009: 94-117 - 2008
- [c11]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63 - [c10]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
Assertion-Based Design with Horus. MEMOCODE 2008: 75-76 - 2007
- [j2]Katell Morin-Allory, Eric Gascard
Synthesis of Property Monitors for Online Fault Detection. J. Circuits Syst. Comput. 16(6): 943-960 (2007) - [c9]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS 2007: 383-388 - [c8]Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione:
Asynchronous online-monitoring of logical and temporal assertions. FDL 2007: 286-290 - 2006
- [c7]Katell Morin-Allory, Dominique Borrione:
Proven correct monitors from PSL specifications. DATE 2006: 1246-1251 - [c6]Katell Morin-Allory, Dominique Borrione:
On-line Monitoring of Properties Built on Regular Expressions. FDL 2006: 249-255 - [c5]Katell Morin-Allory, Laurent Fesquet, Dominique Borrione:
Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping 2006: 98-102 - [c4]Yann Oddos, Katell Morin-Allory, Dominique Borrione:
On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC 2006: 397-402 - 2005
- [j1]David Cachera, Katell Morin-Allory:
Verification of safety properties for parameterized regular systems. ACM Trans. Embed. Comput. Syst. 4(2): 228-266 (2005) - [c3]Katell Morin-Allory, David Cachera:
Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic. CHARME 2005: 376-379 - [c2]Katell Morin-Allory, Dominique Borrione:
A proof of correctness for the construction of property monitors. HLDVT 2005: 237-244 - 2004
- [b1]Katell Morin-Allory:
Vérification Formelle dans le Modèle Polyédrique. (Formal Verification in the Polyhedral Model). University of Rennes 1, France, 2004 - 2003
- [c1]David Cachera, Katell Morin-Allory:
Verification of Control Properties in the Polyhedral Model. MEMOCODE 2003: 265-
Coauthor Index
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