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Sukumar Jairam
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2010 – 2019
- 2010
- [c11]Jithendra Srinivas, Sukumar Jairam:
Clock gating approaches by IOEX graphs and cluster efficiency plots. DATE 2010: 638-641
2000 – 2009
- 2009
- [c10]Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao:
Clock gating effectiveness metrics: Applications to power optimization. ISQED 2009: 482-487 - 2008
- [c9]Sukumar Jairam, Kusum Lata
, Subir K. Roy
Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches. ICECS 2008: 910-913 - [c8]Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao:
Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED 2008: 307-308 - [c7]Sukumar Jairam, S. M. Stalin, Jean-Yves Oberle, H. Udayakumar:
An SSO Based Methodology for EM Emission Estimation from SoCs. ISQED 2008: 297-300 - [c6]Santhosh Coimbatore Vaidyanathan, Amit Mangesh Brahme, Sukumar Jairam:
Techniques for Early Package Closure in System-in-Packages. ISQED 2008: 608-613 - [c5]Sukumar Jairam, Navakanta Bhat:
GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes. VLSI Design 2008: 589-594 - 2007
- [c4]Sankar P. Debnath, Ganesh P. Kumar, Sukumar Jairam:
Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCsc. VLSI Design 2007: 887-892 - 2006
- [c3]Snehashis Roy
A Methodology for Switching Activity Based IO Powerpad Optimisation. VLSI Design 2006: 794-797 - 2005
- [c2]Sankar P. Debnath, Sukumar Jairam, H. Udayakumar:
A Methodology for Fast Vector Based Power Supply and Substrate Noise Analyses. VLSI Design 2005: 808-811 - 2004
- [c1]Sukumar Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap:
A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework. VLSI Design 2004: 642-645
Coauthor Index
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