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Yasuhiko Taito
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2020 – today
- 2024
- [j7]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda
, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C. IEEE J. Solid State Circuits 59(4): 1283-1292 (2024) - [c7]Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono:
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs. ISSCC 2024: 290-292 - 2022
- [j6]Amir Amirkhany
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 57(1): 3-5 (2022) - [j5]Masaya Nakano
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier. IEEE J. Solid State Circuits 57(10): 3094-3102 (2022) - [c6]Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C. VLSI Technology and Circuits 2022: 134-135 - 2021
- [c5]Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. A-SSCC 2021: 1-3 - [c4]Yasuhiko Taito, Violante Moschiano, Shinichiro Shiratake:
Session 30 Overview: Non-Volatile Memories Memory Subcommittee. ISSCC 2021: 420-421 - 2020
- [j4]Takashi Kono, Yasuhiko Taito, Hideto Hidaka:
Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age. IEICE Trans. Electron. 103-C(4): 132-143 (2020)
2010 – 2019
- 2019
- [c3]Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive. VLSI Circuits 2019: 210- - 2018
- [p1]Takashi Ito, Yasuhiko Taito:
SONOS Split-Gate eFlash Memory. Embedded Flash Memory for Embedded Systems 2018: 209-244 - 2016
- [j3]Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. IEEE J. Solid State Circuits 51(1): 213-221 (2016) - [c2]Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Hashimoto, Hideaki Yamakoshi, Shinichiro Abe, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Krafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. ISSCC 2016: 140-141 - 2015
- [c1]Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi:
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. ISSCC 2015: 1-3
2000 – 2009
- 2003
- [j2]Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki:
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2991-3000 (2003) - [j1]Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto:
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits 38(11): 1967-1973 (2003)
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