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Martín Vázquez 0001
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- affiliation: National University of Central Buenos Aires (UNICEN), LabSET-INTIA, Tandil, Argentina
- affiliation: FASTA University, Faculty of Engineering, Buenos Aires, Argentina
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2020 – today
- 2024
- [j11]Lucas Leiva
, Bruno Constanzo
Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU. IEEE Embed. Syst. Lett. 16(1): 61-64 (2024) - [j10]Ezequiel Carbajo, Lucas Leiva
Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing. IEEE Embed. Syst. Lett. 16(3): 303-306 (2024) - [j9]Marcelo Tosini, Martín Vázquez, Lucas Leiva
Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding. J. Supercomput. 80(7): 9298-9326 (2024) - 2023
- [j8]Lucas Leiva
FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library. IEEE Embed. Syst. Lett. 15(2): 113-116 (2023) - 2022
- [j7]Lucas Leiva
FPGA acceleration analysis of LibSVM predictors based on high-level synthesis. J. Supercomput. 78(12): 14137-14163 (2022) - 2021
- [j6]Martín Vázquez, Marcelo Tosini, Lucas Leiva
Radix-10 Restoring Square Root for 6-input LUTs Programmable Devices. Circuits Syst. Signal Process. 40(5): 2335-2360 (2021)
2010 – 2019
- 2019
- [j5]Martín Vázquez, Lucas Leiva
Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. Microprocess. Microsystems 64: 143-158 (2019) - 2016
- [j4]Elias Todorovich, Ana Lucía Dai Pra, Lucía Isabel Passoni, Martín Vázquez, Ezequiel Cozzolino, Fernando Ferrara, Gery Bioul:
Real-time speckle image processing. J. Real Time Image Process. 11(3): 535-545 (2016) - 2012
- [j3]Elias Todorovich, José A. Marone, Martín Vázquez:
Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course. IEEE Trans. Educ. 55(2): 255-262 (2012) - [j2]Elias Todorovich, José A. Marone, Martín Vázquez:
Correction to "Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course". IEEE Trans. Educ. 55(2): 305 (2012) - 2010
- [j1]Gery Bioul, Martín Vázquez, Jean-Pierre Deschamps, Gustavo Sutter:
High-Speed FPGA 10's Complement Adders-Subtractors. Int. J. Reconfigurable Comput. 2010: 219764:1-219764:14 (2010)
2000 – 2009
- 2009
- [c2]Gustavo Sutter
FPGA Implementations of BCD Multipliers. ReConFig 2009: 36-41 - [c1]Martín Vázquez, Gustavo Sutter
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. ReConFig 2009: 42-47
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