default search action
Integration, Volume 47
Volume 47, Number 1, January 2014
- Kevin Brelsford, Serafín A. Pérez López, Santiago Fernández-Gomez:
Energy efficient computation: A silicon perspective. 1-11
- Mauro Santos, Nuno Horta
, Jorge Guilherme
A survey on nonlinear analog-to-digital converters. 12-22 - Fernando J. Marquez
A novel autozeroing technique for flash Analog-to-Digital converters. 23-29 - Pinar Basak Basyurt, Devrim Yilmaz Aksin
Untrimmed 6.2 ppm/°C bulk-isolated curvature-corrected bandgap voltage reference. 30-37 - Ihsan Çiçek, Ali Emre Pusane, Günhan Dündar
A novel design method for discrete time chaos based true random number generators. 38-47 - Vahid Foroutan, MohammadReza Taheri, Keivan Navi, Arash Azizi Mazreah:
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. 48-61 - Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish
Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design. 62-70 - Zao Liu, Sheldon X.-D. Tan, Hai Wang, Yingbo Hua, Ashish Gupta:
Compact thermal modeling for packaged microprocessor design with practical power maps. 71-85 - Xi Chen, Jiang Hu, Ning Xu:
Regularity-constrained floorplanning for multi-core processors. 86-95 - Armin Belghadr, Ali Jahanian
Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs. 96-104 - Wing-Kai Chow, Liang Li, Evangeline F. Y. Young, Chiu-Wing Sham
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach. 105-114 - Shmuel Wimer:
Planar CMOS to multi-gate layout conversion for maximal fin utilization. 115-122 - V. R. Vijaykumar
Hardware implementation of tag-reader mutual authentication protocol for RFID systems. 123-129 - Sun-Mi Park, Ku-Young Chang, Dowon Hong
New efficient bit-parallel polynomial basis multiplier for special pentanomials. 130-139 - Constantinos Efstathiou, Nikos K. Moshopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding. 140-147 - Igor Lemberski, Petr Fiser
Dual-rail asynchronous logic multi-level implementation. 148-159
Volume 47, Number 2, March 2014
- Eugene Shaphir, Ron Y. Pinter, Shmuel Wimer:
Cell-based interconnect migration by hierarchical optimization. 161-174 - Wei Zhao, Hailong Yao, Yici Cai, Subarna Sinha, Charles C. Chiang:
Fast and scalable parallel layout decomposition in double patterning lithography. 175-183 - Byunghyun Lee, Taewhan Kim:
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs. 184-194 - Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
Nano-CMOS thermal sensor design optimization for efficient temperature measurement. 195-203 - Rasoul Fathipour, Alireza Saberkari
High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator. 204-212 - Cristian Ferent, Alex Doboli:
Analog circuit design space description based on ordered clustering of feature uniqueness and similarity. 213-231 - Manhwee Jo, Dongwook Lee, Kyuseung Han, Kiyoung Choi:
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. 232-241 - Behzad Mesgarzadeh:
Simultaneous switching noise reduction by resonant clock distribution networks. 242-249 - Dmitry Verbitsky, Rostislav (Reuven) Dobkin, Ran Ginosar, Salomon Beer
StarSync: An extendable standard-cell mesochronous synchronizer. 250-260 - Mariangela Genovese, Ettore Napoli, Davide De Caro
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA. 261-271 - Mohammad Asyaei
Low power wide gates for modern power efficient processors. 272-283 - Robert Wille
Trading off circuit lines and gate costs in the synthesis of reversible logic. 284-294
Volume 47, Number 3, June 2014
- José L. Ayala
VLSI for the new era. 295 - Hailang Wang, Mohammad H. Asgari, Emre Salman:
Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs. 296-306 - Caleb Serafy, Bing Shi, Ankur Srivastava
A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs. 307-317 - Qing Xie
Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes. 318-328 - Yoshiro Riho, Kazuo Nakazato:
A new extension method of retention time for memory cell on dynamic random access memory. 329-338 - Muhammad E. S. Elrabaa:
A portable high-frequency digitally controlled oscillator (DCO). 339-346 - Amin Farshidi
Optimal gate sizing using a self-tuning multi-objective framework. 347-355 - Can Sitik, Baris Taskin
Iterative skew minimization for low swing clocks. 356-364 - Abdulkadir Akin, Ipek Baz, Alexandre Schmid
Dynamically adaptive real-time disparity estimation hardware using iterative refinement. 365-376 - Dimitris Koukounis, Christos Ttofis
A high performance hardware architecture for portable, low-power retinal vessel segmentation. 377-386
Volume 47, Number 4, September 2014
- Harris E. Michail, Georgios Athanasiou
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. 387-407 - Shiann-Rong Kuang, Kun-Yi Wu, Bao-Chen Ke, Jia-Huei Yeh, Hao-Yi Jheng:
Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction. 408-416 - Mehdi Habibi
A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors. 417-430 - I-Chyn Wey, Ye-Jhih Shen:
Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits. 431-442 - Morteza Dorrigiv
Low area/power decimal addition with carry-select correction and carry-select sum-digits. 443-451 - Jin-Tai Yan
Fault-tolerant analysis of TMR design with noise-aware logic. 452-460 - Ville Eerola, Jari Nurmi
High-level parameterizable area estimation modeling for ASIC designs. 461-475 - Sangdo Park
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis. 476-486 - Lerong Cheng, Wenyao Xu, Fengbo Ren
Statistical timing and power analysis of VLSI considering non-linear dependence. 487-498 - S. Sivanantham
Enhancement of test data compression with multistage encoding. 499-509 - Sudip Kundu, Pradip Mandal:
ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing. 510-531 - Ricardo Martins
Electromigration-aware analog Router with multilayer multiport terminal structures. 532-547 - Xiaolu Guo, Mario R. Casu
Simulation and design of an UWB imaging system for breast cancer detection. 548-559
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-18 00:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: