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ISOCC 2018: Daegu, South Korea
- International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018. IEEE 2018, ISBN 978-1-5386-7960-9
- Eunji Youn, Young-Chan Jang:
12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration. 1-2 - Melody Teoh, Sotoudeh Hamedi-Hagh:
Current Feedback-Based High Load Current Low Drop-Out Voltage Regulator in 65nm CMOS Technology. 3-4 - Hyunggoy Oh, Heetae Kim, Sangjun Lee, Sungho Kang:
Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. 7-8 - Bo-Yi Li, Jiun-Lang Huang:
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction. 9-10 - Minho Cheong, Ingeol Lee, Sungho Kang:
A Test Methodology for Neural Computing Unit. 11-12 - Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng:
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees. 13-14 - Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu:
Fast Steady-State Thermal Analysis. 15-16 - Yelim Youn, Kwangmin Kim, Byungsub Kim:
A Rule-of-thumb Condition to Avoid Large HRS Current in ReRAM Crossbar Array Design. 17-18 - Taehwan Kim, Jongsun Park
:
Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme. 19-20 - Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
2-D Failure Bitmap Compression Using Line Fault Marking Method. 21-22 - Yu-Ting Li, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Diagnosis of Resistive Nonvolatile-8T SRAMs. 23-24 - Kwangjin Lee, Tae Hee Han:
Reliability Optimization of ReRAM Architecture using Heterogeneous Error Correcting Code Scheme. 25-26 - Pan Xue, Haijun Shao, Dan Fang, Gan Guo, Wei Che, Zhiliang Hong:
A Digital ΣΔ Modulated Class-S Transmitter with Two-Step Up-conversion and Filter-less Front End. 27-28 - Giovanni Piccinni
A novel high precision SDR-based positioning system. 34-35 - Erwin Setiawan, Trio Adiono:
Implementation of Systolic Co-processor for Deep Neural Network Inference based on SoC. 36-37 - Ryuta Ishida, Toshinori Sato
Approximate Adder Generation for Image Processing Using Convolutional Neural Network. 38-39 - Hyunyoung Oh
Design of a Generic Security Interface for RISC-V Processors and its Applications. 40-41 - Myungwoo Oh, Chaeeun Lee, Sanghun Lee, Youngho Seo, Sunwoo Kim, Jooho Wang
Convolutional Neural Network Accelerator with Reconfigurable Dataflow. 42-43 - Bobbi Winema Yogatama, Jhonson Lee, Suksmandhira Harimurti
FPGA-based Optical Character Recognition for Handwritten Mathematical Expressions. 42-43 - Shreyash Patel, YoungBae Kim, Ken Choi:
Novel Low Power FinFET SRAM Cell Design With Better Read and Writabilty For Cache Memory. 44-45 - Byungjun Choi, Bohun Kim, Jongsun Park
Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique. 46-47 - Junichi Suzuki, Junichi Yamashita, Masami Hanyu, Masamichi Ido, Tatsuya Saito, Yasuhiro Nakashima, Masanori Hayashikoshi, Yukiyoshi Kiyota:
A Cost-Effective High Accuracy Auto-Trimming System without Tester Constraint for Low-End Embedded Flash Memory. 48-49 - Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang:
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. 50-51 - Jinyong Lee:
Study on Intel CPU-FPGA Architecture : Security Perspective. 52-53 - Yingfei Xiang, Yu Wang, Chuanjin Richard Shi:
A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems. 54-55 - Behnam Samadpoor Rikan, Hamed Abbasizadeh, Reza E. Rad, Arash Hejazi
1.6-ppm/°C Reference Voltage Generator with PSRR of -93dB based on Threshold Voltage Difference of LVT and SVT Devices. 60-61 - Taeju Lee, Ji-Hyoung Cha, Su-Hyun Han, Seong-Jin Kim, Minkyu Je:
A 4.86 µW/Channel Fully Differential Multi-Channel Neural Recording System. 68-69 - Sungbum Kang, Joonsang Yu, Kiyoung Choi:
Tapered-Ratio Compression for Residual Network. 72-73 - Gyu Jin Bae, Young Hwan Kim:
Segmentation-based disparity refinement. 74-75 - Ho Sub Lee, Young Hwan Kim:
Human Visual Attention Analysis-based Image Segmentation using Color Histogram. 76-77 - Tsung-Han Tsai, Chia-Hsiang Yao:
A Real-time Tracking Algorithm for Human Following Mobile Robot. 78-79 - Sangjae Lee, Byungin Moon:
Drivable Area Detection Method Capable of Distinguishing Vegetation Area on Country Road. 80-81 - Tzu-Yi Lai, Kuan-Hung Chen:
On-Chip Memory Optimization of High Efficiency Accelerator for Deep Convolutional Neural Networks. 82-83 - Lavanya Maddisetti
Performance Metrics of Inexact Multipliers Based on Approximate 5: 2 Compressors. 84-85 - Toshinori Sato
Exploiting Configurability for Correct Sign Calculation in an Approximate Adder. 86-87 - Yu-Chi Wei, Shi-Yu Huang:
A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL. 90-91 - Morteza Nabavi, Maitham Shams, Mohamad Sawan:
Temperature Independent Subthreshold Circuits Design. 92-93 - Imtinan Basem Attili, Soliman A. Mahmoud
Optimizing the Performance of a Low Power - Area Efficient OTA Design that is Based on Hybrid Current Shunting Technique. 95-96 - Gauri Punekar, Venkateswarlu Gonuguntla
A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier. 99-100 - Minhyun Jin, Hyejin Im, Minkyu Song, Soo Youn Kim:
Nano-ampere Current Sensing Technique for OLED Mobile Displays. 101-102 - Maha S. Diab
Elliptic OTA-C Low-Pass Filters for Analog Front-End of Biosignal Detection System. 103-104 - Hyunki Jung, Dzuhri Radityo Utomo, Saebyeok Shin, Seok-Kyun Han, Sang-Gug Lee, Jusung Kim:
Ka-band RF Front-End with 5dB NF and 16dB conversion gain in 45nm CMOS technology. 105-106 - Saebyeok Shin, Dzuhri Radityo Utomo, Hyunki Jung, Seok-Kyun Han, Sang-Gug Lee, Jusung Kim:
A 22.8-to-32.4 GHz Injection-locked Frequency Tripler with Source Degeneration. 107-108 - Jaegyeong Choi, Jungah Kim, Yongho Lee, Seungsoo Kim, Jongsik Kim, Hyunchol Shin:
Design of a Low-Power Complex Baseband Filter with Tunable Gain and Bandwidth in 65nm CMOS. 109-110 - Jill C. Mayeda, Donald Y. C. Lie, Jerry Lopez:
A 24-28GHz Reconfigurable CMOS Power Amplifier in 22nm FD-SOI for Intelligent SoC Applications. 111-112 - Erwin Setiawan, Trio Adiono, Syifaul Fuada
PHY Layer Design of OFDM-VLC System based on SoC using Reuse Methodology. 115-116 - Zhaoqian Zhong, Masato Edahiro:
Model-Based Parallelizer for Embedded Control Systems on Single-ISA Heterogeneous Multicore Processors. 117-118 - Byeong Yong Kong
Efficient Implementation of Multiple Interleavers in IDMA for 5G. 119-120 - Soyeon Choi, Hoyoung Yoo
Hybrid Decoding for Polar Codes. 121-122 - Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng:
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. 123-124 - So Yeon Jo, Namhyun Ahn, Yunsoo Lee, Suk-Ju Kang:
Transfer Learning-based Vehicle Classification. 127-128 - Hyunhoon Lee, Younghoon Byun, Seokha Hwang, Sunggu Lee, Youngjoo Lee
Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition. 129-130 - Tsung-Han Tsai, Yuan-Chen Ho, Yih-Ru Tsai:
Implementation of 3D Hand Gesture Recognition System using FPGA. 131-132 - Junseo Jo, Seokha Hwang, Sunggu Lee, Youngjoo Lee
Multi-Mode LSTM Network for Energy-Efficient Speech Recognition. 133-134 - Tomotaka Tanaka, Fumiya Naito, Makoto Nakamura, Daisuke Ito, Keiji Kishine:
A Wideband Differential VCO Based on Multiple-path Loop Architecture. 135-136 - Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park:
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. 140-141 - Min Kim, Kyung-Sub Son, Namhoon Kim, Chang Hang Rho, Jin-Ku Kang:
A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. 143-144 - Jitendra Kumar Saini, Avireni Srinivasulu
Low Power - High Speed Magnitude Comparator Circuit Using 12 CNFETs. 145-146 - Hyun-jeong Kwon, Young Hwan Kim, Seokhyeong Kang:
Estimation of Leakage Distribution Utilizing Gaussian Mixture Model. 149-150 - YoungBae Kim, Qiang Tong, Ken Choi, Eunchong Lee, Sung-Joon Jang, Byeong-Ho Choi:
System Level Power Reduction for YOLO2 Sub-modules for Object Detection of Future Autonomous Vehicles. 151-155 - Kojiro Tamura, Yuki Kametaka, Takuji Kousaka, Hirokazu Ohtagaki, Hiroyuki Asahara:
A Simple Circuit Model for PWM-1-Controlled DC-DC Converter and Its Analysis. 158-159 - Tatsuki Ohsato, Yuta Yamada, Xiuqin Wei, Hiroo Sekiya
Analysis and Design of Phase-Controlled Class-D ZVS Inverter. 160-161 - Yasuteru Hosokawa, Yoko Uwate, Yoshifumi Nishio
Design of Two Template Cellular Neural Networks for Color Image Processing. 162-163 - Kyohei Fujii, Shuhei Hashimoto, Yoko Uwate, Yoshifumi Nishio
Synchronization Phenomena of Coupled Chaotic Circuits Network with Coupling Strength Depending on Number of Degree. 164-165 - Shu Sumimoto, Yuichi Miyata, Ryuta Yoshimura, Yoko Uwate, Yoshifumi Nishio
Design of Convolutional Neural Network for Classifying Depth Prediction Images from Overhead. 166-167 - Akari Oura, Kyohei Fujii, Yoko Uwate, Yoshifumi Nishio
Analysis of Chaotic Circuit Networks with One-Way Coupling. 168-169 - Tso-Bing Juang, Cong-Yi Lin, Guan-Zhong Lin:
Area-Delay Product Efficient Design for Convolutional Neural Network Circuits Using Logarithmic Number Systems. 170-171 - Chun Zhao, Zong Jie Shen
Neuromorphic Properties of Memristor towards Artificial Intelligence. 172-173 - Chun Zhao, Guang You Zhou, Ce Zhou Zhao, Li Yang, Ka Lok Man, Eng Gee Lim
Memristor-based Neuromorphic Implementations for Artificial Neural Networks. 174-175 - Jieming Ma, Ziqiang Bi
Automatic Shading Detection System for Photovoltaic Strings. 176-177 - Zhao Wang, Heng Zhang, Zhenzhen Jiang, Mark Leach, Jing Chen Wang, Ka Lok Man, Eng Gee Lim
A Multiband Rectenna for Self-sustainable Devices. 178-179 - Yoko Uwate, Yoshifumi Nishio
Oscillation Quenching in Coupled van der Pol Oscillators with Different Frequencies. 180-181 - Joonho Park, Yong Moon:
A design of rectifier for 13.56MHz wireless power transfer receiver with all digital delay-locked loop. 194-195 - JunYoung Kweon, JunTae Choi, Yun-Heup Song, Tony Tae-Hyoung Kim:
Leakage Control System Using Data Estimation of Resistive Memory. 196-197 - Sungick Kong, Sang-Seol Lee, Sung-Joon Jang:
Stereo vision-based Collision Avoidance for Unmanned Systems. 204-205 - Thathupara Subramanyan Kavya, Erdenetuya Tsogtbaatar, Young-Min Jang, Sang-Bock Cho:
Night-time Vehicle Detection Based on Brake/Tail Light Color. 206-207 - Mangi Han, Ji Min Song, Hoon-Gee Yang, Youngmin Kim:
Implementation of Multi-Channel FM Repeater using Digital Signal Processing Algorithm in FPGA. 208-209 - Tram Thi Bao Nguyen, Hanho Lee:
Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture. 210-211 - Hossein Moradian, Sujeong Jo, Kiyoung Choi:
Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators. 212-213 - Geun-Jun Kim, Bongsoon Kang:
A Method of Prevent Loss of Information in Ill-Posed Problem Based Application using Atmospheric Scattering Model. 214-215 - Yeon-Jin Kim, Ho-Yun Lee, Jin-Gyun Chung:
4-Bit Data Arrangement Algorithm for CAN Compression. 216-217 - Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing. 218-219 - Jae Hyeon Park, Jeong Hyeon Kim, Sung In Cho:
The Analysis of CNN Structure for Image Denoising. 220-221 - Jeong Hyeon Kim, Jae Hyeon Park, Sung In Cho:
Optimized Image Crop-based Video Retargeting. 224-225 - Wei Liu, Wei Li, Sang Un Park, Yong Beom Cho:
High-throughput HW-SW implementation for MV-HEVC decoder. 226-228 - Hounghun Joe, Manhee Cho, Youngmin Kim:
Accurate Stochastic Computing Using a Wire Exchanging Unipolar Multiplier. 229-230 - Hoyoung Yu, Youngmin Kim:
True Random Number Generator Using Bio-related Signals in Wearable Devices. 231-232 - Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique. 233-234 - M. Sultan M. Siddiqui, Ruchi Sharma, Van Loi Le
A Radiation Hardened SRAM with Self-refresh and Compact Error Correction. 235-236 - Kyunghyun Lim, Minsoo Choi, Myat Thu Linn Aung, Kyunghwan Kim, Ji-Seong Kim, Rock-Hyun Baek, Ho-Jin Song
Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects. 239-240 - Taeryoung Seol
A Wearable Electrocardiogram Monitoring System Robust to Motion Artifacts. 241-242 - Yunfan Chen
Infrared and Visible Image Fusion using Multi-Scale Decomposition and Visual Saliency Map. 243-244 - Jehong An, Yunfan Chen
Weather Classification using Convolutional Neural Networks. 245-246 - Prateek Manocha, Ayush Kumar, Jameel Ahmed Khan, Hyunchul Shin:
Korean Traffic Sign Detection Using Deep Learning. 247-248 - Donghee Han, Hyo Bin Choi, Yong Sin Kim:
Design of Road Surface Lighting System for Rear Lamp using Automotive Ultrasonic Sensor. 249-250 - Bruce C. Kim, Sang-Bock Cho:
Design of 3D Inductors for IoT Security. 251-252 - Kamilya Smagulova
Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection. 253-254 - Jeongsoo Park
A Ka-band low noise amplifier in 0.15μm GaAs E-mode pHEMT technology. 255-256 - Hui Dong Lee, Sunwoo Kong, Bonghyuk Park, Kwang Chun Lee, Jeong-Soo Park
A 28-GHz 28.5-dBm power amplifier using 0.15-µm InGaAs E-mode pHEMT technology. 257-258 - Donggu Lee, Taejong Kim, Sinyoung Kim, Kanghyeon Byun, Kuduck Kwon:
A CMOS Rectifier with 72.3% RF-to-DC Conversion Efficiency Employing Tunable Impedance Matching Network for Ambient RF Energy Harvesting. 259-260 - Kyungnam Lee, Youngmin Kim:
Design and Analysis of Digital PID Controller in MCU and FPGA. 261-262 - Min-Cheol Kim, Kwang-Yeob Lee:
Optimal Model Analysis for Denoising Monte Calro Rendering Noise. 263-264 - Hyeonchan Lim, Seokjun Jang, Sungho Kang:
A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain. 265-266 - Heetae Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang:
Low Power Scan Chain Architecture Based on Circuit Topology. 267-268 - Ju Sung Kim, Jeong Beom Hong, Ju Yeon Kang, Tae Hee Han:
Lifetime Improvement Method using Threshold-based Partial Data Compression in NoC. 269-270 - Jaehyun Kim, Chaeun Lee, Kiyoung Choi:
Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks. 271-272 - Sang Un Park, Tae Pyeong Kim, Mee Zee Lee, Yong Beom Cho:
Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL. 273-274
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