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Yeong-Jar Chang
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2020 – today
- 2021
- [j4]Jai-Ming Lin
, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 985-997 (2021) - [j3]Jai-Ming Lin
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1652-1664 (2021)
2010 – 2019
- 2019
- [c11]Lih-Yih Chiou, Tsung-Han Yang, Jian-Tang Syu, Che-Pin Chang, Yeong-Jar Chang:
Intelligent Policy Selection for GPU Warp Scheduler. AICAS 2019: 302-303 - 2018
- [c10]Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. ICCAD 2018: 1:1-1:8 - [c9]Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu:
Fast Steady-State Thermal Analysis. ISOCC 2018: 15-16 - 2010
- [j2]Yu-Shih Su, Wing-Kai Hon
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1921-1930 (2010)
2000 – 2009
- 2009
- [c8]Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang:
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ICCAD 2009: 535-538 - [c7]Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang:
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process. ISCAS 2009: 2281-2284 - 2008
- [c6]Chung-Fu Lin, Chia-Fu Huang, De-Chung Lu, Chih-Chiang Hsu, Wen-Tsung Chiu, Yu-Wei Chen, Yeong-Jar Chang:
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances. ITC 2008: 1 - 2005
- [c5]Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu:
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. Asian Test Symposium 2005: 106-111 - 2004
- [c4]Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang:
Fail Pattern Identification for Memory Built-In Self-Repair. Asian Test Symposium 2004: 366-371 - [c3]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli. ITC 2004: 124-133 - [c2]Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu:
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. MTDT 2004: 65-69 - 2000
- [j1]Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su:
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000)
1990 – 1999
- 1994
- [c1]Yeong-Jar Chang, Chung-Len Lee:
Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic. ISMVL 1994: 35-41
Coauthor Index
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