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ISCA Workshops 2010: Saint-Malo, France
- Ana Lucia Varbanescu, Anca Mariana Molnos, Rob van Nieuwpoort
:
Computer Architecture - ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers. Lecture Notes in Computer Science 6161, Springer 2012, ISBN 978-3-642-24321-9
A4MMC: Applications for Multi- and Many-Cores
- Michael Lange, Tony Field:
Accelerating Agent-Based Ecosystem Models Using the Cell Broadband Engine. 1-12 - Jörg Keller, Ana Lucia Varbanescu:
Performance Impact of Task Mapping on the Cell BE Multicore Processor. 13-23 - Motohiro Takayama, Ryuji Sakai:
Parallelization Strategy for CELL TV. 24-27 - Ben van Werkhoven
Towards User Transparent Parallel Multimedia Computing on GPU-Clusters. 28-39 - Stephen M. Kofsky, Daniel R. Johnson, John A. Stratton, Wen-mei W. Hwu, Sanjay J. Patel, Steven S. Lumetta:
Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture. 40-51 - Shams A. H. Al Umairy, Alexander S. van Amesfoort, Irwan D. Setija, Martijn C. van Beurden, Henk J. Sips:
On the Use of Small 2D Convolutions on GPUs. 52-64 - Milan Pavlovic, Yoav Etsion, Alex Ramírez:
Can Manycores Support the Memory Requirements of Scientific Applications? 65-76 - David J. Meder, Walter F. Tichy:
Parallelizing an Index Generator for Desktop Search. 77-85
AMAS-BT: 3rd Workshop on Architectural and Micro-Architectural Support for Binary Translation
- Martha A. Kim
Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks. 86-98 - João Paulo Porto, Guido Araujo, Edson Borin, Youfeng Wu:
Trace Execution Automata in Dynamic Binary Translation. 99-116 - Maxwell Souza, Daniel Nicácio, Guido Araujo:
ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation. 117-138
EAMA: 3rd Workshop for Emerging Applications and Many-Core Architectures
- Matthew A. Goodrum, Michael J. Trotter, Alla Aksel, Scott T. Acton, Kevin Skadron
Parallelization of Particle Filter Algorithms. 139-149 - Mark Moir, Daniel Nussbaum:
What Kinds of Applications Can Benefit from Transactional Memory? 150-160 - Christian Bienia, Kai Li:
Characteristics of Workloads Using the Pipeline Programming Model. 161-171
WEED: 2nd Workshop on Energy Efficient Design
- Laura Keys, Suzanne Rivoire, John D. Davis:
The Search for Energy-Efficient Building Blocks for the Data Center. 172-182 - Sabyasachi Ghosh, Mark Redekopp, Murali Annavaram
KnightShift: Shifting the I/O Burden in Datacenters to Management Processor for Energy Efficiency. 183-197 - Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram
Guarded Power Gating in a Multi-core Setting. 198-210 - Ali Shafiee, Narges Shahidi, Amirali Baniasadi:
Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors. 211-221 - Hrishikesh Amur, Karsten Schwan:
Achieving Power-Efficiency in Clusters without Distributed File System Complexity. 222-232 - Heather Hanson, Karthick Rajamani:
What Computer Architects Need to Know about Memory Throttling. 233-242 - William Lloyd Bircher, Lizy K. John:
Predictive Power Management for Multi-core Processors. 243-255
WIOSCA: 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture
- Nadav Amit
IOMMU: Strategies for Mitigating the IOTLB Bottleneck. 256-274 - David W. Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian:
Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality. 275-292 - Mel Gorman, Patrick Healy:
Performance Characteristics of Explicit Superpage Support. 293-310 - Mojtaba Sabeghi, Koen Bertels:
Interfacing Operating Systems and Polymorphic Computing Platforms Based on the MOLEN Programming Paradigm. 311-323 - Marios Kleanthous, Yiannakis Sazeides, Marios D. Dikaiakos:
Extrinsic and Intrinsic Text Cloning. 324-340 - Priyanka Tembey, Ada Gavrilovska, Karsten Schwan:
A Case for Coordinated Resource Management in Heterogeneous Multicore Platforms. 341-356 - Boris Grot
Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors. 357-375
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