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ICCAD 1991: Santa Clara, California, USA
- 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers. IEEE Computer Society 1991, ISBN 0-8186-2157-5
Physical Partitioning
- Chuck Kring, A. Richard Newton:
A Cell-Replicating Approach to Minicut-Based Circuit Partitioning. 2-5 - Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
On Clustering for Minimum Delay/Area. 6-9 - Lars W. Hagen, Andrew B. Kahng:
Fast Spectral Methods for Ratio Cut Partitioning and Clustering. 10-13
Analog Simulation
- Jaidip Singh, Resve A. Saleh:
iMACSIM: A Program for Multi-Level Analog Circuit Simulation. 16-19 - Luís Miguel Silveira, Jacob White, Steven B. Leeb:
A Modified Envelope-Following Approach to Clocked Analog Circuit Simulation. 20-23 - David Bedrosian, Jirí Vlach:
An Accelerated Steady-State Method for Networks with Internally Controlled Switches. 24-27
Controller Synthesis
- James J. Kim, Fadi J. Kurdahi, Nohbyung Park:
Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths. 30-33 - Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski:
Layout-Area Models for High-Level Synthesis. 34-37 - Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu:
Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. 38-41
Placement
- Tong Gao, Pravo M. Vaidya, C. L. Liu:
A New Performance Driven Placement Algorithm. 44-47 - Arvind Srinivasan, Kamal Chaudhary, Ernest S. Kuh:
RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. 48-51 - Ching-Ting Wu, Andrew Lim, David Hung-Chang Du:
Wafer Packing for Full Mask Exposure Fabrication. 52-55 - Sang-Gil Choi, Chong-Min Kyung:
A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping. 56-59
Interconnect Simulation
- Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson:
An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation. 62-65 - Dong H. Xie, Michel S. Nakhla:
Delay and Crosstalk Simulation of High-Speed VLSI Interconnects with Nonlinear Terminations. 66-69 - Hansruedi Heeb, Albert E. Ruehli:
Retarded Models for PC Board Interconnects - Or How the Speed of Light Affects your SPICE Circuit Simulation. 70-73 - Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage:
Evaluating RC-Interconnect Using Moment-Matching Approximations. 74-77
Scheduling
- Reinaldo A. Bergamaschi:
The Effects of False Paths in High-Level Synthesis. 80-83 - Taewhan Kim, Jane W.-S. Liu, C. L. Liu:
A Scheduling Algorithm for Conditional Resource Sharing. 84-87 - Miodrag Potkonjak, Jan M. Rabaey:
Optimizing Resource Utilization Using Transformations. 88-91 - Loganath Ramachandran, Daniel Gajski:
An Algorithm for Component Selection in Performance Optimized Scheduling. 92-95
Module Generation
- T. W. Her, D. F. Wong
:
Optimal Module Implementation and Its Application to Transistor Placement. 98-101 - Amnon Baron Cohen, Michael Shechory:
Track Assignment in the Pathway Datapath Layout Assembler. 102-105 - H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok:
Flexible Block-Multiplier Generation. 106-109
Numerical Algorithms
- Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern:
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications. 112-115 - Andrew Lumsdaine, Mark W. Reichelt, Jacob K. White:
Conjugate Direction Waveform Methods for Transient Two-Dimensional Simulation for MOS Devices. 116-119 - Chun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng:
Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation. 120-123
Topics in Logic Synthesis
- Yosinori Watanabe, Robert K. Brayton:
Heuristic Minimazation of Multiple-Valued Relations. 126-129 - Arlindo L. Oliveira, Alberto L. Sangiovanni-Vincentelli:
LSAT-An Algorithm for the Synthesis of Two Level Threshold Gate Networks. 130-133 - Massoud Pedram, Narasimha B. Bhat:
Layout Driven Logic Restructuring/Decomposition. 134-137
Real World Framework Applications
- Amir Milo, Smadar Nehab:
Data Framework for VLSI Design. 140-143 - Mahesh Mehendale, P. Murugavel, M. Poornima:
SLIM: A System for ASIC Library Management. 144-147 - Klaus D. Müller-Glaser, K. Kirsch, Karl Neusinger:
Estimating Essential Design Characteristics to Support Project Planning for ASIC Design Management. 148-151 - Mani B. Srivastava, Robert W. Brodersen:
Rapid-Prototyping of Hardware and Software in a Unified Framework. 152-155
Reliability and Manufacturability Analysis
- Peter Feldmann, Stephen W. Director:
Improved Methods for IC Yield and Quality Optimization Using Surface Integrals. 158-161 - Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang:
New Simulation Methods for MOS VLSI Timing and Reliability. 162-165 - Kurt Antreich, Helmut E. Graeb:
Circuit Optimization Driven by Worst-Case Distances. 166-169 - M. A. Styblinski, J. C. Zhang:
Circuit Performance Variability Reduction: Principles, Problems, and Practical Solutions. 170-173
Timing Analysis and Performance Optimization
- Srinivas Devadas, Kurt Keutzer, Sharad Malik
Delay Computation in Combinational Logic Circuits: Theory and Algorithms. 176-179 - Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. 180-183 - Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni:
Performance Enhancement through the Generalized Bypass Transform. 184-187 - Hervé J. Touati, Hamid Savoj, Robert K. Brayton:
Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. 188-191
Diagnostics and Testability Analysis
- Torsten Grüning, Udo Mahlstedt, Hartmut Koopmeiners:
DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits. 194-197 - M. Marzouki, F. L. Vargas:
Knowledge-Based Debugging of ASICs: Real Case Study and Performance Analysis. 198-201 - Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab:
BETA: Behavioral Testability Analysis. 202-205
The False Path Problem in Timing Analysis
- Hsi-Chuan Chen, David Hung-Chang Du:
Path Sensitization in Critical Path Problem. 208-211 - João P. Marques Silva, Karem A. Sakallah, Luís M. Vidigal:
FPD - An Environment for Exact Timing Analysis. 212-215 - Shiang-Tang Huang, Tai-Ming Parng, Jyuo-Min Shyu:
A New Approach to Solving False Path Problem in Timing Analysis. 216-219
Encoding Algorithms
- Christopher Duff, Gabriele Saucier:
State Assignment Based on the Reduced Dependency Theory and Recent Experimental Results. 222-225 - Biswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri:
A Flexible Scheme for State Assignment Based on Characteristics of the FSM. 226-229 - David Binger, David Knapp:
Encoding Multiple Outputs for Improved Column Compaction. 230-233
Built-In Self Test
- Debaditya Mukherjee, Charles Njinda, Melvin A. Breuer:
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware. 236-239 - Chien-In Henry Chen:
BISTSYN - A Built-In Self-Test Synthesizer. 240-243 - Warren H. Debany Jr., Carlos R. P. Hartmann, Pramod K. Varshney, Kishan G. Mehrotra:
Comparison of Random Test Vector Generation Strategies. 244-247 - Vladimir Castro Alves, Michael Nicolaidis, P. Lestrat, Bernard Courtois:
Built-In Self-Test for Multi-Port RAMs. 248-251
Framework Directions
- Jay B. Brockman, Stephen W. Director:
The Hercules CAD Task Management System. 254-257 - Moon-Jung Chung, Sangchul Kim:
The Configuration Management for Version Control in an Object-Oriented VHDL Design Environment. 258-261 - Jukka Lahti, Matti Sipola, Jorma Kivelä:
SADE: A Graphical Tool for VHDL-Based System Analysis. 262-265 - Sanjiv Narayan, Frank Vahid, Daniel Gajski:
System Specification and Synthesis with the SpecCharts Language. 266-269
Techniques for Effective Memory Utilization
- Jan Vanhoof, Ivo Bolsens, Hugo De Man:
Compiling Multi-Dimensional Data Streams into Distributed DSP ASIC Memory. 272-275 - Imtiaz Ahmad, C. Y. Roger Chen:
Post-Processor for Data Path Synthesis Using Multiport Memories. 276-279 - Francis Depuydt, Gert Goossens, Hugo De Man:
Clustering Techniques for Register Optimization During Scheduling Preprocessing. 280-283 - Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers:
Scheduling in Programmable Video Signal Processors. 284-287
High-Level Layout Verification
- Georg Pelz, Uli Roettcher:
Circuit Comparison by Hierarchical Pattern Matching. 290-293 - Keh-Jeng Chang, Soo-Young Oh, Ken Lee:
HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs. 294-297 - Takeshi Yoshitome:
Hierarchical Analyzer for VLSI Power Supply Networks Based on a New Reduction Method. 298-301
Timing Analysis
- Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff:
Automatic Detection of MOS Synchronizers for Timing Verification. 304-307 - Ronald B. Stewart, Jacques Benkoski:
Static Timing Analysis Using Interval Constraints. 308-311 - Li-Ren Liu, Hsi-Chuan Chen, David Hung-Chang Du:
The Calculation of Signal Stable Ranges in Combinational Circuits. 312-315
Asynchronous Circuit Synthesis
- Steven M. Nowick, David L. Dill:
Automatic Synthesis of Locally-Clocked Asynchronous State Machines. 318-321 - Cho W. Moon, Paul R. Stephan, Robert K. Brayton:
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. 322-325 - Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Synthesis for Testability Techniques for Asynchronous Circuits. 326-329
Performance Driven and Parallel Routing Techniques
- Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani:
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. 332-335 - Ren-Song Tsay:
Exact Zero Skew. 336-339 - Tsukasa Yamauchi, Akio Ishizuka, Toshiyuki Nakata, Nobuyuki Nishiguchi, Nobuhiko Koike:
PROTON: A Parallel Detailed Router on an MIMD Parallel Machine. 340-343 - Rajeev Jayaraman, Rob A. Rutenbar:
A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. 344-347
Topics in Simulation
- Randal E. Bryant:
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis. 350-353 - Andrew T. Yang, Yu-Hsu Chang:
Bipolar Timing Modeling Including Interconnects Based on Parametric Correction. 354-357 - Karim Khordoc, Mario Dufresne, Eduard Cerny:
A Stimulus/Response System Based on Hierarchical Timing Diagrams. 358-361 - Frank Vahid, Daniel Gajski:
Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. 362-365
Sequential Synthesis and Verification
- Andreas Münzner, Günter Hemme:
Converting Combinational Circuits into Pipelined Data Paths. 368-371 - Kwang-Ting Cheng:
An ATPG-Based Approach to Sequential Logic Optimization. 372-375 - Carl Pixley, Gary Beihl:
Calculating Resetability and Reset Sequences. 376-379 - Filip Van Aelten, Jonathan Allen, Srinivas Devadas:
Verification of Relations Between Synchronous Machines. 380-383
Analog Circuit and Layout Synthesis
- Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli, Georges G. E. Gielen
A Behavioral Representation for Nyquist Rate A/D Converters. 386-389 - Prabir C. Maulik, L. Richard Carley:
Automating Analog Circuit Design using Constrained Optimization Techniques. 390-393 - John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley:
Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. 394-397
Scan Design
- Vivek Chickermane, Janak H. Patel:
A Fault Oriented Partial Scan Design Approach. 400-403 - Jing-Yang Jou, Kwang-Ting Cheng:
Timing-Driven Partial Scan. 404-407 - Rajesh Gupta, Melvin A. Breuer:
Ordering Storage Elements in a Single Scan Chain. 408-411
High-Level Synthesis - FSM Synthesis
- James H. Kukula, Srinivas Devadas:
Finite State Machine Decomposition by Transition Pairing. 414-417 - June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi:
Don't Care Sequences and the Optimization of Interacting Finite State Machines. 418-421 - Keisuke Bekki, Tohru Nagai, Nobuhiro Hamada, Tsuguo Shimizu, Noriharu Hiratsuka, Kazumasa Shima:
An Automatic Finite State Machine Synthesis Using Temporal Logic Decomposition. 422-425
Detailed Routing
- Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh:
Algorithms for Three-Layer Over-The-Cell Channel Routing. 428-431 - Masayuki Terai, Kazuhiro Takahashi, Kazuo Nakajima, Koji Sato:
A New Model for Over-The-Cell Channel Routing with Three Layers. 432-435 - Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu:
A Channel Router for Single Layer Customization Technology. 436-439 - Cliff Yungchin Hou, C. Y. Roger Chen:
A Hierarchical Methodology to Improve Channel Routing by Pin Permutation. 440-443
Automatic Test Pattern Generation
- Dong-Ho Lee, Sudhakar M. Reddy:
A New Test Generation Method for Sequential Circuits. 446-449 - Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. 450-453 - Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy:
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. 454-457 - Jaushin Lee, Janak H. Patel:
A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation. 458-461
Verification Algorithms
- Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. 464-467 - Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham:
Probabilistic Design Verification. 468-471 - Nagisa Ishiura, Hiroshi Sawada, Shuzo Yajima:
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables. 472-475 - Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi:
Variable Ordering and Selection for FSM Traversal. 476-479
Transistor-Level Optimization and Layout
- Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya:
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. 482-485 - Edgar Auer, Werner L. Schiele, Georg Sigl:
A New Linear Placement Algorithm for Cell Generation. 486-489 - Katsunori Tani, Kyoichi Izumi, Masahiko Kashimura, Tsuneo Matsuda, Takashi Fujii:
Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits. 490-493
Design for Testability
- Sen-Pin Lin, Charles Njinda, Melvin A. Breuer:
A Systematic Approach for Designing Testable VLSI Circuits. 496-499 - Edwin Hsing-Mean Sha, Liang-Fang Chao:
Design for Easily Applying Test Vectors to Improve Delay Fault Coverage. 500-503 - Mark D. Sloan, William A. Rogers, Srihari Shoroff:
The Impedance Fault Model and Design for Robust Impedance Fault Testability. 504-507
Advances in Combinational Synthesis
- Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen:
Application of Boolean Unification to Combinational Logic Synthesis. 510-513 - Hamid Savoj, Robert K. Brayton, Hervé J. Touati:
Extracting Local Don't Cares for Network Optimization. 514-517 - Hamid Savoj, Robert K. Brayton:
Observability Relations and Observability Don't Cares. 518-521
Exact Algorithms in General Cell Routing
- Yang Cai, D. F. Wong
Minimizing Channel Density by Shifting Blocks and Terminals. 524-527 - Malgorzata Marek-Sadowska, Majid Sarrafzadeh:
The Crossing Distribution Problem. 528-531 - Moazzem Hossain, Naveed A. Sherwani:
On Topological Via Minimization and Routing. 532-535 - S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani:
Switchbox Steiner Tree Problem in Presence of Obstacles. 536-539
Fault Simulation
- Nikolaus Gouders, Reinhard Kaibel:
PARIS: A Parallel Pattern Fault Simulator for Synchronous Sequential Circuits. 542-545 - Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel:
Methods for Reducing Events in Sequential Circuit Fault Simulation. 546-549 - Noriyuki Takahashi, Nagisa Ishiura, Shuzo Yajima:
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets. 550-553 - Terry Lee, Ibrahim N. Hajj:
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. 554-557
Synthesis for FPGA's
- Masahiro Fujita, Yusuke Matsunaga:
Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. 560-563 - Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Improved Logic Synthesis Algorithms for Table Look Up Architectures. 564-567 - Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic:
Technology Mapping on Lookup Table-Based FPGAs for Performance. 568-571 - Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. 572-575
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