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31st FPL 2021: Dresden, Germany
- 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021. IEEE 2021, ISBN 978-1-6654-3759-2
- Jeffrey Chen, Sehwan Hong, Warrick He, Jinyeong Moon
, Sang-Woo Jun:
Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge. 1-8 - Jian Meng, Shreyas Kolala Venkataramanaiah, Chuteng Zhou, Patrick Hansen, Paul N. Whatmough, Jae-sun Seo:
FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. 9-16 - Shun Yan, Zhengyan Liu, Yun Wang, Chenglong Zeng, Qiang Liu, Bowen Cheng, Ray C. C. Cheung:
An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics. 17-23 - Atiyehsadat Panahi, Suhail Basalama, Ange-Thierry Ishimwe, Joel Mandebi Mbongue, David Andrews
A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications. 24-27 - Myat Thu Linn Aung, Chuping Qu, Liwei Yang, Tao Luo
DeepFire: Acceleration of Convolutional Spiking Neural Network on Modern Field Programmable Gate Arrays. 28-32 - Chen Wu, Jinming Zhuang, Kun Wang, Lei He:
MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks. 33-37 - Franz-Josef Streit, Paul Krüger, Andreas Becher
Choice - A Tunable PUF-Design for FPGAs. 38-44 - Gökhan Akgün, Muhammad Ali, Diana Göhringer
Power-Aware Computing Systems on FPGAs: A Survey. 45-51 - Vatistas Kostalabros, Jordi Ribes-González, Oriol Farràs
HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. 52-59 - Zhengtai Chang, Shanshan Shi, Binwei Song, Wenbing Fan, Yao Wang:
Modeling Attack Resistant Arbiter PUF with Time-Variant Obfuscation Scheme. 60-63 - Shikha Goel, M. Balakrishnan, Rijurekha Sen:
EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPU. 64-68 - Duc-Minh Ngo, Andriy Temko, Colin C. Murphy, Emanuel M. Popovici:
FPGA Hardware Acceleration Framework for Anomaly-based Intrusion Detection System in IoT. 69-75 - Anupreetham Anupreetham
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. 76-82 - Enrico Calore, Sebastiano Fabio Schifano:
Performance assessment of FPGAs as HPC accelerators using the FPGA Empirical Roofline. 83-90 - Yunhui Qiu, Wenbo Yin, Lingli Wang:
A High-performance Open-channel Open-way NAND Flash Controller Architecture. 91-98 - Sumesh Kumar, Fahad Saeed:
Communication-avoiding micro-architecture to compute Xcorr scores for peptide identification. 99-103 - Michael Hart, John McAllister, Leo Rogers, Charles Gillan:
An Emulation of Quantum Error-Correction on an FPGA device. 104-108 - Daouda Diakite
OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration. 109-114 - Tian Ye, Sanmukh R. Kuppannagari
Performance Modeling and FPGA Acceleration of Homomorphic Encrypted Convolution. 115-121 - Sanjay Deshpande, Santos Merino Del Pozo
Modular Inverse for Integers using Fast Constant Time GCD Algorithm and its Applications. 122-129 - Martin Langhammer, Simon Finn, Sergey Gribok, Bogdan Pasca
Dense FPGA Compute Using Signed Byte Tuples. 130-138 - Philippos Papaphilippou
Demonstrating custom SIMD instruction development for a RISC-V softcore. 139 - Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou:
DO-GPU: Domain Optimizable Soft GPUs. 140-144 - Sarah L. Harris, Daniel Chaver
RVfpga: Using a RISC-V Core Targeted to an FPGA in Computer Architecture Education. 145-150 - Abbas Haghi, Santiago Marco-Sola, Lluc Alvarez, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó:
An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment. 151-159 - Thomas Mauldin, Zhenyu Xu, Tao Wei:
Minimal Overhead Optical Time-Domain Reflectometer Via I/O Integrated Data Converter Enabled by Field Programmable Voltage Offset. 160-166 - Nobuho Hashimoto, Shinya Takamaeda-Yamazaki:
An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. 167-173 - David Castells-Rufas
OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. 174-178 - Anh Hoang Ngoc Nguyen
An FPGA-based Stochastic SAT Solver Leveraging Inter-Variable Dependencies. 179-184 - Emilien Fournier, Ciprian Teodorov, Loïc Lagadec:
Carnac: Algorithm Variability for Fast Swarm Verification on FPGA. 185-189 - Fei Wen
An FPGA-based Hybrid Memory Emulation System. 190-196 - Zhenhao He, Dario Korolija, Gustavo Alonso:
EasyNet: 100 Gbps Network for HLS. 197-203 - Prajith Ramakrishnan Geethakumari, Ioannis Sourdis:
A Specialized Memory Hierarchy for Stream Aggregation. 204-210 - Chunyou Su, Hao Liang, Wei Zhang, Kun Zhao, Baole Ai, Wenting Shen, Zeke Wang:
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators. 211-218 - Arish Sateesan
Speed Records in Network Flow Measurement on FPGA. 219-224 - Stefan Nikolic
Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. 225-233 - Yuhang Shen, Jiadong Qian, Kaichuang Shi
Two-level MUX Design and Exploration in FPGA Routing Architecture. 234-241 - Minghua Shen, Nong Xiao:
Load Balance-Centric Distributed Parallel Routing for Large-Scale FPGAs. 242-248 - Cornelia Wulf, Michael Willig, Diana Göhringer
A Survey on Hypervisor-based Virtualization of Embedded Reconfigurable Systems. 249-256 - Arzhang Rafii, Welson Sun, Paul Chow:
Pharos: a Multi-FPGA Performance Monitor. 257-262 - Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris
Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators. 263-264 - Ahmed Kamaleldin, Diana Göhringer
Design For Agility: A Modular Reconfigurable Platform for Heterogeneous Many-Core Architectures. 265-266 - Florian Fricke:
A Novel Top to Bottom Toolchain For Generating Virtual Coarse-Grained Reconfigurable Arrays. 267-268 - Ariel Podlubne, Diana Göhringer
Reconfigurable Computing Systems as Component-oriented Designs for Robotics. 269-270 - Emmanouil Kavvousanos, Vassilis Paliouras
Optimizing Deep Learning Decoders for FPGA Implementation. 271-272 - Jens Rettkowski, Diana Göhringer
Wormhole Computing in Networks-on-Chip. 273-274 - Keyvan Shahin
Accelerating Fixed-Point Simulations Using Width Reconfigurable Hardware Architectures. 275-276 - Hector Gerardo Muñoz Hernandez:
Towards the Efficient Multi-Platform Execution of Deep Neural Networks. 277-278 - Yu Zhu, Zhenhao He, Wenqi Jiang, Kai Zeng, Jingren Zhou, Gustavo Alonso:
Distributed Recommendation Inference on FPGA Clusters. 279-285 - Sathish Panchapakesan, Zhenman Fang, Jian Li:
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs. 286-293 - Duvindu Piyasena, Siew-Kei Lam, Meiqing Wu:
Accelerating Continual Learning on Edge FPGA. 294-300 - Linqiao Liu, Stephen Brown:
Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures. 301-305 - Hasan Irmak, Daniel Ziener, Nikolaos Alachiotis:
Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. 306-311 - Ameer M. S. Abdelhadi, He Li:
Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs. 312-318 - Alexander Klemd, Bernd Klauer, Johannes Timmermann, Delf Sachau:
A Flexible Multi-Channel Feedback FxLMS Architecture for FPGA Platforms. 319-326 - Grace Zgheib, Yu Shen Lu, Ilya Ganusov:
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. 327-333 - Jin Hee Kim, Jason Helge Anderson:
Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. 334-340 - Jianyi Cheng, John Wickerson, George A. Constantinides:
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. 341-346 - Nikhil Pratap Ghanathe, Vivek Seshadri, Rahul Sharma, Steve Wilton, Aayan Kumar:
MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications. 347-354 - Aman Arora
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research. 355-362 - Jonas Ney, Dominik Marek Loroch, Vladimir Rybalkin, Nico Weber, Jens Krüger, Norbert Wehn:
HALF: Holistic Auto Machine Learning for FPGAs. 363-368 - Behnam Ghavami, Milad Ibrahimipour, Zhenman Fang, Lesley Shannon:
MAPLE: A Machine Learning based Aging-Aware FPGA Architecture Exploration Framework. 369-373 - Marcelo Brandalero, Mitko Veleski, Hector Gerardo Muñoz Hernandez, Muhammad Ali, Laurens Le Jeune, Toon Goedemé
AITIA: Embedded AI Techniques for Industrial Applications. 374-375 - Konstantina Koliogeorgi, Fekhr Eddine Keddous, Dimosthenis Masouros, Antony Chazapis
FPGA acceleration in EVOLVE's Converged Cloud-HPC Infrastructure. 376-377 - Nikolaos Bellas, Christos D. Antonopoulos, Spyros Lalis, Maria Rafaela Gkeka, Alexandros Patras, Georgios Keramidas, Iakovos Stamoulis, Nikolaos Tavoularis, Stylianos Piperakis, Emmanouil Hourdakis, Panos E. Trahanias, Paul Zikas, George Papagiannakis, Ioanna Kartsonaki
Architectures for SLAM and Augmented Reality Computing. 378-379 - Philipp S. Käsgen, Mohamed Messelka, Markus Weinhardt:
HiPReP: High-Performance Reconfigurable Processor - Architecture and Compiler. 380-381 - Jürgen Becker, Leonard Masing, Tobias Dörr, Florian Schade, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems. 382-383 - Angelos S. Voros, Christos Panagiotou, Stavros Zogas, Georgios Keramidas, Christos P. Antonopoulos, Michael Hübner, Nikolaos S. Voros
The SMART4ALL High Performance Computing Infrastructure: Sharing high-end hardware resources via cloud-based microservices. 384-385 - Fritjof Steinert
Demonstration of a Distributed Accelerator Framework for Energy-efficient ML Processing. 386 - David Northcote, Lewis D. McLaughlin, Louise H. Crockett, Robert W. Stewart:
Capture and Visualisation of Radio Signals with an Open Source, Single Chip Spectrum Analyser. 387 - Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich:
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. 388 - Marc Perelló Bacardit, Behzad Salami:
Reduced-voltage OmpSs@FPGA: A Demonstration. 389 - Nupur Sumeet, Manoj Nambiar:
HLS_PRINT: High Performance Logging Framework on FPGA. 390 - Philippos Papaphilippou
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. 391-397 - Joanna Stanisz
Hardware-software implementation of a DNN for 3D object detection using FINN - a demo. 398 - Friedrich Bauer, Felix Braun, Daniel Hauer, Axel Jantsch, Markus D. Kobelrausch, Martin Mosbeck, Nima Taherinejad, Philipp-Sebastian Vogt
MELODI: An Online Platform for Mass Education of Digital Design - HDL to Remote FPGA. 399 - Xifan Tang, Ganesh Gore, Grant Brown, Pierre-Emmanuel Gaillardon:
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. 400 - Marcin Kowalczyk
A comparison of real-time 4K/UltraHD connected component labelling architectures. 401 - Gökhan Akgün, Diana Göhringer
Power-Aware Real-Time Operating Systems on Reconfigurable Architectures. 402-403 - Nathaniel Peura, Yuan Meng
FGYM: Toolkit for Benchmarking FPGA based Reinforcement Learning Algorithms. 404 - Dominika Przewlocka-Rus
Quantised Siamese Tracker for 4K/UltraHD Video Stream - a demo. 405 - Jing Yu, Andrew Attwood, Nguyen Dao, Dirk Koch:
The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running Bitsteams. 406
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