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Jianyi Cheng
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2020 – today
- 2024
- [c16]Jianyi Cheng
, Samuel Coward
SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting. ASPLOS (2) 2024: 1029-1044 - [c15]Zhewen Yu, Sudarshan Sreeram, Krish Agrawal, Junyi Wu, Alexander Montgomerie-Corcoran, Cheng Zhang, Jianyi Cheng, Christos-Savvas Bouganis, Yiren Zhao:
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator. FPL 2024: 257-263 - [c14]Cheng Zhang, Jianyi Cheng, George Anthony Constantinides, Yiren Zhao:
LQER: Low-Rank Quantization Error Reconstruction for LLMs. ICML 2024 - [i12]Cheng Zhang, Jianyi Cheng, George A. Constantinides, Yiren Zhao:
LQER: Low-Rank Quantization Error Reconstruction for LLMs. CoRR abs/2402.02446 (2024) - [i11]Zhewen Yu, Sudarshan Sreeram
HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator. CoRR abs/2406.03088 (2024) - [i10]Zeyu Cao, Cheng Zhang, Pedro Gimenes, Jianqiao Lu, Jianyi Cheng, Yiren Zhao:
Scaling Laws for Mixed quantization in Large Language Models. CoRR abs/2410.06722 (2024) - 2023
- [j6]Jianyi Cheng
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets. IEEE Trans. Computers 72(11): 3300-3313 (2023) - [j5]Jianyi Cheng
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(4): 55:1-55:32 (2023) - [c13]Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao:
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? EMNLP 2023: 9988-10006 - [c12]Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis:
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. FPL 2023: 288-293 - [i9]Alexander Montgomerie-Corcoran, Zhewen Yu, Jianyi Cheng, Christos-Savvas Bouganis:
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration. CoRR abs/2307.07821 (2023) - [i8]Jianyi Cheng, Cheng Zhang, Zhewen Yu, Alexander Montgomerie-Corcoran, Can Xiao, Christos-Savvas Bouganis, Yiren Zhao:
Fast Prototyping Next-Generation Accelerators for New ML Models using MASE: ML Accelerator System Exploration. CoRR abs/2307.15517 (2023) - [i7]Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane:
SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR. CoRR abs/2308.07654 (2023) - [i6]Aditya Rajagopal, Diederik Adriaan Vink, Jianyi Cheng, Yann Herklotz:
GSA to HDL: Towards principled generation of dynamically scheduled circuits. CoRR abs/2308.11048 (2023) - [i5]Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao:
Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? CoRR abs/2310.05079 (2023) - 2022
- [j4]Jianyi Cheng
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71(4): 933-946 (2022) - [j3]Jianyi Cheng
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 628-641 (2022) - [c11]Jianyi Cheng, John Wickerson, George A. Constantinides:
Dynamic C-Slow Pipelining for HLS. FCCM 2022: 1-10 - [c10]Jianyi Cheng, John Wickerson, George A. Constantinides:
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. FPGA 2022: 89-100 - [c9]Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides:
POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL 2022: 235-242 - [c8]Jianyi Cheng, Lana Josipovic
Dynamic Inter-Block Scheduling for HLS. FPL 2022: 243-252 - [c7]Xuefei He, Jianyi Cheng, George A. Constantinides:
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. FPT 2022: 1-4 - [c6]Hanchen Ye
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. HPCA 2022: 741-755 - 2021
- [c5]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Scheduling in High-Level Synthesis. FCCM 2021: 195-203 - [c4]Jianyi Cheng, John Wickerson, George A. Constantinides:
Probabilistic Optimization for High-Level Synthesis. FPGA 2021: 145 - [c3]Jianyi Cheng, John Wickerson, George A. Constantinides:
Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. FPL 2021: 341-346 - [i4]Yijiang Lian, Yubo Liu, Zhicong Ye, Liang Yuan, Yanfeng Zhu, Min Zhao, Jianyi Cheng, Xinwei Feng:
A Concept Knowledge-Driven Keywords Retrieval Framework for Sponsored Search. CoRR abs/2102.10560 (2021) - [i3]Ruizhe Zhao, Jianyi Cheng:
Phism: Polyhedral High-Level Synthesis in MLIR. CoRR abs/2103.15103 (2021) - [i2]Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen:
ScaleHLS: Scalable High-Level Synthesis through MLIR. CoRR abs/2107.11673 (2021) - 2020
- [c2]Jianyi Cheng, Lana Josipovic
Combining Dynamic & Static Scheduling in High-level Synthesis. FPGA 2020: 288-298
2010 – 2019
- 2019
- [c1]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides:
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA 2019: 142-151 - 2017
- [j2]Bin He, Bin Dong, Yi Guan, Jinfeng Yang, Zhipeng Jiang, Qiubin Yu, Jianyi Cheng, Chunyan Qu:
Building a comprehensive syntactic and semantic corpus of Chinese clinical texts. J. Biomed. Informatics 69: 203-217 (2017) - 2016
- [i1]Bin He, Bin Dong, Yi Guan, Jinfeng Yang, Zhipeng Jiang, Qiubin Yu, Jianyi Cheng, Chunyan Qu:
Building a comprehensive syntactic and semantic corpus of Chinese clinical texts. CoRR abs/1611.02091 (2016) - 2015
- [j1]Bin He, Yi Guan, Jianyi Cheng, Keting Cen, Wenlan Hua:
CRFs based de-identification of medical records. J. Biomed. Informatics 58: S39-S46 (2015)
Coauthor Index
aka: George Anthony Constantinides
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