default search action
47th ESSDERC 2017: Leuven, Belgium
- 47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017. IEEE 2017, ISBN 978-1-5090-5978-2
- Ian A. Young, Dmitri E. Nikonov
:
Principles and trends in quantum nano-electronics and nano-magnetics for beyond-CMOS computing. 1-5 - Chihiro Matsui, Ken Takeuchi:
22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash. 6-9 - Takashi Inose, Seiichi Aritome, Ryutaro Yasuhara, Satoshi Mishima, Ken Takeuchi:
Study of error repeatability and recovery in 40nm TaOx ReRAM. 10-13 - Shan Wang, Huaqiang Wu, Bin Gao, Ning Deng, Dong Wu, He Qian:
Optimization of writing scheme on 1T1R RRAM to achieve both high speed and good uniformity. 14-17 - Rui Liu, Heng-Yuan Lee, Shimeng Yu
Analyzing inference robustness of RRAM synaptic array in low-precision neural network. 18-21 - Colin C. McAndrew:
SPICE modeling in Verilog-A: Successes and challenges: Invited paper. 22-25 - Chiara Rossi
SPICE modeling of light induced current in silicon with 'Generalized' lumped devices. 26-29 - C.-M. Zhang, Farzan Jazaeri, Alessandro Pezzotta, Claudio Bruschini
Total ionizing dose effects on analog performance of 28 nm bulk MOSFETs. 30-33 - Chhandak Mukherjee
1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. 34-37 - Markus Hellenbrand
Random telegraph signal noise in tunneling field-effect transistors with S below 60 mV/decade. 38-41 - Gia Vinh Luong, Sebastiano Strangio
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM. 42-45 - Benoit Sklénard
Advances in the understanding of microscopic switching mechanisms in ReRAM devices (Invited paper). 46-49 - Saurabh Sant, Andreas Schenk:
Modeling the effect of surface roughness on the performance of line tunnel FETs. 50-53 - Tarun Agarwal, Bart Soree
Material selection and device design guidelines for two-dimensional materials based TFETs. 54-57 - Rosario M. Incandela, Lin Song, Harald A. R. Homulle
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures. 58-61 - Arnout Beckers
Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing. 62-65 - Renan Trevisoli Doria
A new method for junctionless transistors parameters extraction. 66-69 - Mathieu Jaoul
Avalanche compact model featuring SiGe HBTs characteristics up to BVcbo. 70-73 - Gina C. Adam
Utilizing I-V non-linearity and analog state variations in ReRAM-based security primitives. 74-77 - Ali Saeidi, Farzan Jazaeri, Francesco Bellando, Igor Stolichnov
Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation. 78-81 - Thomas Grap, Felix Riederer, Charu Gupta
Buried multi-gate InAs-nanowire FETs. 82-85 - Enrique Miranda
Equivalent circuit model for the electron transport in 2D resistive switching material systems. 86-89 - Igor Bejenari, Michael Schröter, Martin Claus:
Analytical drain current model for non-ballistic Schottky-Barrier CNTFETs. 90-93 - Meshal Alawein
A general circuit model for spintronic devices under electric and magnetic fields. 94-97 - Matteo Ghittorelli
Compact physical model of a-IGZO TFTs for circuit simulation. 98-101 - Nicolo Oliva, Emanuele A. Casu, Wolfgang A. Vitale, Igor Stolichnov
Complementary black phosphorous FETs by workfunction engineering of pre-patterned Au and Ag embedded electrodes. 102-105 - Yashwanth Balaji
Tunneling transistors based on MoS2/MoTe2 Van der Waals heterostructures. 106-109 - Amit Gahoi, Satender Kataria, Max Christian Lemme
Temperature dependence of contact resistance for gold-graphene contacts. 110-113 - Takamasa Kawanago, Ryo Ikoma, Tomoaki Oba, Hiroyuki Takagi:
Radical oxidation process for hybrid SAM/HfOx gate dielectrics in MoS2 FETs. 114-117 - Roland Rupp:
CoolSiC™ and major trends in SiC power device development. 118-121 - B. Gunnar Malm, Hossein Elahipanah, Arash Salemi, Mikael Östling
Gated base structure for improved current gain in SiC bipolar technology. 122-125 - William Vandendaele, Thomas Lorin, Romain Gwoziecki, Yannick Baines, Jérome Biscarrat, Marie-Anne Jaud, Charlotte Gillot, Matthew Charles
On the understanding of cathode related trapping effects in GaN-on-Si Schottky diodes. 126-129 - Arno Stockman, Michael J. Uren
Temperature dependent substrate trapping in AlGaN/GaN power devices and the impact on dynamic ron. 130-133 - Tanya Nigam, Andreas Kerber, Tian Shen, Rakesh Ranjan, Linjun Cao:
Material and device innovation impact on reliability for scaled CMOS technologies. 134-139 - Kyung Hwa Lee, Maryline Bawedin, Hyungjin Park, Mukta Singh Parihar, Sorin Cristoloveanu:
Carrier lifetime evaluation in FD-SOI layers. 140-143 - Jessy Micout, Quentin Rafhay, Xavier Garros, Mikaël Cassé, Jean Coignus
Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices. 144-147 - B. Kazemi Esfeh, Valeria Kilchytska
Back-gate bias effect on UTBB-FDSOI non-linearity performance. 148-151 - B. Attarimashalkoubeh, Jury Sandrini, Elmira Shahrabi, Yusuf Leblebici:
Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs. 152-155 - Giorgio Servalli:
Emerging memory technologies for high density applications. 156-159 - Milan Pesic, Michael Hoffmann, Claudia Richter, Stefan Slesazeck, Thomas Kämpfe
Anti-ferroelectric ZrO2, an enabler for low power non-volatile 1T-1C and 1T random access memories. 160-163 - Karine Florent, Simone Lavizzari, Luca Di Piazza, Mihaela Ioana Popovici, Goedele Potoms, Tom Raymaekers, Guido Groeseneken
From planar to vertical capacitors: A step towards ferroelectric V-FeFET integration. 164-167 - Naga Sruti Avasarala, Bogdan Govoreanu, Karl Opsomer, Wouter Devulder
Doped GeSe materials for selector applications. 168-171 - Behzad Zeinali
Multilevel SOT-MRAM cell with a novel sensing scheme for high-density memory applications. 172-175 - Fabian M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta:
On the ballistic ratio in 14nm-Node FinFETs. 176-179 - Luca Donetti, Carlos Sampedro
Three-dimensional multi-subband simulation of scaled FinFETs. 180-183 - Muhammad A. Elmessary
Study of strained effects in nanoscale GAA nanowire FETs using 3D Monte Carlo simulations. 184-187 - Jeffrey A. Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, P. R. Chidi Chidambaram, Suman Datta
Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. 188-191 - Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti
Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits. 192-195 - Muhammad Alshahed, M. Dakran, Lars Heuken, Mohammed Alomari, Joachim N. Burghartz:
Comprehensive compact electro-thermal GaN HEMT model. 196-199 - Apoorva Ojha, Nihar R. Mohapatra:
Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: A compact model. 200-203 - Francesco Maria Puglisi
A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design. 204-207 - Francesco Bonaccorso:
Ink-jet printed 2D crystal heterostructures. 208-211 - Tom Schram, Quentin Smets, Benjamin Groven
WS2 transistors on 300 mm wafers with BEOL compatibility. 212-215 - Mesut Inac, Grzegorz Lupina, Matthias Wietstruck, Marco Lisker, Mirko Fraschke, Andreas Mai
200 mm Wafer level graphene transfer by wafer bonding technique. 216-219 - Sung-Kun Park, Donghyun Woo, Min-Ki Na, Pyong-Su Kwag, Ho-Ryeong Lee, Kyoung-Wook Ro, Kyung-Hwan Kim, Dong-Kyu Lee, Chris Hong, In-Wook Cho, Kyung-Dong Yoo:
Epitaxial growth and diffusion characteristics analysis of vertical thin poly-Si channel transfer gate structured pixels for 3D CMOS image sensor. 220-223 - Wouter Diels, Michiel Steyaert
Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers. 224-227 - R. Pecheux, R. Kabouche, E. Dogmus, A. Linge, E. Okada, M. Zegaoui, F. Medjdoub:
Importance of buffer configuration in GaN HEMTs for high microwave performance and robustness. 228-231 - Emanuele A. Casu, Wolfgang A. Vitale, Michele Tamagnone, Mariazel Maqueda Lopez, Nicolo Oliva, Anna Krammer, Andreas Schuler, Montserrat Fernandez-Bolaños, Adrian M. Ionescu:
Shunt capacitive switches based on VO2 metal insulator transition for RF phase shifter applications. 232-235 - K. Ben Ali, P. M. Gammon, C. W. Chan, F. Li, V. Pathirana, T. Trajkovic, Farzan Gity
Single event effects and total ionising dose in 600V Si-on-SiC LDMOS transistors for rad-hard space applications. 236-239 - Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta
PPAC scaling enablement for 5nm mobile SoC technology. 240-243 - V. Deshpande, Herwig Hahn
Hybrid InGaAs/SiGe CMOS circuits with 2D and 3D monolithic integration. 244-247 - Mirko Scholz, Geert Hellings, Shih-Hung Chen, Dimitri Linten:
Tunable ESD clamp for high-voltage power I/O pins of a battery charge circuit in mobile applications. 248-251 - Claire Fenouillet-Béranger, S. Beaurepaire, Fabien Deprat, Alexandre Ayres De Sousa, Laurent Brunet, Perrine Batude, Olivier Rozeau, François Andrieu, Paul Besombes, M.-P. Samson, Bernard Previtali, F. Nemouchi, G. Rodriguez, Philippe Rodriguez
Guidelines for intermediate back end of line (BEOL) for 3D sequential integration. 252-255 - Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene:
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. 256-259 - Severine Le Gac:
Microfluidic technology: New opportunities to develop physiologically relevant in vitro models integrated microfluidic platform for the in vitro pre-implantation culture of individual mammalian embryos and their in situ characterization. 260-263 - Getenet Tesega Ayele, Stéphane Monfray, Frédéric Boeuf, Jean-Pierre Cloarec
Development of ultrasensitive extended-gate Ion-sensitive-field-effect-transistor based on industrial UTBB FDSOI transistor. 264-267 - Qinghua Han, Anran Gao, Keyvan Narimani, Yuelin Wang, Tie Li, Siegfried Mantl, Qing-Tai Zhao
Ultrathin lateral unidirectional bipolar-type insulated-gate transistor as pH sensor. 268-271 - Andreas Hessel, Stefan Scholz, Alexander Pelger, Albert Pfander, Joachim Knoch
A novel approach for scalable sensor arrays using cantilever field-effect transistors. 272-275 - Nian Wang, Shih-Hung Chen, Geert Hellings, Kris Myny
ESD characterisation of a-IGZO TFTs on Si and foil substrates. 276-279 - Guangrui Xia:
Dopant diffusion and segregation, Si-Ge interdiffusion and defect engineering in SiGe devices. 280-283 - Theresia Knobloch
Physical modeling of the hysteresis in M0S2 transistors. 284-287 - Gioele Mirabelli
Impact of impurities, interface traps and contacts on MoS2 MOSFETs: Modelling and experiments. 288-291 - Eduard Cartier, Atreya Majumdar, K.-T. Lee, Takashi Ando, Martin M. Frank, John Rozen, Keith A. Jenkins, C. Liang, C.-W. Cheng, John Bruley, M. Hopstaken, Pranita Kerber, J.-B. Yau, X. Sun, Renee T. Mo, Chun-Chen Yeh, Effendi Leobandung, Vijay Narayanan
Electron mobility in thin In0.53Ga0.47As channel. 292-295 - Mengnan Ke, Mitsuru Takenaka, Shinichi Takagi:
Understanding of slow traps generation in plasma oxidation GeOx/Ge MOS interfaces with ALD high-k layers. 296-299 - Romain Ritzenthaler, Hans Mertens, An De Keersgieter, Jérôme Mitard, Dan Mocuta, N. Horiguchi:
Isolation of nanowires made on bulk wafers by ground plane doping. 300-303 - Dae-Young Jeon, Tim Baldauf, So Jeong Park, Sebastian Pregl, Larysa Baraban
In-depth electrical characterization of carrier transport in ambipolar Si-NW Schottky-barrier FETs. 304-307
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-29 20:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: