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ERSA 2007: Las Vegas, Nevada, USA
- Toomas P. Plaks:
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007. CSREA Press 2007, ISBN 1-60132-026-4
Keynotes and Invited Talks
- Steve Leibson:
Challenges in Consumer Electronics for the 21st Century. ERSA 2007: 3-12 - Viktor K. Prasanna:
Scientific Computing using Reconfigurable Hardware. ERSA 2007: 13 - Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet:
A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24 - Bernard Pottier:
An Integrated Platform for Heterogeneous Reconfigurable Computing. ERSA 2007: 25-36
Reconfigurable Systems on Chip
- Swathi Tanjore Gurumani, B. Earl Wells:
Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures. ERSA 2007: 37-43 - Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews:
Memory Hierarchy for MCSoPC Multithreaded Systems. ERSA 2007: 44-50 - Pranav Vaidya, Jaehwan John Lee:
Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors. ERSA 2007: 51-60 - Xiaofang Wang, Sotirios G. Ziavras, Jie S. Hu:
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors. ERSA 2007: 61-70
Task Scheduling and Dynamic Reconfiguration
- Javier Resano, Juan Antonio Clemente, Carlos González, Jose Luis Garcia, Daniel Mozos:
HW implementation of an execution manager for reconfigurable systems. ERSA 2007: 71-77 - Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto:
Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity. ERSA 2007: 78-84 - Fredy Rivera, Marcos Sánchez-Élez, Nader Bagherzadeh:
Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures. ERSA 2007: 85-91 - Darrin M. Hanna, Michael DuChene, Lawrence Kennedy, Brian Carpenter:
A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded Systems. ERSA 2007: 92-98 - Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung:
Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing. ERSA 2007: 99-106
Applications
- Chuan He, Guan Qin, Richard E. Ewing, Wei Zhao:
High-Precision BLAS on FPGA-enhanced Computers. ERSA 2007: 107-116 - Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne P. Burleson:
High-efficiency protection solution for off-chip memory in embedded systems. ERSA 2007: 117-123 - Eric Grobelny, Casey Reardon, Adam Jacobs, Alan D. George:
Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and Applications. ERSA 2007: 124-130 - Michaela Amoo, Clay Gloster:
FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT. ERSA 2007: 131-137 - Abdel Ejnioui:
Prototyping of a Two-Phase Micropipeline on FPGAs. ERSA 2007: 138-146
Reconfigurable Hardware
- Weinan Chen, Chenglian Peng, Bo Zhou:
A New Routing Approach to Minimizing FPGA Reconfiguration Data. ERSA 2007: 147-151 - Florian Dittmann, Achim Rettberg, Raphael Weber:
Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture. ERSA 2007: 152-158 - Sam Lee, Paul Chow:
An FPGA Implementation of Reciprocal Sums for SPME. ERSA 2007: 159-165 - Melissa Smith, Gregory Peterson:
Optimization of Shared High-Performance Reconfigurable Computing Resources. ERSA 2007: 166-174 - Christophe Wolinski, Krzysztof Kuchcinski:
Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware. ERSA 2007: 175-181 - Jason Meyer, Fatih Kocan, Daniel G. Saab:
Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. ERSA 2007: 182-190
Short Papers
- Elena Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor:
Reducing the reconfiguration overhead: a survey of techniques. ERSA 2007: 191-194 - Henrik Svensson, Thomas Lenart, Viktor Öwall:
Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor. ERSA 2007: 195-198 - Cristiana Bolchini, Fabio Salice, Marco D. Santambrogio:
Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs. ERSA 2007: 199-202 - Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano:
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. ERSA 2007: 203-206 - Pekka Rantala, Jouni Isoaho, Hannu Tenhunen:
Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip. ERSA 2007: 207-210 - Dimitris Syrivelis, Spyros Lalis:
Design and Evaluation of a Software Infrastructure for the Runtime Management of Reconfigurable Resources. ERSA 2007: 211-215 - Anna Antola, Marco Castagna, Pamela Gotti, Marco D. Santambrogio:
Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC. ERSA 2007: 216-219 - Neil Steiner, Peter Athanas:
Autonomous Computing Systems: A Proposed Roadmap. ERSA 2007: 220-226
Posters
- Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras:
A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. ERSA 2007: 227-230
Late Papers
- Yong-Kyu Jung:
Pure ASIC-Based Retargetable Computing: Architectures, Advantages, and Challenges. ERSA 2007: 231-237 - Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann:
Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. ERSA 2007: 238-247 - Alex Marschner, Stephen D. Craven, Peter M. Athanas:
A Sandbox for Exploring the OpenFire Processor. ERSA 2007: 248-251 - Arjun K. Pai, Khaled Benkrid:
Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications. ERSA 2007: 252-258 - Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi:
272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA 2007: 259-264 - Ludek Bryan, Otto Fucík:
FPGA Implementation of a Reconfigurable License Plate Detection Method. ERSA 2007: 265-268 - Rawad N. Al-Haddad, Carthik A. Sharma, Ronald F. DeMara:
Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation. ERSA 2007: 269-272 - Jeoong Sung Park, Hong-Jip Jung:
Efficient FPGA-based Implementation of Time Synchronization for MIMO-OFDM. ERSA 2007: 273-279 - Stephen D. Craven, Peter M. Athanas:
High-Level Specification of Runtime Reconfigurable Designs. ERSA 2007: 280-283 - Ross Brennan, Michael Manzke, Keith O'Conor, John Dingliana, Carol O'Sullivan:
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture. ERSA 2007: 284-290 - Minoru Watanabe:
Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. ERSA 2007: 291-294 - Sébastien Lafontant, Tarek Taha:
Feasibility of Hardware Acceleration of a Neocortex Model. ERSA 2007: 295-301 - Neil Steiner, Peter M. Athanas:
Autonomous Computing Systems: A Proof-of-Concept. ERSA 2007: 302-
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