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CASES 2010: Scottsdale, AZ, USA
- Vinod Kathail, Reid Tatge, Rajeev Barua:
Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010. ACM 2010, ISBN 978-1-60558-903-9
Compilers
- Apala Guha, Kim M. Hazelwood, Mary Lou Soffa:
Balancing memory and performance through selective flushing of software code caches. 1-10 - Cupertino Miranda, Antoniu Pop, Philippe Dumont, Albert Cohen, Marc Duranton:
Erbium: a deterministic, concurrent intermediate representation to map data-flow tasks to scalable, persistent streaming processes. 11-20 - Yongjun Park, Hyunchul Park, Scott A. Mahlke, Sukjin Kim:
Resource recycling: putting idle resources to work on a composable accelerator. 21-30 - Sebastian Buchwald, Andreas Zwinkau:
Instruction selection by graph transformation. 31-40
Special session -- embedded systems for future medical care
- Elena Maftei, Paul Pop
, Jan Madsen
Routing-based synthesis of digital microfluidic biochips. 41-50 - Rajeswari Pingali, P. Niranjana:
Mosaic of organic development through technology intervention in the rural indian context. 51-52 - Danny Petrasek, Alan Barr, Krishna V. Palem:
The virtual hospital: the emergence of telemedicine. 53-54 - Alan H. Barr:
Parsimonious information technologies for pixels, perception, wetware and simulation: issues for Petrasek's global virtual hospital system. 55-56
Architectures I
- Zhimin Chen, Ambuj Sinha, Patrick Schaumont
Implementing virtual secure circuit using a custom-instruction approach. 57-66 - Ganesh S. Dasika, Mark Woh, Sangwon Seo, Nathan Clark, Trevor N. Mudge, Scott A. Mahlke:
Mighty-morphing power-SIMD. 67-76 - Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita:
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. 77-86
Architectures II
- Jonghee M. Youn
Implementing dynamic implied addressing mode for multi-output instructions. 87-96 - Vladimir Uzelac, Aleksandar Milenkovic
Real-time unobtrusive program execution trace compression using branch predictor events. 97-106 - Sylvain Girbal
A memory interface for multi-purpose multi-stream accelerators. 107-116 - Vladimir Uzelac, Aleksandar Milenkovic
Hardware-based data value and address trace filtering techniques. 117-126
Compiler managed caches and memories
- Xuejun Yang, Li Wang, Jingling Xue
Improving scratchpad allocation with demand-driven data tiling. 127-136 - JongSoo Park, James D. Balfour, William J. Dally:
Fine-grain dynamic instruction placement for L0 scratch-pad memory. 137-146 - Yun Liang, Tulika Mitra
Improved procedure placement for set associative caches. 147-156 - Lovic Gauthier, Tohru Ishihara
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. 157-166
Special session: IEEE McDowell lecture and novel architectures
- Krishna V. Palem:
Compilers, architectures and synthesis for embedded computing: retrospect and prospect. 167-176 - Zvi M. Kedem, Vincent John Mooney, Kirthi Krishna Muntimadugu, Krishna V. Palem, Avani Devarasetty, Phani Deepak Parasuramuni:
Optimizing energy to minimize errors in dataflow graphs using approximate adders. 177-186
Compilers and applications
- Michael R. Jantz
Eliminating false phase interactions to reduce optimization phase order search space. 187-196 - Mircea Namolaru, Albert Cohen, Grigori Fursin, Ayal Zaks, Ari Freund:
Practical aggregation of semantical program properties for machine learning based optimization. 197-206 - Andrea Marongiu, Paolo Burgio
Vertical stealing: robust, locality-aware do-all workload distribution for 3D MPSoCs. 207-216 - Dongwon Lee, Marilyn Wolf, Hyesoon Kim:
Design space exploration of the turbo decoding algorithm on GPUs. 217-226
Cache and memory architectures
- Mafijul Md. Islam, Per Stenström:
Characterization and exploitation of narrow-width loads: the narrow-width cache approach. 227-236 - Arup Chakraborty, Houman Homayoun, Amin Khajeh, Nikil D. Dutt
E < MC2: less energy through multi-copy cache. 237-246 - Ji Gu, Hui Guo:
Enabling large decoded instruction loop caching for energy-aware embedded processors. 247-256
Tutorials
- Arindam Mallik, Peter Marwedel, Dimitrios Soudris
MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs. 257-258 - Luigi Carro
Challenges for embedded multicore architecture. 259-260
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