What does convergent values mean in this context?

In this context, a value is "convergent" if it has the same value in every SIMD lane.

Intel GPUs can execute 8, 16 or 32 lanes wide SIMD; before this change, convergent values had to be stored in a register as wide as SIMD execution. After this change, they can be stored in an 8 lane register, and the GPU will automatically replicate it twice or four times for operations on 16 or 32 lanes.

Do such Mesa enhancements automatically benefit Rusticle?

I assume this distinction is a static determination, no?

Is this a hardware or software limitation? It still seems awfully wasteful to burn 256 bits on a 32-bit scalar, but I get that it's a lot better than 512 or 1024 bits.

So, does the hardware actually have scalar registers and they're just not being used?

Thanks for the explanation. When you say "the GPU will automatically replicated it", does that mean adding a SIMD8 vector to a SIMD32 vector will cause the SIMD8 operand automatically to get replicated to match the width of the larger operand?

This is a patch for the Intel compiler graphics as the article says, so i am pretty sure it is static, the compiler will check wich values are convergent and put that information on the machine code.

Software, register allocation is a function of compilers, hardware dont decide wich registers are used in a instruction.

the architecture of the compiler can only allocate register in groups of 8, they could change it, but that would require to change lots of code.

​​

Modern GPUs have scalar ALUs, but not scalar registers, they are shared with SIMD ALUs.

I have not seen the code to see how it is implemented.

But it could be like that, store convergent values in a SIMD8 to reduce register usage, then when using it in a instruction, just copy the value to more registers until you have a full SIMD32.​

No...all registers are 256-bit (8 lanes at 32-bit) until Xe2 (Lunarlake/Battlemage) when they start being 512-bit (16 lanes at 32-bit). You've got the right of it—using 8 lanes for a scalar is still pretty wasteful, but a lot better than wasting 16 or 32 lanes. Eventually, we plan to do SIMD1 scalars, where we use only 1 lane, and can pack things more tightly.

But, as an incremental step, this let us figure out which values are convergent, teach consumers to handle that, and begin taking advantage of the information. We can then look at allocating scalars more efficiently in a second step.

Most instructions can implicitly replicate a scalar source out to all the lanes. For example,

Would add the 16 lanes in register r4 with r8's single lane 7 and store that in r2. This is effectively free.​