coder
Senior Member
"testing..."
Last Activity: 29 December 2024, 10:12 AM
Joined: 24 November 2014
Location: Somewhere code is written.
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You're excluding Chromebooks, which sell at more than twice the volume of Macs.... -
This works, but depends on the library in question to make proper use of shared library versioning (or other name mangling), for the .so file(s). For...Leave a comment:
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Wouldn't installing a Rust crate be more akin to installing a RPM or DEB of a C/C++ library?...Leave a comment:
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In full disclosure, I don't really know anything about Swift. I just remember seeing this news:...Leave a comment:
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Yes, I don't follow the subject of Management Engine hacks very closely, because it's not generically very useful and is mostly just of interest to hackers....Leave a comment:
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Yeah, this was explained in an earlier article. Another big caveat of O_DIRECT than the ones you mentioned is that it's not supported by all filesystems...Leave a comment:
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First of all, your math is bad. If you think picosecond precision means it's running at a cycle per picosecond, then it would have to run at 1 Terahertz....Leave a comment:
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I assume this distinction is a static determination, no?
Is this a hardware or software limitation? It still seems awfully wasteful...Leave a comment:
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A core is defined by a set of execution machinery and state that are physically interconnected and interoperate. SMT provides a layer of abstraction over...Leave a comment:
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This. It's for the type of apps which already might've been using O_DIRECT (or wanted to, if not for some of its unfortunate side-effects and complications)....Leave a comment:
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Intel's hybrid CPUs organize E-cores in clusters of 4*, with a shared L2 cache per cluster. Each P-core gets its own L2. Arrow Lake continues this tradition....Leave a comment:
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It seems to be mostly technical content, like tutorials, webinars, GDC sessions, etc. There are a few interviews that sound more wide-ranging, but I...Leave a comment:
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Michael , Intel used 15 (0Fh) for the Netburst-based CPUs, like Pentium 4 and Pentium D. Then, with Pentium M, and the Core series, they returned to using...Leave a comment:
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Some of the really weird performance results from the initial 285K testing seemed due to threads getting scheduled on E-cores. It's obvious when this...Last edited by coder; 23 December 2024, 12:54 AM.Leave a comment:
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How do you know? Are you a chip designer? Or a venture capitalist? The name implies this is their third generation, so it's past time for technology demos...Last edited by coder; 22 December 2024, 03:18 PM.Leave a comment:
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Since when in the technology world was it deemed "algright" to be like 6 years behind anyone??
Wow, you guys are being super weird....Leave a comment:
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There are plenty of database, webserver, fileserver, etc. benchmarks that measure latency.
One micro-benchmark that seems very relevant to...Leave a comment:
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That's a decent amount of content at launch. Mostly AI focused, but a smattering of other stuff too. This one caught my attention:...
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