TM
MP2305 – 2A, 23V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER
The worst-case condition occurs at VIN = 2VOUT
,
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP2305 can be optimized for a wide range of
capacitance and ESR values.
where IC1 = ILOAD/2. For simplification, choose
the input capacitor whose RMS current rating
greater than half of the maximum load current.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, a small, high quality ceramic
capacitor, i.e. 0.1µF, should be placed as close
to the IC as possible. When using ceramic
capacitors, make sure that they have enough
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The
input voltage ripple for low ESR capacitors can
be estimated by:
Compensation Components
MP2305 employs current mode control for easy
compensation and fast transient response. The
system stability and transient response are
controlled through the COMP pin. COMP pin is
the output of the internal transconductance
error amplifier. A series capacitor-resistor
combination sets a pole-zero combination to
control the characteristics of the control system.
The DC gain of the voltage feedback loop is
given by:
⎛
⎜
⎝
⎞
⎟
⎟
⎠
ILOAD
VOUT
VIN
VOUT
⎜
∆V
=
×
× 1−
IN
C1× fS
V
IN
VFB
AVDC = RLOAD × GCS × AEA
×
VOUT
Where C1 is the input capacitance value.
Where AVEA is the error amplifier voltage gain;
GCS is the current sense transconductance and
Output Capacitor
The output capacitor is required to maintain the
DC output voltage. Ceramic, tantalum, or low
ESR electrolytic capacitors are recommended.
Low ESR capacitors are preferred to keep the
output voltage ripple low. The output voltage
ripple can be estimated by:
RLOAD is the load resistor value.
The system has two poles of importance. One
is due to the compensation capacitor (C3) and
the output resistor of the error amplifier, and the
other is due to the output capacitor and the load
resistor. These poles are located at:
⎛
⎜
⎝
⎞
⎟
⎟
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
VOUT
VIN
1
⎜
⎜
∆VOUT
=
× 1−
× RESR
+
fS × L
8 × fS × C2
GEA
⎠
fP1
=
2π× C3× AVEA
Where C2 is the output capacitance value and
RESR is the equivalent series resistance (ESR)
value of the output capacitor.
1
fP2
=
2π × C2× RLOAD
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is mainly caused by the
capacitance. For simplification, the output
voltage ripple can be estimated by:
Where
transconductance.
GEA
is
the
error
amplifier
The system has one zero of importance, due to the
compensation capacitor (C3) and the compensation
resistor (R3). This zero is located at:
1
⎛
⎜
⎝
⎞
VOUT
VOUT
VIN
fZ1
=
⎜
⎟
⎟
⎠
∆VOUT
=
× 1−
2
2π × C3×R3
8 × fS × L × C2
The system may have another zero of
importance, if the output capacitor has a large
capacitance and/or a high ESR value. The zero,
due to the ESR and capacitance of the output
capacitor, is located at:
In the case of tantalum or electrolytic
capacitors, the ESR dominates the impedance
at the switching frequency. For simplification,
the output ripple can be approximated to:
VOUT
VOUT
VIN
⎛
⎞
1
∆VOUT
=
× ⎜1−
⎟ ×RESR
⎜
⎟
fESR
=
fS ×L
⎝
⎠
2π × C2× RESR
MP2305 Rev. 1.7
4/17/2006
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