[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/368434.368842acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
Article
Free access

Importance of CAD tools and methodology in high speed CPU design: invited talk

Published: 28 January 2000 Publication History
First page of PDF

References

[1]
Ken Kutaragi, et al., "A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.256-257, 1999.
[2]
F. Michael Raam, et al., "A High Bandwidth Superscalar Microprocessor for Multimedia Applications," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.258-259, 1999.
[3]
T. Kamei, et al., "300MHz design methodology of VU for Emotion Synthesis," Proc. ASP-DAC, to be appeared., 2000.
[4]
N. Kojima, et al., "Repeater Insertion Method and its application to a 300MHz 128-bit 2-way Superscaler Microprocessor," Proc. ASP-DAC, to be appeared., 2000.
[5]
F. Ishihara, et al., "Clock Design of 300MHz 128-bit 2-way Superscaler Microprocessor," Proc. ASP-DAC, to be appeared., 2000.

Cited By

View all
  • (2012)IEICE Communications Society Magazine10.1587/bplus.5.3285:4(328-333)Online publication date: 2012
  • (2010)Authentication of Processor Hardware Leveraging Performance Limits in Detailed Simulations and EmulationsTowards Hardware-Intrinsic Security10.1007/978-3-642-14452-3_14(309-329)Online publication date: 12-Oct-2010
  • (2009)Hardware authentication leveraging performance limits in detailed simulations and emulationsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630090(682-687)Online publication date: 26-Jul-2009
  • Show More Cited By
  1. Importance of CAD tools and methodology in high speed CPU design: invited talk

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation Conference
    January 2000
    691 pages
    ISBN:0780359747
    DOI:10.1145/368434
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 28 January 2000

    Permissions

    Request permissions for this article.

    Check for updates

    Qualifiers

    • Article

    Conference

    ASP-DAC00
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 466 of 1,454 submissions, 32%

    Upcoming Conference

    ASPDAC '25

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)42
    • Downloads (Last 6 weeks)11
    Reflects downloads up to 01 Jan 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2012)IEICE Communications Society Magazine10.1587/bplus.5.3285:4(328-333)Online publication date: 2012
    • (2010)Authentication of Processor Hardware Leveraging Performance Limits in Detailed Simulations and EmulationsTowards Hardware-Intrinsic Security10.1007/978-3-642-14452-3_14(309-329)Online publication date: 12-Oct-2010
    • (2009)Hardware authentication leveraging performance limits in detailed simulations and emulationsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630090(682-687)Online publication date: 26-Jul-2009
    • (2005)Challenges in PowerPC440-FS Soft Core Development: Timing perspective2005 6th International Conference on ASIC10.1109/ICASIC.2005.1611274(156-159)Online publication date: 2005
    • (2005)Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)10.1109/ASAP.2005.68(204-212)Online publication date: 2005
    • (2003)Hybrid hierarchical timing closure methodology for a high performance and low power DSPProceedings of the 40th annual Design Automation Conference10.1145/775832.776046(850-855)Online publication date: 2-Jun-2003
    • (2000)Vector Unit Architecture for Emotion SynthesisIEEE Micro10.1109/40.84847120:2(40-47)Online publication date: 1-Mar-2000

    View Options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Login options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media