More Web Proxy on the site http://driver.im/

research-article

Public Access

Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System

Authors:

M. Amimul Ehsan,

Yang YiAuthors Info & Claims

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

Article No.: 86, Pages 1 - 6

https://doi.org/10.1145/3061639.3062196

Published: 18 June 2017 Publication History

Abstract

Neurophysiological architecture using 3D integration technology offers a high device interconnection density as well as fast and energy efficient links among the neuron and synapses layers. In this paper, we propose to reconfigure the Through-Silicon-Vias (TSVs) to serve as the neuronal membrane capacitors that map the membrane electrical activities in a hybrid 3D neuromorphic system. We also investigate new methodology that could significantly enhance the TSV capacitance to achieve a high efficiency of signal processing through membrane. An optimal CAD framework is designed to optimally utilize such TSV devices, and resolve the signal-integrity issues arising at fast data rates during massively parallel data transmissions. The electrical performance of the 3D neuromorphic chip is compared against the ones of the 2D counterpart design to demonstrate the advantages of our design and methodology.

References

[1]

C. Mead, Analog VLSI and neural systems. Addison-Wesley, Boston, MA, USA.

Digital Library

[2]

DARPA Synapse Program: http://www.artificialbrains.com/darpa-synapse-program.

[3]

I. Loi, F. Angiolini, S. Fujita, S. Mitra, and L. Benini, "Characterization, and implementation of fault-tollerant vertical links for 3-D network-on-chip," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 1, pp. 124--134, 2011.

Digital Library

[4]

U. R. Tida, R. Yang, C. Zhuo and Y. Shi, "On the Efficacy of Through-Silicon-Via Inductors," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 7, pp. 1322--1334, July 2015.

[5]

U. R. Tida, C. Zhuo and Y. Shi, "Novel Through-Silicon-Via Inductor-Based On-Chip DC-DC Converter Designs in 3D ICs," in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 11, no. 2, Nov. 2014.

Digital Library

[6]

J. H. Lau, "TSV Manufacturing Yield and Hidden Costs for 3D IC Integration," in Proc. Of Electronic Components and Technology Conference (ECTC), pp. 1031--1042, 2010.

[7]

C. Zhao, B. Wysocki, C. Thiem, N. McDonald, J. Li, and Y. Yi, "Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems," IEEE Trans. on Multi-Scale Computing Systems (TMSCS), vol. 2, no. 4, pp. 265--276, 2016.

[8]

C. Zhao, J. Li, and Y, Yi, "Making neural encoding robust and energy-efficient: an advanced analog temporal encoder for brain-inspired computing systems," in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2016, pp. 1--6.

Digital Library

[9]

D.H. Kim et al., "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory," in Proc. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 188--190, 2012.

[10]

H.-Y. Huang, Y.-S. Huang, C.-L. Hsu, "Built-in Self-test/repair Scheme for TSV-based Three dimensional Integrated Circuits," in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 56--59, 2010.

[11]

A. Joubert, M. Duranton, B. Belhadj, O. Temam, and R. Heliot, "Capacitance of TSVs in 3D stacked chips a problem? Not for neuromorphic systems," In proc. DAC'12. pp. 1260--1261.

Digital Library

[12]

K. Ryan, S. Tanachutiwat, and W. Wang, "3D CMOL Crossnet for Neuromorphic Network Applications," Nano-Net, Springer Berlin Heidelberg, 3, 2009, pp. 1--5.

[13]

B. Belhadj, A. Valentian, P. Vivet, M. Duranton, L. He, O. Temam, "The improbable but highly appropriate marriage of 3D stacking and neuromorphic accelerators," In proc. Int. Conf. on Compilers, Architec. Synth for Embedded Syst. (12-17 Oct. 2014), 1--9.

Digital Library

[14]

Y. Yi, Y. Zhou, X. Fu, and F. Shen, "Modeling Differential Through-Silicon-Vias (TSVs) with Voltage Dependent and Nonlinear Capacitance," Journal of Selected Areas in Microelectronics (JSAM), Cyber Journals, vol.3, no. 6, pp. 1--9, 2013.

[15]

S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981.

[16]

Y. Yi, Y. Liu, Y. Zhou, and W. Becker, "Minimizing crosstalk in highspeed differential buses by optimizing power/ground and signal assignment," in Proceedings of 18th IEEE conference on Electrical Performance of electronic Packaging (EPEP), pp. 255--258, 2009.

[17]

G. Katti, M. Stucchi, J. Van Olmen, K. De Meyer and W. Dehaene, "Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance," in IEEE Electron Device Letters, vol. 31, no. 6, pp. 549--551, June 2010.

Cited By

Ikechukwu ODang KAbdallah A(2021)On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip LearningIEEE Access10.1109/ACCESS.2021.30710899(64331-64345)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3071089
Liu SYi Y(2020)Quantized Neural Networks and Neuromorphic Computing for Embedded SystemsIntelligent System and Computing [Working Title]10.5772/intechopen.91835Online publication date: 30-Mar-2020
https://doi.org/10.5772/intechopen.91835
An HBai KYi Y(2018)The Roadmap to Realize Memristive Three-Dimensional Neuromorphic Computing SystemAdvances in Memristor Neural Networks - Modeling and Applications10.5772/intechopen.78986Online publication date: 3-Oct-2018
https://doi.org/10.5772/intechopen.78986
Show More Cited By

Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System
1. Hardware

Recommendations

Neuromorphic 3D Integrated Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation Computing
GLSVLSI '17: Proceedings of the Great Lakes Symposium on VLSI 2017

In this paper, we proposed to use 3D integration technology to create a neuromorphic hardware system that is compatible with current technology, provides high system speed, high density, massively parallel processing, low power consumption, and small ...
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs
Abstract
In this work, we discuss the influence of strained silicon technology on transistors in the context of Through Silicon Via (TSV) thermal stress. An accurate thermal stress distribution around a single TSV is firstly obtained by finite ...
Highlights
- An accurate stress distribution of a complete TSV structure through FEA simulation.
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

Three methods have been proposed to test Through-Silicon-Vias (TSV) electrically prior to 3D integration. These test methods are (1) sense amplification; (2) leakage current monitor; and (3) capacitance bridge methods. These tests are aimed at detecting ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017

June 2017

533 pages

ISBN:9781450349277

DOI:10.1145/3061639

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 June 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Funding Sources

NSF

Conference

DAC '17

Sponsor:

EDAC
SIGDA

DAC '17: The 54th Annual Design Automation Conference 2017

June 18 - 22, 2017

TX, Austin, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
222
Total Downloads

Downloads (Last 12 months)73
Downloads (Last 6 weeks)19

Reflects downloads up to 10 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Ikechukwu ODang KAbdallah A(2021)On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip LearningIEEE Access10.1109/ACCESS.2021.30710899(64331-64345)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3071089
Liu SYi Y(2020)Quantized Neural Networks and Neuromorphic Computing for Embedded SystemsIntelligent System and Computing [Working Title]10.5772/intechopen.91835Online publication date: 30-Mar-2020
https://doi.org/10.5772/intechopen.91835
An HBai KYi Y(2018)The Roadmap to Realize Memristive Three-Dimensional Neuromorphic Computing SystemAdvances in Memristor Neural Networks - Modeling and Applications10.5772/intechopen.78986Online publication date: 3-Oct-2018
https://doi.org/10.5772/intechopen.78986
Ehsan MAn HZhou ZYi Y(2018)A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D ICIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.276050637:8(1640-1653)Online publication date: Aug-2018
https://doi.org/10.1109/TCAD.2017.2760506

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents