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research-article

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

Authors:

Russell Barnes,

Yuan XieAuthors Info & Claims

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 6

https://doi.org/10.1145/2966986.2980095

Published: 07 November 2016 Publication History

Abstract

Due to the increasing fabrication and design complexity with new process nodes, the cost per transistor trend originally identified in Moore's Law is slowing when using traditional integration methods. However, emerging die-level integration technologies may be viable alternatives that can scale the number of transistors per integrated device while reducing the cost per transistor through yield improvements across multiple smaller dies. Additionally, the escalating overheads of non-recurring engineering costs like masks and verification can be curtailed through die integration-enabled reuse of intellectual property across heterogeneous process technologies. In this paper, we present an analytical cost model for 3D and interposer-based 2.5D die integration and employ it to demonstrate the potential cost reductions across semiconductor markets. We also propose a methodology and platform for IP reuse based on these integration technologies and explore the available reductions in overall product cost through reduction in non-recurring engineering effort.

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Jiao BXu LYu XYang HZhu HWang YZhu JWen DWang LTao JChen CHan YLiu QSun NLiu M(2024)FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon InterposerIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.341957971:9(4156-4168)Online publication date: Sep-2024
https://doi.org/10.1109/TCSI.2024.3419579
Li ZWentzlaff D(2024)LUCIE: A Universal Chiplet-Interposer Design Framework for Plug-and-Play Integration2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00039(423-436)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00039
Cai JWu ZPeng SWei YTan ZShi GGao MMa K(2024)Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00022(156-171)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00022
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Index Terms

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits

Index terms have been assigned to the content through auto-classification.

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cover image Guide Proceedings

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2016

946 pages

Copyright © 2016.

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IEEE Press

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Published: 07 November 2016

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Cited By

Jiao BXu LYu XYang HZhu HWang YZhu JWen DWang LTao JChen CHan YLiu QSun NLiu M(2024)FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon InterposerIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2024.341957971:9(4156-4168)Online publication date: Sep-2024
https://doi.org/10.1109/TCSI.2024.3419579
Li ZWentzlaff D(2024)LUCIE: A Universal Chiplet-Interposer Design Framework for Plug-and-Play Integration2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00039(423-436)Online publication date: 2-Nov-2024
https://doi.org/10.1109/MICRO61859.2024.00039
Cai JWu ZPeng SWei YTan ZShi GGao MMa K(2024)Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00022(156-171)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00022
Kadomoto JIrie HSakai S(2024)A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS62602.2024.10808622(105-109)Online publication date: 7-Nov-2024
https://doi.org/10.1109/APCCAS62602.2024.10808622
Liu YLi XYin S(2024)Review of chiplet-based design: system architecture and interconnectionScience China Information Sciences10.1007/s11432-023-3926-867:10Online publication date: 19-Jul-2024
https://doi.org/10.1007/s11432-023-3926-8
Feng YXiang DMa K(2023)Heterogeneous Die-to-Die Interfaces: Enabling More Flexible Chiplet Interconnection SystemsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614310(930-943)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614310
Bhattacharjee AMoitra APanda P(2023)HyDe: A Hybrid PCM/FeFET/SRAM Device-Search for Optimizing Area and Energy-Efficiencies in Analog IMC PlatformsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2023.332774813:4(1073-1082)Online publication date: Dec-2023
https://doi.org/10.1109/JETCAS.2023.3327748
Palesi MRusso EDas AJose J(2023)Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW59300.2023.00081(477-483)Online publication date: May-2023
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Feng YXiang DMa K(2023)A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10070981(1059-1071)Online publication date: Feb-2023
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Li FWang YCheng YWang YHan YLi HLi XMitra TYoung EXiong J(2022)GIAProceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549464(1-9)Online publication date: 30-Oct-2022
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