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Design and verification of large-scale computers by using DDL

Authors:

Nobuaki Kawato,

Takao Saito,

Fumihiro Maruyama,

Takao UeharaAuthors Info & Claims

DAC '79: Proceedings of the 16th Design Automation Conference

Pages 360 - 366

Published: 25 June 1979 Publication History

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Abstract

This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.

References

[1]

[1] J. R. Duley and D. L. Dietmeyer, "A Digital system Design Language (DDL)," IEEE TC, Vol. C-17, 1968.

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[2]

[2] J. R. Duley and D. L. Dietmeyer, "Translation of a DDL Digital System Specification to Boolean equation," IEEE TC, Vol. C-18, 1968.

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[3]

[3] R. L. Arndt and D. L. Dietmeyer, "DDLSIM-A Digital Design Language Simulator," Proceedings of NEC, Vol. 26, 1970.

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[4]

[4] D. L. Dietmeyer, "Logic Design of Digital System," Allyn and Bacon, 1971.

Digital Library

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[5]

[5] M. A. Breuer, editor, "Digital System Design Automation: Languages, Simulation & Data Base," Computer Science Press, 1975.

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Cited By

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Chu YDietmeyer DDuley JHill FBarbacci MRose COrdy GJohnson BRoberts M(1992)Three Decades of HDLsIEEE Design & Test10.1109/54.1431479:2(69-81)Online publication date: 1-Apr-1992
https://dl.acm.org/doi/10.1109/54.143147
Saito TSugimoto HYamazaki MKawato NThomas D(1986)A rule-based logic circuit synthesis system for CMOS gate arraysProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318109(594-600)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318109
Kawato NUehara THirose SSaito TCrabbe JRadke COfek H(1982)An interactive logic synthesis system based upon AI techniquesProceedings of the 19th Design Automation Conference10.5555/800263.809300(858-864)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809300
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Index Terms

Design and verification of large-scale computers by using DDL
1. Hardware
  1. Hardware validation
    1. Functional verification
2. Software and its engineering
  1. Software notations and tools
    1. System description languages
      1. Design languages

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Published In

DAC '79: Proceedings of the 16th Design Automation Conference

June 1979

578 pages

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IEEE Press

Publication History

Published: 25 June 1979

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Cited By

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Chu YDietmeyer DDuley JHill FBarbacci MRose COrdy GJohnson BRoberts M(1992)Three Decades of HDLsIEEE Design & Test10.1109/54.1431479:2(69-81)Online publication date: 1-Apr-1992
https://dl.acm.org/doi/10.1109/54.143147
Saito TSugimoto HYamazaki MKawato NThomas D(1986)A rule-based logic circuit synthesis system for CMOS gate arraysProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318109(594-600)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318109
Kawato NUehara THirose SSaito TCrabbe JRadke COfek H(1982)An interactive logic synthesis system based upon AI techniquesProceedings of the 19th Design Automation Conference10.5555/800263.809300(858-864)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809300
Maruyama FUehara TKawato NSaito TCrabbe JRadke COfek H(1982)A verification technique for hardware designsProceedings of the 19th Design Automation Conference10.5555/800263.809297(832-841)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809297
Saito TUehara TKawato N(1981)A CAD system for logic design based on frames and demonsProceedings of the 18th Design Automation Conference10.5555/800073.802342(451-456)Online publication date: 29-Jun-1981
https://dl.acm.org/doi/10.5555/800073.802342
Cory W(1981)Symbolic simulation for functional verification with ADLIB and SDLProceedings of the 18th Design Automation Conference10.5555/800073.802284(82-89)Online publication date: 29-Jun-1981
https://dl.acm.org/doi/10.5555/800073.802284
Yamada A(1981)Design automation status in JapanProceedings of the 18th Design Automation Conference10.5555/800073.802278(43-50)Online publication date: 29-Jun-1981
https://dl.acm.org/doi/10.5555/800073.802278
Sasaki TYamada AKato SNakazawa TTomita KNomizu NHassler ESmith RPistilli PAbel LCrabbe JBening LShaklee DRadke C(1980)MIXSProceedings of the 17th Design Automation Conference10.1145/800139.804596(626-633)Online publication date: 23-Jun-1980
https://dl.acm.org/doi/10.1145/800139.804596
Shiva SHassler ESmith RPistilli PAbel LCrabbe JBening LShaklee DRadke C(1980)Combinational logic synthesis from an HDL descriptionProceedings of the 17th Design Automation Conference10.1145/800139.804584(550-555)Online publication date: 23-Jun-1980
https://dl.acm.org/doi/10.1145/800139.804584
Cory WVanCleemput WHassler ESmith RPistilli PAbel LCrabbe JBening LShaklee DRadke C(1980)Developments in verification of design correctness (A Tutorial)Proceedings of the 17th Design Automation Conference10.1145/800139.804525(156-164)Online publication date: 23-Jun-1980
https://dl.acm.org/doi/10.1145/800139.804525

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