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Article

Formulae and applications of interconnect estimation considering shield insertion and net ordering

Authors:

James D. Z. Ma,

Lei HeAuthors Info & Claims

ICCAD '01: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Pages 327 - 332

Published: 04 November 2001 Publication History

Abstract

It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an area-efficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in the min-area SINO/R solution. In order to accommodate pre-routed P/G wires that also serve as shields, we then formulate two new SINO problems: SINO/SPR and SINO/UPG, and propose effective and efficient two-phase algorithms to solve them. Compared to the existing dense wiring fabric scheme, the resulting SINO/SPR and SINO/UPG schemes maintain the regularity of the P/G structure, have negligible penalty on noise and delay variation, and reduce the total routing area by up to 42% and 36%, respectively. Further, we develop various pre-layout estimation formulae for shielding areas and optimal P/G structures under different routing styles. These formulae can be readily used to guide global routing and high-level design decisions.

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Cited By

Chang CCheng JHuang TLee DChen C(2016)Coding Rate Analysis of Forbidden Overlap Codes in High-Speed BusesACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/28460911:2(1-25)Online publication date: 10-May-2016
https://dl.acm.org/doi/10.1145/2846091
Chang CCheng JHuang THuang XLee D(2010)A bit-stuffing algorithm for crosstalk avoidance in high speed switchingProceedings of the 29th conference on Information communications10.5555/1833515.1833655(839-847)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.5555/1833515.1833655
Duan CCalle VKhatri S(2009)Efficient on-chip crosstalk avoidance CODEC designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200531317:4(551-560)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2005313
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Index Terms

Formulae and applications of interconnect estimation considering shield insertion and net ordering
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Electronic design automation
    1. Physical design (EDA)

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Information

Published In

cover image ACM Conferences

ICCAD '01: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

November 2001

656 pages

ISBN:0780372492

Conference Chair:
Rolf Ernst
Tech. Univ. of Braunschweig, Braunschweig, Germany

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE Circuits & Systems Society
The IEEE Computer Society DATC

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IEEE Press

Publication History

Published: 04 November 2001

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Article

Conference

ICCAD01

Sponsor:

SIGDA

ICCAD01: International Conference on Computer Aided Design

November 4 - 8, 2001

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Chang CCheng JHuang TLee DChen C(2016)Coding Rate Analysis of Forbidden Overlap Codes in High-Speed BusesACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/28460911:2(1-25)Online publication date: 10-May-2016
https://dl.acm.org/doi/10.1145/2846091
Chang CCheng JHuang THuang XLee D(2010)A bit-stuffing algorithm for crosstalk avoidance in high speed switchingProceedings of the 29th conference on Information communications10.5555/1833515.1833655(839-847)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.5555/1833515.1833655
Duan CCalle VKhatri S(2009)Efficient on-chip crosstalk avoidance CODEC designIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200531317:4(551-560)Online publication date: 1-Apr-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2005313
Duan CZhu CKhatri SFix L(2008)Forbidden transition free crosstalk avoidance CODEC designProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391717(986-991)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391717
Moiseev KWimer SKolodny A(2008)On optimal ordering of signals in parallel wire bundlesIntegration, the VLSI Journal10.1016/j.vlsi.2007.06.00241:2(253-268)Online publication date: 1-Feb-2008
https://dl.acm.org/doi/10.1016/j.vlsi.2007.06.002
Mutyam MGielen G(2007)Selective shieldingProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326201(618-621)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326201
Satyanarayana NMutyam MBabu AKennings AMandoiu I(2007)Exploiting on-chip data behavior for delay minimizationProceedings of the 2007 international workshop on System level interconnect prediction10.1145/1231956.1231977(103-110)Online publication date: 17-Mar-2007
https://dl.acm.org/doi/10.1145/1231956.1231977
Li LVijaykrishnan NKandemir MIrwin M(2004)A Crosstalk Aware Interconnect with Variable Cycle TransmissionProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969081Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969081
Sakai AYamada TMatsushita YYasuura HStan MGarrett DNakajima K(2003)Routing methodology for minimizing 1nterconnect energy dissipationProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764840(120-123)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764840
Sakai AYamada TMatsushita YYasuura HYasuura H(2003)Reduction of crosstalk noise by optimizing 3-D configuration of the routing gridProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119782(49-52)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119782
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