On enabling diagnosis for 1-pin test fails in an industrial flow
Authors: 
Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, 
Ulf SchlichtmannAuthors Info & Claims
Pages 233 - 238
Abstract
The 1-Pin Test concept has proven to be beneficial for test cost reduction. By compacting test responses into a signature and reading them out at test end, test parallelism can be increased significantly. This reduces the test time and thus test cost. Especially cost-sensitive devices, e.g. IoT end nodes, profit. A drawback of this method is the limited capability of diagnosis due to the lack of cycle-accurate PASS/FAIL information.
In this paper, we present a new approach to tackle this challenge. It enables the use of an industrial diagnosis flow for fails that occurred during 1-Pin Test. For this purpose, we propose failing vector and failing cycle analysis techniques. Our approach is fault model independent and not limited to a single fault assumption. We mitigate the aliasing problem by masking. The effectiveness of our approach is shown on an investigation of real silicon fails in industrial designs.
References
[1]
M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
[2]
D. Tille, B. Gottinger, and U. Pfannkuchen, "A lightweight X-masking scheme for IoT-designs", in IEEE Int'l Test Conf. Asia, 2017, pp. 1--6.
[3]
Y. Wu and S. M. I. Adham, "Scan-based bist fault diagnosis", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 203--211, 1999.
[4]
C. Liu and K. Chakrabarty, "Failing vector identification based on overlapping intervals of test vectors in a scan-bist environment", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 593--604, 2003.
[5]
A. B. Kahng and S. Reda, "New and improved bist diagnosis methods from combinatorial group testing theory", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 3, pp. 533--543, 2006.
[6]
M. Goessel, K. Chakrabarty, V. Ocheretnij, and A. Leininger, "A signature analysis technique for the identification of failing vectors with application to scan-bist", Jour. of Electronic Testing: Theory and Applications, vol. 20, no. 6, pp. 611--622, 2004.
[7]
W.-T. Cheng, M. Sharma, T. Rinderknecht, L. Lai, and C. Hill, "Signature based diagnosis for logic bist", in Int'l Test Conf., 2006, pp. 1--9.
[8]
M. Elm and H.-J. Wunderlich, "BISD: Scan-based built-in self-diagnosis", in Design, Automation and Test in Europe, 2010, pp. 1243--1248.
[9]
A. Cook and H.-J. Wunderlich, "Diagnosis of multiple faults with highly compacted test responses", in IEEE European Test Symp., 2014, pp. 1--6.
[10]
A. Leininger, M. Goessel, and P. Muhmenthaler, "Diagnosis of scan-chains by use of a configurable signature register and error-correcting codes", in Design, Automation and Test in Europe, 2004, pp. 1--6.
[11]
J. C. Chan and B. F. Womack, "A study of faulty signature for diagnostics", in IEEE Int'l Symp. on Circuits and Systems, 1990, pp. 2701--2704.
[12]
T. W. Williams, W. Daehn, M. Gruetzner, and C. W. Starke, "Aliasing errors in signature analysis registers", IEEE Design & Test of Computers, vol. 4, no. 2, pp. 48--57, 1987.
[13]
T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, "Diagnosing combinational logic designs using the single location at-a-time (slat) paradigm", in Int'l Test Conf., 2001, pp. 287--296.
[14]
T. Clouqueur, O. Ercevik, and K. K. Saluja, "Efficient signature-based fault diagnosis using variable size windows", in Int'l Conf. on VLSI Design, 2001, pp. 391--396.
[15]
S. Holst and H. J. Wunderlich, "Adaptive debug and diagnosis without fault dictioraries", in IEEE European Test Symp., 2008, pp. 199--204.
[16]
S. Holst and H. J. Wunderlich, "A diagnosis algorithm for extreme space compaction", in Design, Automation and Test in Europe, 2009, pp. 1355--1360.
[17]
A. Jayalakshmi and T. E. Cheong, "A methodology for lbist logic diagnosis in high volume manufacturing", in Asia Symp. on Quality Electronic Design, 2012, pp. 249--253.
[18]
I. Pomeranz and S. M. Reddy, "On dictionary-based fault location in digital logic circuits", IEEE Trans. on Comp., vol. 46, no. 1, pp. 48--59, 1997.
[19]
C. Liu and K. Chakrabarty, "Compact dictionaries for fault diagnosis in scan-bist", IEEE Trans. on Comp., vol. 53, no. 6, pp. 775--780, 2004.
[20]
C. Liu and K. Chakrabarty, "Design and analysis of compact dictionaries for diagnosis in scan-bist", IEEE Trans. on VLSI Systems, vol. 13, no. 8, pp. 979--984, 2005.
[21]
W. Zou, W. T. Cheng, S. M. Reddy, and H. Tang, "Speeding up effect-cause defect diagnosis using a small dictionary", in VLSI Test Symp., 2007, pp. 225--230.
[22]
G. Mrugalski, A. Pogiel, J. Rajski, J. Tyszer, and C. Wang, "Fault diagnosis in designs with convolutional compactors", in Int'l Test Conf., 2004, pp. 498--507.
[23]
W.-T. Cheng, K.-H. Tsai, Y. Huang, N. Tamarapalli, and J. Rajski, "Compactor independent direct diagnosis", in IEEE Asian Test Symp., 2004, pp. 204--209.
[24]
J. Tyszer, J. Rajski, G. Mrugalski, N. Mukherjee, M. Kassab, W.-T. Cheng, M. Sharma, and L. Lai, "X-tolerant compactor with on-chip registration and signature-based diagnosis", IEEE Design & Test of Computers, vol. 24, no. 5, pp. 476--485, 2007.
[25]
B. Keller and T. Bartenstein, "Use of misrs for compression and diagnostics", in Int'l Test Conf., 2005, pp. 735--743.
[26]
K. J. Balakrishnan and N. A. Touba, "Scan-based bist diagnosis using an embedded processor", in IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 209--2016.
- On enabling diagnosis for 1-pin test fails in an industrial flow
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Published: 22 January 2018
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January 22 - 25, 2018
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