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Simulation-guided property checking based on a multi-valued AR-automata

Published: 13 March 2001 Publication History
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References

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L. Augustin, B. Gennart, Y. Huh, D. Luckham, and A. Stanculescu. Verification of VHDL designs using VAL. In Design Automation Conference (DAC), pages 48-53. ACM/IEEE, 1988.
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D. Brand. Verification of Large Synthesized Designs. In IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 534-537, Santa Clara, California, November 1993. ACM/IEEE, IEEE Computer Society Press.
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J. Burch, E. Clarke, K. McMillan, D. Dill, and L. Hwang. Symbolic Model Checking: 10 20 States and Beyond. In IEEE Symposium on Logic in Computer Science (LICS), pages 1-33, Washington, D.C., June 1990. IEEE Computer Society Press.
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W. Canfield, E. Emerson, and A. Saha. Checking formal specifications under simulation. In International Conference on Computer Design (ICCD '97). IEEE Computer Society Press, 1997.
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E. Emerson. Temporal and Modal Logic. In J. van Leeuwen, editor, Handbook of Theoretical Computer Science, volume B, pages 996-1072, Amsterdam, 1990. Elsevier Science Publishers.
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T. Kropf. Formal Hardware Verification - Methods and Systems in Comparison, volume 1287 of Lecture Notes in Computer Science. Springer Verlag, state of the art report edition, August 1997.
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K. McMillan. Symbolic Model Checking. Kluwer Academic Publishers, Norwell Massachusetts, 1993.
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R. Milner. A Calculus of Communicating Systems, volume 92 of Lecture Notes in Computer Science. Springer- Verlag, New York, 1980.
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B. Nelson and R. Jones. Simulation event pattern checking with proto. In SHDL 1994, 1994.
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M. Rabin and D. Scott. Finite automata and their decision problems. IBM Journal of Research and Development, 3:115-125, 1959.
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J. Ruf, D. W. Hoffmann, T. Kropf, and W. Rosenstiel. Simulation based validation of fltl formulas in executable system descriptions. In R. Seepold, editor, Forum on Design Languages (FDL 2000), pages 311-319, T~bingen, Germany, September 2000. Sig.-VHDL and ECSI.
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Cited By

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  • (2014)Virtual prototyping evaluation framework for automotive embedded systems engineeringProceedings of the 7th International ICST Conference on Simulation Tools and Techniques10.4108/icst.simutools.2014.254625(1-10)Online publication date: 17-Mar-2014
  • (2012)An asymptotically correct finite path semantics for LTLProceedings of the 18th international conference on Logic for Programming, Artificial Intelligence, and Reasoning10.1007/978-3-642-28717-6_24(304-319)Online publication date: 11-Mar-2012
  • (2010)Towards assertion-based verification of heterogeneous system designsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871210(1171-1176)Online publication date: 8-Mar-2010
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Published In

cover image ACM Conferences
DATE '01: Proceedings of the conference on Design, automation and test in Europe
March 2001
756 pages
ISBN:0769509932

Sponsors

  • EDAA: European Design Automation Association
  • IFIP WG 10.5: IFIP WG 10.5
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEEE-CS\TTTC: Test Technology Technical Council
  • IEEE-CS\DATC: IEEE Computer Society
  • The Russian Academy of Sciences: The Russian Academy of Sciences

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IEEE Press

Publication History

Published: 13 March 2001

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DATE01
Sponsor:
  • EDAA
  • IFIP WG 10.5
  • EDAC
  • SIGDA
  • IEEE-CS\TTTC
  • IEEE-CS\DATC
  • The Russian Academy of Sciences

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2014)Virtual prototyping evaluation framework for automotive embedded systems engineeringProceedings of the 7th International ICST Conference on Simulation Tools and Techniques10.4108/icst.simutools.2014.254625(1-10)Online publication date: 17-Mar-2014
  • (2012)An asymptotically correct finite path semantics for LTLProceedings of the 18th international conference on Logic for Programming, Artificial Intelligence, and Reasoning10.1007/978-3-642-28717-6_24(304-319)Online publication date: 11-Mar-2012
  • (2010)Towards assertion-based verification of heterogeneous system designsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871210(1171-1176)Online publication date: 8-Mar-2010
  • (2010)Simulation-based verification of the MOST NetInterface specification revision 3.0Proceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871053(538-543)Online publication date: 8-Mar-2010
  • (2009)System-on-chip design by proof-based refinementInternational Journal on Software Tools for Technology Transfer (STTT)10.5555/3220918.322122311:3(217-238)Online publication date: 1-Jul-2009
  • (2008)Verification of temporal properties in automotive embedded softwareProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403417(164-169)Online publication date: 10-Mar-2008
  • (2007)Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptionsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266560(900-905)Online publication date: 16-Apr-2007
  • (2006)Formal verification of systemc designs using a petri-net based representationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131824(1228-1233)Online publication date: 6-Mar-2006
  • (2006)Fast falsification based on symbolic bounded property checkingProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147181(1077-1082)Online publication date: 24-Jul-2006
  • (2006)Distributed Symbolic Bounded Property CheckingElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2005.10.018135:2(47-63)Online publication date: 1-Feb-2006
  • Show More Cited By

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