Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions
Abstract
As an industrial practice, the functional coverage models are developed based on a high-level specification of the Design Under Verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed entirely from a high-level specification. We present a method to automatically generate implementation-aware coverage models based on the static analysis of a HDL description of the DUV. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design.
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- The EDA Consortium
- EDAA: European Design Automation Association
- ECSI
- SIGDA: ACM Special Interest Group on Design Automation
- The IEEE Computer Society TTTC
- IEEE Council on Electronic Design Automation (CEDA)
- The Russian Academy of Sciences: The Russian Academy of Sciences
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EDA Consortium
San Jose, CA, United States
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Published: 16 April 2007
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- The Russian Academy of Sciences
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