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Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache

Authors:

Jörg HenkelAuthors Info & Claims

CODES+ISSS '13: Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Article No.: 1, Pages 1 - 8

Published: 29 September 2013 Publication History

Abstract

On-chip DRAM cache has the advantage of increased cache capacity that may alleviate the memory bandwidth problem. Recent research has demonstrated the benefits of high capacity on-chip DRAM cache that leads to reduced off-chip accesses. However, state-of-the-art has not taken into consideration the cache access patterns of concurrently running heterogeneous applications that can cause inter-core cache contention. We therefore propose an adaptive bank mapping policy in response to the diverse requirements of applications with different cache access behaviors that -- as a result -- reduces inter-core cache contention in DRAM-based cache architectures. On average, our adaptive bank mapping policy increases the harmonic mean instruction-per-cycle throughput by 19.3% (max. 71%) compared to state-of-the-art bank mapping policies.

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Cited By

Hameed FMenard CCastrillon JJacob B(2017)Efficient STT-RAM last-level-cache architecture to replace DRAM cacheProceedings of the International Symposium on Memory Systems10.1145/3132402.3132414(141-151)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132414
Yin SLi JLiu LWei SGuo YNebel WAtienza D(2015)Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cacheProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755794(187-192)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755794

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM Conferences

CODES+ISSS '13: Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

September 2013

335 pages

ISBN:9781479914173

Program Chairs:
Radu Marculescu
Carnegie Mellon University
,
Preeti Ranjan Panda
IIT Delhi

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IEEE Press

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Published: 29 September 2013

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ESWEEK'13

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ESWEEK'13: Ninth Embedded System Week

September 29 - October 4, 2013

Quebec, Montreal, Canada

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Cited By

Hameed FMenard CCastrillon JJacob B(2017)Efficient STT-RAM last-level-cache architecture to replace DRAM cacheProceedings of the International Symposium on Memory Systems10.1145/3132402.3132414(141-151)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132414
Yin SLi JLiu LWei SGuo YNebel WAtienza D(2015)Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cacheProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755794(187-192)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755794

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