Integrated nanoelectronics for the future

R Chau, B Doyle, S Datta, J Kavalieros, K Zhang - Nature materials, 2007 - nature.com
Integrated electronics has come a long way since the invention of the transistor in 1947 and
the fabrication of the first integrated circuit in 1958. Given feature sizes as small as a few …

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

R Chau, S Datta, M Doczy, B Doyle… - IEEE transactions on …, 2005 - ieeexplore.ieee.org
Recently there has been tremendous progress made in the research of novel nanotechnology
for future nanoelectronic applications. In particular, several emerging nanoelectronic …

The high-k solution

MT Bohr, RS Chau, T Ghani, K Mistry - IEEE spectrum, 2007 - ieeexplore.ieee.org
The Intel's Core 2 microprocessors, based on the latest 45-nanometer CMOS process
technology have more transistors and run faster and cooler than microprocessors fabricated with …

High-/spl kappa//metal-gate stack and its MOSFET characteristics

R Chau, S Datta, M Doczy, B Doyle… - IEEE Electron …, 2004 - ieeexplore.ieee.org
We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric
being the primary cause of channel electron mobility degradation. Next, we show that …

A 90-nm logic technology featuring strained-silicon

…, C Auth, M Alavi, M Buehler, R Chau… - … on electron devices, 2004 - ieeexplore.ieee.org
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length,
strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-…

A logic nanotechnology featuring strained-silicon

…, M Armstrong, C Auth, S Cea, R Chau… - IEEE Electron …, 2004 - ieeexplore.ieee.org
Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si
increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (…

A 50 nm depleted-substrate CMOS transistor (DST)

R Chau, J Kavalieros, B Doyle, A Murthy… - … Digest (Cat. No …, 2001 - ieeexplore.ieee.org
In this paper we show a Depleted-Substrate Transistor (DST) technology which demonstrates
significant performance gain over bulk Si transistors without the floating body effect (FBE). …

Fabrication, characterization, and physics of III–V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing

…, M Radosavljevic, HW Then, R Chau - 2011 International …, 2011 - ieeexplore.ieee.org
This work demonstrates the steepest subthreshold swing (SS <; 60mV/decade) ever reported
in a III-V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction …

Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering

…, U Shah, N Zelick, R Chau - 2006 Symposium on …, 2006 - ieeexplore.ieee.org
We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k
gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS …

In search of" Forever," continued transistor scaling one new material at a time

SE Thompson, RS Chau, T Ghani… - IEEE Transactions …, 2005 - ieeexplore.ieee.org
This work looks at past, present, and future material changes for the metal-oxide-semiconductor
field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET …