User profiles for Marc Loinaz

Marc Loinaz

Verified email at stanfordalumni.org
Cited by 2099

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

DK Su, MJ Loinaz, S Masui… - IEICE transactions on …, 1993 - search.ieice.org
Switching transients in digital MOS circuits can perturb analog circuits integrated on the
same die by means of coupling through the substrate. This paper describes an experimental …

A 200-mW, 3.3-V, CMOS color camera IC producing 352/spl times/288 24-b video at 30 frames/s

MJ Loinaz, KJ Singh, AJ Blanksby… - IEEE Journal of Solid …, 1998 - ieeexplore.ieee.org
A digital color camera has been monolithically realized in a standard 0.8-/spl mu/m CMOS
technology. The chip integrates a 353/spl times/292 photogate sensor array with a unity-gain …

Performance analysis of a color CMOS photogate image sensor

AJ Blanksby, MJ Loinaz - IEEE Transactions on Electron …, 2000 - ieeexplore.ieee.org
The performance of a color CMOS photogate image sensor is reported. It is shown that by
using two levels of correlated-double sampling it is possible to effectively cancel all fixed-…

Noise performance of a color CMOS photogate image sensor

AJ Blanksby, MJ Loinaz, DA Inglis… - … IEDM Technical Digest, 1997 - ieeexplore.ieee.org
We report on the noise performance of a color CMOS photogate image sensor that supports
two levels of correlated double sampling and has high conversion gain at each pixel. Imager …

A CMOS multichannel IC for pulse timing measurements with 1-mV sensitivity

MJ Loinaz, BA Wooley - IEEE Journal of Solid-State Circuits, 1995 - ieeexplore.ieee.org
A multichannel data acquisition circuit that measures the occurrence times of input pulses
relative to a 62.5-MHz clock has been integrated in a 1.2-/spl mu/m CMOS technology. The …

A 10-Gb/s 16: 1 multiplexer and 10-GHz clock synthesizer in 0.25-/spl mu/m SiGe BiCMOS

HI Cong, SM Logan, MJ Loinaz… - IEEE Journal of Solid …, 2001 - ieeexplore.ieee.org
A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 /spl
times/ 16 b input data buffer are integrated in a 0.25-/spl mu/m SiGe BiCMOS technology. The …

An integrated VCSEL driver for 10Gb ethernet in 0.13/spl mu/m CMOS

…, A Feldman, HJ Liaw, D Liu, M Loinaz… - … Solid State Circuits …, 2006 - ieeexplore.ieee.org
A 10.3Gb/s VCSEL driver is integrated with a complete Ethernet transceiver in a standard
0.13μ m CMOS process. When driving a VCSEL differentially, the resulting optical eye exceeds …

Design and fabrication of VLSI components for a general purpose analog neural computer

…, T Clare, C Donham, TP Hsieh, M Loinaz - … VLSI implementation of …, 1989 - Springer
The design of components for a programmable analog neural computer and simulator is
described. The machine can be scaled to any size and is composed of three types of …

An 800 mW 10 Gb Ethernet transceiver in 0.13/spl mu/m CMOS

…, J Dao, A Feldman, HJ Liaw, M Loinaz… - … Solid-State Circuits …, 2004 - ieeexplore.ieee.org
A fully integrated 10 Gb Ethernet transceiver IC using a standard 0.13 /spl mu/m CMOS
process integrates 10.3 Gb/s and 4/spl times/3.12 Gb/s analog front-ends, with Layer-1 coding …

Experimental results and modeling techniques for switching noise in mixed-signal integrated circuits

MJ Loinaz, DK Su, BA Wooley - 1992 Symposium on VLSI …, 1992 - ieeexplore.ieee.org
In mixed-signal integrated circuits, fast transients in digital circuits can perturb other circuits
on the same die through both direct capacitive coupling between circuit nodes and …