CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system
M Suda, K Yamamoto, T Okayasu… - … Conference on Test …, 2005 - ieeexplore.ieee.org
This paper presents solutions to realize a high-speed, high-precision CMOS timing generator
for a 4.266-Gbps memory test system. In order to realize such a timing generator, we …
for a 4.266-Gbps memory test system. In order to realize such a timing generator, we …
1.83 ps-resolution CMOS dynamic arbitrary timing generator for> 4GHz ATE applications
T Okayasu, M Suda, K Yamamoto… - … Solid State Circuits …, 2006 - ieeexplore.ieee.org
A high-speed high-precision dynamic arbitrary timing generator, fabricated in a 0.18μm
CMOS process, for >4GHz ATE applications is demonstrated. It exhibits a maximum operating …
CMOS process, for >4GHz ATE applications is demonstrated. It exhibits a maximum operating …
On-chip circuit for measuring data jitter in the time or frequency domain
…, TJ Yamaguchi, M Soma, M Suda… - 2007 IEEE Radio …, 2007 - ieeexplore.ieee.org
An on-chip data jitter measurement circuit in 0.11-μm CMOS is demonstrated. It utilizes a
data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The …
data-to-clock converter, pulse generators, and an integrator followed by a sample-&-hold. The …
Dynamic arbitrary jitter injection method for≫ 6.5 Gb/s SerDes testing
T Fujibe, M Suda, K Yamamoto… - 2009 International …, 2009 - ieeexplore.ieee.org
A dynamic arbitrary jitter injection method that can be integrated into our high speed and
high density CMOS timing generator has been developed. This method makes it possible to …
high density CMOS timing generator has been developed. This method makes it possible to …
CMOS circuit technology for precise GHz timing generator
T Okayasu, M Suda, K Yamamoto - Proceedings. International …, 2002 - ieeexplore.ieee.org
CMOS circuit technology to realize a high-precision GHz-timing-generator is described. The
timing error factors in the CMOS circuit are explained and solutions are given. A reduced …
timing error factors in the CMOS circuit are explained and solutions are given. A reduced …
2GS/s, 10ps resolution CMOS differential time-to-digital converter for real-time testing of source-synchronous memory device
K Yamamoto, M Suda, T Okayasu - 2007 IEEE Custom …, 2007 - ieeexplore.ieee.org
A differential time-to-digital converter (TDC), fabricated in 0.18μm CMOS process, for source-synchronous
device testing is demonstrated. It exhibits a maximum sampling rate of 2.133…
device testing is demonstrated. It exhibits a maximum sampling rate of 2.133…
34.1 Gbps low jitter, low BER high-speed parallel CMOS interface for interconnections in high-speed memory test system
D Watanabe, M Suda, T Okayasu - 2004 International Conferce …, 2004 - ieeexplore.ieee.org
To solve the transmission bottleneck inside ATE systems, we developed a high-speed
parallel CMOS interface macro, which is flexibly applicable to ASICs in ATE systems. The …
parallel CMOS interface macro, which is flexibly applicable to ASICs in ATE systems. The …
Multi Strobe Circuit for 2.133 GHz Memory Test System
K Yamamoto, M Suda, T Okayasu… - 2006 IEEE …, 2006 - ieeexplore.ieee.org
This paper presents solutions to reduce measurement error and test time in an AC characteristic
test of a source-synchronous device. In order to realize such a solution, we developed a …
test of a source-synchronous device. In order to realize such a solution, we developed a …
A Novel Approach for Digitizing Series Integrators and Its Application to Implementation of Recursive Digital Filters with Linear Phase
…, S ONODERA, H ASANO, M SUDA - Transactions of the Society …, 1995 - jstage.jst.go.jp
A novel approach is proposed to digitizing series integrators which are often used in modeling
dynamical system and in realizing controller and filiter. The so-called causal signals are …
dynamical system and in realizing controller and filiter. The so-called causal signals are …
A Programmable On-Chip Picosecond Jitter Measurement Circuit without a Reference Clock
…, M Ishida, T Yamaguchi, M Soma, M Suda… - … Report; IEICE Tech …, 2005 - ken.ieice.org
(in English) A new on-chip jitter measurement circuit, which does not require a reference
clock, is proposed. It consists of a combination of a programmable delay line, a phase …
clock, is proposed. It consists of a combination of a programmable delay line, a phase …