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WO2020108306A1 - 译码方法、译码装置及译码器 - Google Patents

译码方法、译码装置及译码器 Download PDF

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Publication number
WO2020108306A1
WO2020108306A1 PCT/CN2019/117991 CN2019117991W WO2020108306A1 WO 2020108306 A1 WO2020108306 A1 WO 2020108306A1 CN 2019117991 W CN2019117991 W CN 2019117991W WO 2020108306 A1 WO2020108306 A1 WO 2020108306A1
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information
block
decoding
decoded
sub
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PCT/CN2019/117991
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English (en)
French (fr)
Inventor
张鹤
唐雄
章伟
陈朝正
李晓亮
文奏章
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中兴通讯股份有限公司
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Priority to US17/296,122 priority Critical patent/US11483011B2/en
Priority to EP19890382.5A priority patent/EP3876424A4/en
Publication of WO2020108306A1 publication Critical patent/WO2020108306A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1114—Merged schedule message passing algorithm with storage of sums of check-to-bit node messages or sums of bit-to-check node messages, e.g. in order to increase the memory efficiency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Definitions

  • the present disclosure relates to, but is not limited to, the field of wireless communication, and in particular, to a decoding method, decoding device, and decoder.
  • LDPC Low Density Parity Check Code
  • the code length of the data service is flexible and changeable. Code length includes long code and short code.
  • 5G baseband channel coding uses Quasi-Cyclic LDPC (Quasi Cyclic Low Density Parity Check, QC-LDPC) coding method, which needs to be compatible with up to 51 expansion factors and 2 basic matrixes. This brings great difficulty to the flexible design of LDPC decoder.
  • the parallelism of the LDPC decoder determines the resource consumption.
  • the parallelism of the decoder based on the "block parallel" architecture is proportional to the supported expansion factor.
  • decoder parallelism In order to support the maximum expansion factor in the 5G standard, decoder parallelism is usually very large, resulting in a large resource consumption of a single decoder. In this way, in some application scenarios where hardware resources and costs are limited and the traffic demand is small, such as smart terminals, Internet of Things (IoT), etc., it will cause excess performance of the decoder and waste of hardware resources. , Low cost performance. Therefore, it is necessary to design an LDPC decoder with low parallelism and low resource consumption.
  • LDPC decoders in the industry are currently implemented using a “block parallel” architecture based on a layered decoding (Layered-decoding) method.
  • the peak throughput performance of the decoder designed using this method and architecture scheme is limited.
  • high traffic and low latency requirements such as: wireless communication base station equipment that needs to support multi-cell, multi-carrier, and multi-user equipment (User Equipment, UE), the decoding traffic demand may reach more than 10Gbps.
  • DSP Digital Signal Processing
  • FPGA Field Programmable Gate Array
  • GPU Graphics Processing Unit
  • ASIC Application Specific Integrated Circuit
  • Embodiments of the present disclosure provide a decoding method, a decoding device, and a decoder to at least solve the problems of high hardware resource consumption and difficulty in flexible application caused by excessive parallelism of decoders in the related art.
  • a decoding method includes: setting a parallelism P of a decoder, and splitting the soft information of the block to be decoded according to the parallelism P; Decode and calculate the block to be decoded according to the split information, and output the decoded hard bit information; reorganize the hard bit information according to the parallelism P.
  • a decoding device includes: an information splitting module for setting a parallel degree P of the decoder, and according to the parallel degree P to the block to be decoded The soft information of the information is split; the decoding module is used to decode the block to be decoded according to the split information and output the decoded hard bit information; the information reorganization module is used to The parallel degree P reorganizes the hard bit information.
  • a decoder including a memory and a processor, a computer program is stored in the memory, the processor is configured to run the computer program to perform the method of the above embodiment step.
  • a storage medium in which a computer program is stored, wherein, when the computer program is executed by a processor, the method steps of the above embodiments are executed.
  • FIG. 1 is a flowchart of a decoding method according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a decoding device according to an embodiment of the present disclosure
  • FIG. 3 is another schematic structural diagram of a decoding device according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an implementation manner of information splitting according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a decoding module according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a decoding method according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a calculation module according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic flowchart of verification according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of an implementation manner of information reorganization according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a decoder according to an embodiment of the present disclosure.
  • variable parallelism LDPC decoder design is provided, which avoids the problems of excessive hardware resource consumption and difficulty in flexible application due to excessive parallelism of the decoder, and is effective
  • the flexibility of the LDPC decoder in different scenarios is improved, and the resource consumption of the decoder can be reduced.
  • FIG. 1 is a flowchart of decoding according to an embodiment of the present disclosure. As shown in FIG. 1, the process includes the following steps:
  • Step S102 Set the parallelism P of the decoder, and split the soft information of the block to be decoded according to the parallelism P;
  • Step S104 Perform decoding calculation on the block to be decoded according to the split information, and output decoded hard bit information
  • Step S106 Reorganize the hard bit information according to the parallelism P.
  • the parallelism P of the decoder can be based on different application scenarios, data services, such as throughput and delay requirements of the decoder, and the cost of hardware resources or chip area acceptable to users.
  • the cost is set by the user with reasonable choice, and P ⁇ Max(Z set ), that is, P is less than or equal to the maximum spreading factor in the spreading factor set Z set of the supported LDPC code.
  • step S102 the soft information to be decoded is split.
  • the soft information of the input block to be decoded CB is split according to certain rules.
  • Information splitting is mainly to split all "block" information of size Z in one CB into T "sub-block” information. The principle of information splitting will be described in detail below.
  • decoding calculation is performed.
  • the decoding calculation process is based on the "layered decoding” method, and time-sharing is performed in the decoding calculation process of each layer, that is, “layered-time-shared decoding".
  • “Layered decoding” is to process all "block” information of size Z in parallel in the decoding calculation process of each layer, and sequentially serialize pipeline processing between "block” and "block”.
  • “Layer-time-sharing decoding” is to split each "block” information of size Z into T "sub-block” information.
  • the "sub-block” information is processed in parallel, and the sub-block and the "sub-block” are serially pipelined to complete the decoding of one layer in T times.
  • the Z check lines in each layer are divided into T parts, and the decoding calculation of the Z check lines is completed in a time-sharing manner in T times; if T is equal to 1, each "block” information is processed Decoding, that is, the decoding calculation of Z check lines is completed in a fully parallel manner; if T is greater than 1, each "sub-block” information is decoded, that is, in a partially parallel manner, Z/
  • T check lines the calculation of Z check lines in one layer is completed in T times; after the decoding calculation in one layer is completed, the decoding calculation in the next layer is performed.
  • the hard bit information is reassembled after decoding in step S106.
  • the hard bit information output after decoding is reorganized.
  • the decoded hard bit information reorganization is the inverse process of the soft information split before decoding.
  • the information of one hard bit "sub-block” is reorganized into the corresponding hard bit "block” information, and then the "block” information is output as a CB block. The principle of information reorganization will be described in detail below.
  • a decoding device is also provided.
  • the device is used to implement the above-mentioned embodiments and preferred implementation modes, and those that have already been described will not be repeated.
  • the term "module” may implement a combination of software and/or hardware that performs predetermined functions.
  • the devices described in the following embodiments are preferably implemented in software, implementation of hardware or a combination of software and hardware is also possible and conceived.
  • the decoding device includes an information splitting module 10, a decoding module 20, and an information restructuring module 30.
  • the information splitting module 10 is configured to set the parallelism P of the decoder, and split the soft information of the block to be decoded according to the parallelism P.
  • the decoding module 20 is configured to perform decoding calculation on the block to be decoded according to the split information, and output decoded hard bit information.
  • the information reassembly module 30 is configured to reorganize the hard bit information according to the parallelism P.
  • the above modules can be implemented by software or hardware. In the case of hardware, it can be implemented in the following manner, but not limited to this: the above modules are all located in the same processor; or, the above modules are located in different processors in any combination.
  • An embodiment of the present disclosure also provides a decoder including the above-described decoding device and necessary storage components.
  • the decoder may be a structured quasi-cyclic low density parity check code (QC-LDPC, Quasi-Cyclic Low Density Parity-check Code) decoder.
  • QC-LDPC quasi-cyclic low density parity check code
  • Quasi-Cyclic Low Density Parity-check Code Quasi-Cyclic Low Density Parity-check Code
  • An embodiment of the present disclosure also provides a storage medium in which a computer program is stored, wherein the computer program is set to execute the steps in the above embodiments when it is run.
  • Z set the expansion factor set supported by the designed decoder
  • Z the expansion factor actually used by the code block to be decoded, Z ⁇ Z set ;
  • T Decoding time division number of the code block to be decoded, that is, time division number
  • L the number of basic matrix rows or layers used in the code block to be decoded
  • K the number of basic matrix columns used in the code block to be decoded
  • k decoding column index of the code block to be decoded, 0 ⁇ k ⁇ K-1;
  • QC-LDPC codes are an important type of structured LDPC codes.
  • the coding matrix is generally represented by a basic matrix H (L ⁇ K) with L rows (layers), K columns, and an expansion factor Z.
  • the non--1 element in the basic matrix is replaced by the Z-dimensional identity matrix or its cyclic shift matrix.
  • the shift value of the cyclic shift matrix is the value of this element, and the “-1” element in the basic matrix is Z ⁇ Z Dimension 0 matrix instead.
  • the matrix H(L*Z ⁇ K*Z) obtained by expanding the basic matrix using the Z ⁇ Z dimension “sub-matrix” has L ⁇ Z rows and K ⁇ Z columns, and the expanded matrix has L layers, Layer Z check lines, and used as the coding matrix of QC-LDPC codes.
  • decoding also uses this matrix for decoding and verification.
  • the decoding process mainly includes information splitting, decoding calculation, and information reassembly. Each process is described in detail below.
  • the soft information of the CB block to be decoded C [B 0 , B 1 , B 2 ,..., B K-1 ], including K “blocks” B k , and each “block” contains Z soft information Q, which is And it corresponds to the "sub-matrix" (or k-th variable node) of the kth column of the basic matrix H(L*K).
  • each "block” Before decoding, each "block” needs to be split according to the set decoder parallelism P and the expansion factor Z configured in the CB block to be decoded.
  • the key of this splitting method is that each splitting block obtained by splitting the "blocks” still satisfies the cyclic shift characteristics.
  • the "block” splitting steps include: first, determine the decoding time division number T, T is the smallest positive integer that can divide Z and not less than (Z/P); then, each "block” B k is split into T "sub-blocks" Where i represents the "sub-block” index, ie:
  • each "sub-block” is expressed as follows:
  • each "sub-block” Contains Z/T soft information to be decoded.
  • index i the shift value corresponding to the "block” in that layer must be used S l,k select the corresponding "sub-block” Participate in this time-sharing decoding, index i pairs by "sub-block"
  • the index i calculation rules are as follows:
  • each time-division decoding must be based on the corresponding shift of the "block” in that layer
  • the value Sl, k calculates the sub-shift value needed for time-sharing decoding Subshift value
  • the prior information B k,t can be addressed , and the prior information B k,t is subjected to “layer-time-sharing decoding”.
  • the "layered-time-shared decoding" process is as follows:
  • Step 1 Address the prior information B k,t .
  • Step 2 Positive cyclic shift.
  • B k,t and the shift value of the data Perform cyclic shift to obtain a priori information after cyclic shift which is:
  • N(l) represents the set of index k of all "blocks" B k participating in the decoding of the first layer, that is, all non-"- in the first layer of the basic matrix H(L ⁇ K)
  • the set of column index k corresponding to the 1" element, cyclic_shift(,) represents a positive cyclic shift function.
  • Step 3 Calculate variable node information Variable node information
  • Step 4 Calculate check node information Check node information
  • N(l) Represents the information of the k-th new check node in the l-th layer and the t-th time-sharing decoding
  • N(l) ⁇ k represents the set of all variable node indexes k′ in the set N(l) except for k.
  • Update old check node information which is:
  • Step 5 Calculate the posterior information Posterior information
  • Step 6 Reverse cyclic shift.
  • Shift value Posterior information Perform reverse cyclic shift to obtain the posterior information new_B k,t after cyclic shift, namely:
  • k ⁇ N (l), inv_cyclic_shift (,) represents the reverse cyclic shift function.
  • Step 7 Update a priori information.
  • update the corresponding "sub-block" with B k,t which is Where i Mod(S l,k +t,T).
  • each soft information "sub-block" is expressed as follows:
  • each soft information "sub-block” Contains Z/T soft information.
  • the hard bit information S sign (Q), sign () is a sign function, 0 ⁇ i ⁇ T-1, 0 ⁇ k ⁇ K-1, each hard bit "sub-block" Contains Z/T hard bit information.
  • T hard bits "sub-block” information Reorganized into hard bit "block” information Hk Hk information is expressed as follows:
  • H k [S Z*k+0 ,S Z*k+1 ,S Z*k+2 ,...,S Z*k+Z-1 ]
  • Embodiment 2 provides a decoder that implements the above decoding process.
  • FIG. 3 is a structural block diagram of the decoder of this embodiment.
  • the decoder includes an information splitting module 10, a decoding module 20, and an information restructuring module 30.
  • the information splitting module 10 completes the soft information splitting function before decoding.
  • the decoding module 20 performs the "layered-time-sharing decoding" iterative calculation function.
  • the information reassembly module 30 completes the output of the decoded hard bit information.
  • the information splitting module and the information reassembling module may be located inside the decoding device or outside the decoding device.
  • the module first calculates the available decoding time division T according to the preset decoder parallelism P and the expansion factor Z of the CB block to be decoded.
  • the time-sharing number T can also be obtained through parameter configuration after being calculated outside the decoder.
  • After obtaining the parameter T first extract each “block” information in the CB block information storage space according to the expansion factor Z.
  • Each “block” information is continuously stored in the storage space with a fixed storage bit width. It is necessary to extract the "block” information before dividing.
  • FIG. 5 An optional structural schematic diagram of the decoding module 20 is shown in FIG. 5 and includes: a decoding control module 201, a soft information storage module 202, a positive shift module 203, a calculation module 204, an inverse shift module 205, and a hard decision Module 206, hard bit information storage module 207 and check module 208.
  • Each module completes the functions of storing, processing, and calculating the data information input to the module according to the parameter information required by the module.
  • FIG. 6 is a schematic diagram of the decoding process of the decoding module. As shown in FIG. 6, the i-th decoding iteration, the first-layer decoding calculation, and the t-th time-sharing decoding calculation are started in a loop nesting manner. First complete all T time-sharing decoding of the first layer, and then perform decoding calculation of the second layer until all decoding calculations of the L layer are completed. Then, the loop ends by judging whether the decoding is successful and the number of decoding iterations.
  • the t-th time-sharing decoding calculation includes the following steps:
  • Step 1 Perform prior information addressing and calculate sub-shift value
  • Step 2 Perform positive cyclic shift on the corresponding prior information according to the sub-shift value
  • Step 3 Calculate variable node information using the shifted prior information minus the old check node information, where the first iteration check node information is initialized to 0;
  • Step 4 calculate the check node information, use the variable node information obtained in step 3 to calculate the new check node information, and use the new check node information to refine the old check node information;
  • Step 5 calculating the posterior information, using the variable node information obtained in step 3 plus the new check node information obtained in step 4, to obtain posterior information;
  • Step 6 Perform reverse circular shift on the posterior information obtained in Step 5 according to the sub-shift value
  • step 7 the prior information is updated using the shifted posterior information obtained in step 6.
  • step 7 it is judged whether the maximum time-sharing number T is reached, and the next time-sharing decoding or the first time-sharing decoding of the next layer is performed according to the judgment.
  • the next time-sharing decoding or the time-sharing decoding process of the next layer is the same as the above-mentioned decoding process, and will not be repeated here.
  • the soft information storage module 202 is configured to: receive the new CB block information to be decoded output by the information splitting module, and each CB block is stored in a "sub-block" information storage format after the information split.
  • the soft information storage module 202 is configured to receive the posterior information of the currently decoded CB block output by the reverse shift module, and store and back up the posterior information data updated in each iteration.
  • the new CB and the decoding CB are switched using the "ping pong" method.
  • the soft information storage module 202 also reads and outputs the a priori information to be decoded according to the read and write address information output by the control module 201, and stores and updates the newly calculated a posteriori information.
  • the storage bit width of the soft information storage module 202 is determined by the preset decoder parallelism.
  • the forward shift module 203 and the reverse shift module 205 may be provided separately or in combination.
  • An alternative solution is to use the QSN (QC-LDPC Shift Network) shift network to achieve.
  • the advantage of the QSN shift network is that it can cyclically shift the "sub-block” information of different sizes.
  • the forward shift module 203 and the reverse shift module 205 shift and output the input “sub-block” information to be shifted according to the shift value information input by the decoding control module 201.
  • the forward shift module 203 and the reverse shift module 205 adopt a shift network with P input and P output according to a preset parallel degree P.
  • the calculation module 204 is configured to calculate variable node information, check node information, and posterior information according to the input prior information, output the posterior information, and perform parallel calculation and storage according to a preset parallel degree P.
  • 7 is a schematic diagram of an optional structure of a calculation module. As shown in FIG. 7, the calculation module includes: P parallel variable node calculation units, P parallel check node calculation units, and P parallel posteriors Information calculation unit, and variable node storage unit and check node storage unit with parallel degree P.
  • variable node calculation unit is configured to calculate variable node information by subtracting the old check node information from the input prior information, wherein the old check node information is initialized to 0 during the first iteration calculation process.
  • decoder parallelism P at most P variable node calculation units are used to complete the calculation of the variable node information corresponding to each "sub-block" information in parallel.
  • the check node calculation unit is configured to calculate the corresponding new check node information according to the input variable node information, wherein the calculation of the new check node information may use but is not limited to the minimum sum (MS, Min-Sum) algorithm, One or other of the normalized minimum sum (NMS, Normalised Offset) algorithm and the offset minimum sum (OMS, Offset Min-Sum) algorithm.
  • MS, Min-Sum minimum sum
  • NMS Normalised Offset
  • OMS Offset Min-Sum
  • OMS Offset Min-Sum
  • the posterior information calculation unit is configured to calculate the posterior information by inputting the variable node information plus the new check node information. According to the decoder parallelism P, at most P posterior information calculation units are used to complete the calculation of the posterior information corresponding to each "sub-block" information in parallel.
  • variable node information storage unit is configured to store the variable node information output by the variable node calculation unit, and output the corresponding variable node information to the posterior information calculation unit to calculate the posterior information.
  • the variable node data output by at most P variable node calculation units are stored in parallel at the same address, and the storage bit width should ensure that the P variable node data can be written or read in parallel.
  • the check node information storage unit is configured to output the corresponding old check node information to the variable node calculation unit to calculate the variable node information, wherein the first decoding iteration calculates that the old check node information is initialized to 0.
  • the check node information storage unit is further configured to: use the new check node information output by the check node calculation unit of this decoding iteration to update the old check node information cached in the previous iteration.
  • the check node data output by at most P check node calculation units are stored in parallel at the same address, and the storage bit width thereof should ensure that the P check node data can be written or read in parallel.
  • the hard decision module 206 is configured to make a hard decision on the posterior information output by the inverse shift module.
  • the hard decision process is to hard decide the posterior information expressed in the form of soft information into hard bit information.
  • An optional implementation is to perform a sign function calculation on the soft information, that is, to obtain the hard bit information by taking the sign bit of the soft information. According to the preset parallel degree P of the decoder, the hard decision module supports the symbol calculation with the parallel degree P.
  • the hard bit information storage module 207 is configured to cache hard decision information output by two consecutive decoding iterations. For example, the hard decision result output by this iteration and the hard decision result of the previous iteration are ping-pong buffered. On the one hand, the hard decision storage module caches the hard decision results output in this iteration during this iteration. On the other hand, the hard decision result of the previous iteration is output at the same time as the calculation of this iteration, and it is sent to the verification module and the information reorganization module, respectively. The verification module verifies the hard decision result of the previous iteration; and the information reorganization module caches and backs up the hard decision result of the previous iteration.
  • the verification module passes the verification, the hard decision result of the previous iteration is reorganized and output, otherwise the cache of the hard decision result of the previous iteration is released.
  • the storage bit width of the hard bit information storage module is P, and the depth can store two maximum hard bit CB blocks ping-pong.
  • the verification module 208 is configured to verify the hard decision result after an iterative decoding, determine whether the condition for terminating the iterative decoding is satisfied, and if it is satisfied, output a decoding termination signal, otherwise not output and continue to the next iteration.
  • Decoding iteration termination conditions include but are not limited to the following: 1) H matrix parity check passed; 2) CRC check passed; 3) H matrix parity check and CRC check passed simultaneously; 4) The minimum number of iterations was reached and the maximum was reached The number of iterations, etc. 8 is a flowchart of decoding verification according to an embodiment of the present disclosure.
  • the information reassembly module 30 is configured to calculate the available decoding time division number T according to the preset decoder parallelism P and the expansion factor Z of the CB block to be decoded.
  • the time-sharing number T can also be obtained through parameter configuration after being calculated outside the decoder.
  • FIG. 9 is an optional implementation manner that information reorganization may adopt. As shown in FIG.
  • the index read in the hard bit “sub-block” information storage space belongs to the same “block” H k All "subblock” information
  • the hard-bit "block” information H k is obtained , and then all the first KL hard-bit "block” information representing information columns are reassembled and spliced, and the final translation is output in the form of CB blocks The result after the code.
  • An embodiment of the present disclosure also provides a decoder 100, which includes a memory 110 and a processor 120.
  • the memory 110 stores a computer program
  • the processor 120 is configured to run the computer program to execute the foregoing embodiment. Method steps.
  • An embodiment of the present disclosure also provides a storage medium in which a computer program is stored, wherein the computer program is set to execute the method steps of the foregoing embodiments when it is run.
  • the parallelism of the coder can be flexibly set, and the user can select the optimal parallelism for the design of the decoder by combining the requirements such as traffic, delay, resource consumption, and chip area. , On the premise of meeting the performance requirements of the decoder, the cost is minimized.
  • the decoder can be compatible with multiple expansion factors online, compatible with multiple matrices, compatible with multiple bit rates online, decoder structure, resource consumption and The size of the matrix is irrelevant, which improves the flexibility and compatibility of the decoder;
  • a single "block” in the decoding process, a single "block” can be processed in parallel, a serial pipeline processing method between “block” and “block”, all “block” information can be shared and stored, No need to allocate storage for each "block” information independently, reducing the consumption of storage resources;
  • modules or steps of the present disclosure can be implemented by a general-purpose computing device, and they can be concentrated on a single computing device or distributed in a network composed of multiple computing devices
  • they can be implemented with program code executable by the computing device, so that they can be stored in the storage device to be executed by the computing device, and in some cases, can be in a different order than here
  • the steps shown or described are performed, or they are made into individual integrated circuit modules respectively, or multiple modules or steps among them are made into a single integrated circuit module to achieve. In this way, the present disclosure is not limited to any specific combination of hardware and software.

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Abstract

本发明提供了一种译码方法、译码装置及译码器。该译码方法包括：设置译码器的并行度P，并根据所述并行度P对待译码块的软信息进行信息拆分；根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息；根据所述并行度P将所述硬比特信息进行信息重组。在本发明中，由于在译码设计时可以根据设计所需的译码器吞吐量、可接受的资源消耗、硬件成本等，灵活选择译码器的并行度，因此，可以解决并行度过大所带来的硬件资源消耗大、难以灵活应用的问题，达到提高译码器的应用灵活性。

Description

译码方法、译码装置及译码器 技术领域
本公开涉及但不限于无线通信领域，具体而言，涉及一种译码方法、译码装置及译码器。
背景技术
随着多媒体广播、无线通信、超大规模集成电路(Very Large Scale Integration，VLSI)技术的不断发展，低密度奇偶校验码(Low Density Parity Check，LDPC)作为最接近香农极限的前向纠错编码已经被广泛应用在数字视频广播(Digital Video Broadcast，DVB)、无线局域网(Wireless Local Area Network，WLAN)、全球互通微波接入(Worldwide Interoperability for Microwave Access,WiMAX)等通信标准中，而且首次被选为5G移动通信系统中增强型移动宽带业务(enhance Mobile Broadband,eMBB)的数据信道编码方案。面临着未来5G(Generation)移动通信系统中大容量、低时延、高可靠的业务需求，以及各种不同的应用场景需求，设计高性能、低成本、灵活的LDPC译码器成为无线通信领域主要的技术挑战。
灵活性方面，在5G移动通信系统的数据业务信道中，数据业务的码长灵活多变。码长包括长码和短码。根据3GPP TS 38.212 Release15协议，5G基带信道编码采用准循环LDPC码(Quasi Cyclic Low Density Parity Check,QC-LDPC)编码方式，需要兼容多达51种扩展因子、2种基础矩阵。这为LDPC译码器的灵活性设计带来很大难度。
成本方面，LDPC译码器的并行度决定资源消耗。基于“块并行”架构的译码器并行度与所支持的扩展因子成正比。为了支持5G标准中最大扩展因子，译码器并行度通常很大，导致单个译码器资源消耗较大。这样，在一些硬件资源和成本受限，流量需求较小的应用场景中，如：智能终端、物联网(Internet of Things,IoT)等场景，就会造成译码 器的性能过剩，硬件资源浪费，性价比低。因此，需要设计并行度小、资源消耗少的LDPC译码器。
性能方面，目前在业界LDPC译码器大多采用基于分层译码(Layered-decoding)方法的“块并行”架构实现，采用该方法及架构方案所设计的译码器峰值吞吐率性能有限。在大流量、低时延需求的应用场景下时，如：需要支持多小区、多载波、多用户设备(User Equipment,UE)的无线通信基站设备，译码流量需求可能达到10Gbps以上。此时，无论是基于数字信号处理(Digital Signal Processing，DSP)、现场可编程门阵列(Field Programmable Gate Array，FPGA)、图形处理器(Graphics Processing Unit,GPU)，还是专用集成电路(Application Specific Integrated Circuit，ASIC)芯片所设计的译码器，其单核处理能力基本难以满足系统系能需求，需要多核并行加速。
发明内容
本公开实施例提供了一种译码方法、译码装置及译码器，以至少解决相关技术中译码器并行度过大所带来的硬件资源消耗大、难以灵活应用的问题。
根据本公开的实施例，提供了一种译码方法，该方法包括：设置译码器的并行度P，并根据所述并行度P对所述待译码块的软信息进行信息拆分；根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息；根据所述并行度P将所述硬比特信息进行信息重组。
根据本公开的实施例，还提供了一种译码装置，该装置包括：信息拆分模块,用于设置译码器的并行度P，并根据所述并行度P对所述待译码块的软信息进行信息拆分；译码模块，用于根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息；信息重组模块，用于根据所述并行度P将所述硬比特信息进行信息重组。
根据本公开的实施例，还提供了一种译码器，包括存储器和处理 器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述实施例的方法步骤。
根据本公开的实施例，还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序在被处理器运行时执行上述实施例的方法步骤。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本申请的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的限定。在附图中：
图1是根据本公开实施例的译码方法的流程图；
图2是本公开实施例的译码装置的结构示意图；
图3是本公开实施例的译码装置的另一结构示意图；
图4为本公开实施例的信息拆分实现方式的示意图；
图5为本公开实施例的译码模块的结构示意图；
图6为本公开实施例的译码方法的流程示意图；
图7为本公开实施例的计算模块的结构示意图；
图8为本公开实施例的校验的流程示意图；
图9为本公开实施例的信息重组实现方式的示意图；
图10为本公开实施例的译码器的结构示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
根据本公开的一个实施例的译码的方法，提供了可变并行度的LDPC译码器设计，避免因译码器并行度过大带来的硬件资源消耗大、难以灵活应用的问题，有效提高了LDPC译码器在不同场景应用的灵 活性，能够降低译码器的资源消耗。
图1是根据本公开实施例的译码的流程图，如图1所示，该流程包括如下步骤：
步骤S102，设置译码器的并行度P，并根据所述并行度P对待译码块的软信息进行信息拆分；
步骤S104，根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息；以及
步骤S106，根据所述并行度P将所述硬比特信息进行信息重组。
在上述实施例中，译码器的并行度P，可以根据不同的应用场景、数据业务对译码器的吞吐量、时延等指标要求，以及根据用户可接受的硬件资源或芯片面积等成本花费，由用户合理选择设置，且P≤Max(Z set)，即P小于或等于所支持的LDPC码的扩展因子集Z set中的最大扩展因子。
在步骤S102进行待译码软信息拆分。根据并行度P以及待译码块CB(Code Block)的扩展因子Z，将输入的待译码块CB的软信息按照一定规则进行信息拆分。信息拆分主要是将一个CB中的所有大小为Z的“块”信息都拆分为T个“子块”信息。在下文中将会详细描述信息拆分原理。
在步骤S104进行译码计算。译码计算过程是在“分层译码”方法的基础上，在每层的译码计算过程中又进行了分时，即“分层-分时译码”。“分层译码”是在每层的译码计算过程中对每个大小为Z的“块”信息全并行处理，“块”与“块”之间依次串行流水处理。“分层-分时译码”是将每个大小为Z的“块”信息拆分为T个“子块”信息。在每层的译码计算过程中对“子块”信息进行并行处理，“子块”与“子块”之间串行流水处理，分T次完成一层的译码。也就是说，将每层中的Z个校验行分成T份，分T次以分时方式完成Z个校验行的译码计算；如果T等于1，则对每个“块”信息进行译码，即以全并行方式，一次 完成Z个校验行的译码计算；如果T大于1，则对每个“子块”信息进行译码，即以部分并行方式，每次完成Z/T个校验行的计算，分T次完成一层Z个校验行的计算；完成一层译码计算后进行下一层译码计算。
在步骤S106进行译码后硬比特信息重组。根据并行度P以及待译码CB块的扩展因子Z，将译码后输出的硬比特信息进行信息重组，译码后的硬比特信息重组是译码前软信息拆分的逆过程，将每个硬比特“子块”信息重组为对应的硬比特“块”信息，再将“块”信息以CB块方式输出。在下文中将会详细描述信息重组原理。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现。当然也可以通过硬件实现。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来。
在本公开的一个实施例中还提供了一种译码装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图2是根据本公开实施例的译码装置的结构框图，如图2所示，该译码装置包括信息拆分模块10、译码模块20和信息重组模块30。
信息拆分模块10，被构造成设置译码器的并行度P，并根据所述并行度P对待译码块的软信息进行信息拆分。
译码模块20，被构造成根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息。
信息重组模块30，被构造成根据所述并行度P将所述硬比特信息进行信息重组。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的。在硬件的情况下，可以通过以下方式实现，但不限于此：上述模块均 位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
本公开的实施例还提供了一种译码器，该译码器包括上述译码装置和必要的存储部件。该译码器可以为一种结构化的准循环低密度奇偶校验码(QC-LDPC，Quasi-Cyclic Low Density Parity-check Code)译码器。
本公开的实施例还提供了一种存储介质，该存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述实施例中的步骤。
实施例1
下面结合实施例1详细描述本公开的译码实现过程。为便于方案描述，首先定义相关符号含义如下：
P：所设计译码器的硬件并行度；
Z set：所设计译码器支持的扩展因子集；
Z：待译码码块实际所采用的扩展因子，Z∈Z set；
T：待译码码块的译码分时数，即分时数；
t：待译码码块的译码分时索引号，0≤t≤T-1；
L：待译码码块所采用基础矩阵行数，或层数；
l：待译码码块的译码层索引，0≤l≤L-1；
K：待译码码块所采用基础矩阵列数；
k：待译码码块的译码列索引，0≤k≤K-1；
S l,k：待译码码块基础矩阵的l行k列所对应移位值；
Figure PCTCN2019117991-appb-000001
待译码码块基础矩阵的l行k列t分时所对应的分时移位值；
QC-LDPC码是结构化LDPC码中的一类重要码型，其编码矩阵一般用一个L行(层)、K列的基础矩阵H(L×K)和一个扩展因子Z来表示。基础矩阵中的非“-1”元素用Z维单位阵或其循环移位矩阵代替， 循环移位矩阵的移位值即为该元素值，基础矩阵中的“-1”元素用Z×Z维的0阵代替。这样，利用Z×Z维“子矩阵”对基础矩阵进行扩展后得到的矩阵H(L*Z×K*Z)共有L×Z行和K×Z列，扩展后的矩阵共有L层，每层Z个校验行，并作为QC-LDPC码的编码矩阵。同样，译码也使用该矩阵进行译码和校验。
在本实施例中，译码过程主要包括信息拆分、译码计算和信息重组。下面各个过程进行详细描述。
信息拆分：
待译码CB块软信息C＝[B 0,B 1,B 2,...,B K-1]，包含K个“块”B k，每个“块”包含Z个软信息Q，即
Figure PCTCN2019117991-appb-000002
且与基础矩阵H(L×K)的第k列“子矩阵”(或第k变量节点)对应。
译码前需要根据所设译码器并行度P以及待译码CB块所配置扩展因子Z对每个“块”进行拆分。该拆分方法的关键在于：采用该拆分方法对“块”拆分后得到的每个“子块”仍满足循环移位特性。“块”拆分步骤包括：首先，确定译码分时数T，T为可以整除Z且不小于(Z/P)的最小正整数；然后，将每个“块”B k都拆分为T个“子块”
Figure PCTCN2019117991-appb-000003
其中i表示“子块”索引，即：
Figure PCTCN2019117991-appb-000004
其中，每个“子块”表示如下：
Figure PCTCN2019117991-appb-000005
其中，0≤i≤T-1，0≤k≤K-1，每个“子块”
Figure PCTCN2019117991-appb-000006
包含Z/T个待译码软信息。
在每层的每次分时译码过程中，例如第l层，对于每个“块”B k在每次分时译码时，都要根据该“块”在该层对应的移位值S l,k选择对应的“子块”
Figure PCTCN2019117991-appb-000007
参与该次分时译码，通过“子块”索引i对
Figure PCTCN2019117991-appb-000008
进行寻址， 索引i计算规则如下：
第l层第0次分时译码：i＝Mod(S l,k+0,T)
第l层第1次分时译码：i＝Mod(S l,k+1,T)
第l层第2次分时译码：i＝Mod(S l,k+2,T)
以此类推：
第l层第T-1次分时译码：i＝Mod(S l,k+T-1,T)
即：第l层第t次分时译码需要寻址的“子块”记为B k,t，B k,t也叫先验信息，
Figure PCTCN2019117991-appb-000009
其中i＝Mod(S l,k+t,T)，t为分时索引t＝0,1,2,...,T-1。
同时，在每层的每次分时译码过程中，例如第l层，对于每个“块”B k在每次分时译码时都要根据该“块”在该层对应的移位值S l,k计算分时译码所需要的子移位值
Figure PCTCN2019117991-appb-000010
子移位值
Figure PCTCN2019117991-appb-000011
计算规则如下：
第l层第0次分时译码：
Figure PCTCN2019117991-appb-000012
第l层第1次分时译码：
Figure PCTCN2019117991-appb-000013
第l层第2次分时译码：
Figure PCTCN2019117991-appb-000014
以此类推：
第l层第T-1次分时译码：
Figure PCTCN2019117991-appb-000015
即：第l层第t次分时译码所需的子移位值
Figure PCTCN2019117991-appb-000016
其中，t为分时索引(t＝0,1,2,...,T-1)。
译码计算：
完成由“块”信息到“子块”信息的信息拆分后，以及完成子移位值计算得到
Figure PCTCN2019117991-appb-000017
后，即可寻址得到先验信息B k,t，对先验信息B k,t进行“分层-分时译码”。以第l层、第t分时为例，“分层-分时译码”过程如下：
步骤1：寻址先验信息B k,t。根据分时索引t与“子块”索引i的关系i＝Mod(S l,k+t,T)，以及移位值S l,k，完成先验信息寻址，即
Figure PCTCN2019117991-appb-000018
同时，完成子移位值
Figure PCTCN2019117991-appb-000019
的计算，即
Figure PCTCN2019117991-appb-000020
步骤2：正循环移位。对先验信息B k,t跟据子移位值
Figure PCTCN2019117991-appb-000021
进行循环移位，得到循环移位后先验信息
Figure PCTCN2019117991-appb-000022
即：
Figure PCTCN2019117991-appb-000023
其中，k∈N(l)，N(l)表示所有参与第l层译码的“块”B k的索引k的集合，即基础矩阵H(L×K)第l层中所有非“-1”元素所对应的列索引k的集合，cyclic_shift(,)表示正循环移位函数。
步骤3：计算变量节点信息
Figure PCTCN2019117991-appb-000024
变量节点信息
Figure PCTCN2019117991-appb-000025
其中，k∈N(l)，
Figure PCTCN2019117991-appb-000026
表示第l层、第t次分时译码的第k个变量节点信息，
Figure PCTCN2019117991-appb-000027
表示第l层、第t次分时译码的第k个旧校验节点信息，在首次迭代译码时
Figure PCTCN2019117991-appb-000028
被初始化为0；
步骤4：计算校验节点信息
Figure PCTCN2019117991-appb-000029
校验节点信息
Figure PCTCN2019117991-appb-000030
其中，k∈N(l)，
Figure PCTCN2019117991-appb-000031
表示第l层、第t次分时译码的第k个新 校验节点信息，N(l)\k表示集合N(l)中除去k后的所有变量节点索引k′的集合。
同时，用新计算得到的校验节点信息
Figure PCTCN2019117991-appb-000032
更新旧校验节点信息
Figure PCTCN2019117991-appb-000033
即：
Figure PCTCN2019117991-appb-000034
步骤5：计算后验信息
Figure PCTCN2019117991-appb-000035
后验信息
Figure PCTCN2019117991-appb-000036
其中，k∈N(l)。
步骤6：逆循环移位。跟据子移位值
Figure PCTCN2019117991-appb-000037
对后验信息
Figure PCTCN2019117991-appb-000038
进行逆循环移位，得到循环移位后的后验信息new_B k,t，即：
Figure PCTCN2019117991-appb-000039
其中，k∈N(l)，inv_cyclic_shift(,)表示逆循环移位函数。
步骤7：更新先验信息。用移位后的后验信息new_B k,t更新先验信息B k,t，目的是将本次迭代输出的后验信息作为下次迭代初始的先验信息，即B k,t＝new_B k,t，其中k∈N(l)。同时，用B k,t更新对应的“子块”
Figure PCTCN2019117991-appb-000040
即
Figure PCTCN2019117991-appb-000041
其中，i＝Mod(S l,k+t,T)。
完成以上步骤后，即完成了本次译码迭代中的第l层、第t次分时的译码计算，若t＜T-1，则t＝t+1，继续进行l层的第t+1次分时计算，否则完成第l层的译码计算；若l＜L-1，则l＝l+1，继续进行l+1层的计算，否则完成本次迭代计算，进行下一次迭代计算，直到译码成功或达到最大迭代次数后停止迭代译码。
在每次迭代完成后需要对软信息进行硬判决，得到硬比特信息以供终止检测或译码输出。一次迭代后每个软信息“子块”表示如下：
Figure PCTCN2019117991-appb-000042
其中，0≤i≤T-1，0≤k≤K-1，每个软信息“子块”
Figure PCTCN2019117991-appb-000043
包含Z/T个 软信息。软信息“子块”
Figure PCTCN2019117991-appb-000044
经过硬判决后得到硬比特“子块”
Figure PCTCN2019117991-appb-000045
表示如下：
Figure PCTCN2019117991-appb-000046
其中，硬比特信息S＝sign(Q)，sign()为符号函数，0≤i≤T-1，0≤k≤K-1，每个硬比特“子块”
Figure PCTCN2019117991-appb-000047
包含Z/T个硬比特信息。
信息重组：
信息重组是对硬判决得到的硬比特“子块”数据重组为硬比特“块”数据，并将所有的硬比特“块”数据以硬比特CB块方式输出。根据分时数T，将T个硬比特“子块”信息
Figure PCTCN2019117991-appb-000048
重组为硬比特“块”信息H k，H k信息表示如下：
H k＝[S Z*k+0,S Z*k+1,S Z*k+2,...,S Z*k+Z-1]
其中，0≤k≤K-L-1，即只需将基础矩阵前K-L个信息列对应的“块”进行重组输出，忽略校验列信息。将K-L个硬比特“块”信息H k组合为硬比特CB块数据输出，即，硬比特CB块信息C＝[H 0,H 1,H 2,...,H K-L-1]。
实施例2
实施例2提供了一种实现上述译码过程的译码器，图3为本实施例的译码器结构框图。如图3所示，该译码器包括：信息拆分模块10、译码模块20和信息重组模块30。信息拆分模块10完成译码前的软信息拆分功能。译码模块20完成“分层-分时译码”迭代计算功能。信息重组模块30完成译码后的硬比特信息的重组输出。信息拆分模块和信息重组模块可以位于译码装置内部，也可以位于译码装置外部。
信息拆分模块10的一种具体实施方式如图4所示。该模块首先根据预设译码器并行度P，待译码CB块的扩展因子Z，计算得到可采用的译码分时数T。分时数T也可以在译码器外部计算好后通过参数配置得到。获得参数T后，首先根据扩展因子Z在CB块信息存储空间中依 次提取每个“块”信息，每个“块”信息以固定的存储位宽、连续存储在存储空间中，因此在信息拆分之前需要进行“块”信息的提取。得到整个“块”信息后根据分时数T对其进行拆分得到T个“子块”信息，并根据“子块”索引号分别存储在“子块”信息存储空间的不同地址区间，依次完成每个“块”信息的拆分和“子块”信息的存储。
译码模块20的一种可选的结构示意图如图5所示，包括：译码控制模块201，软信息存储模块202、正移位模块203、计算模块204、反移位模块205、硬判决模块206、硬比特信息存储模块207和校验模块208。每个模块根据本模块所需要的参数信息完成对输入到本模块的数据信息的存储、处理、计算等功能。
图6为译码模块的译码流程示意图，如图6所示，采用循环嵌套的方式，启动第i次译码迭代、第一层译码计算以及第t次分时译码计算。先完成第一层的所有T次分时译码，然后进行第二层的译码计算，直到完成所有L层的译码计算。然后，通过判断是否译码成功及译码迭代次数来结束循环。在一个示例性实施例中，第t次分时译码计算包括如下步骤：
步骤1，进行先验信息寻址，计算子移位值；
步骤2，根据子移位值对对应的先验信息进行正循环移位；
步骤3，利用移位后的先验信息减去旧的校验节点信息计算变量节点信息，其中首次迭代校验节点信息初始化为0；
步骤4，计算校验节点信息，利用步骤3得到的变量节点信息计算新校验节点信息，同时用新校验节点信息更细旧校验节点信息；
步骤5，计算后验信息，利用步骤3得到的变量节点信息加步骤4得到的新校验节点信息，得到后验信息；
步骤6，根据子移位值对步骤5得到的后验信息进行逆循环移位；
步骤7，利用步骤6得到的移位后的后验信息更新先验信息。
在步骤7后，判断是否达到最大的分时数T，根据判断进行下一次分时译码或下一层第1次分时译码。这里，下一次分时译码或下一 层的分时译码过程与上述译码过程相同，在此不累述。
一方面，软信息存储模块202被构造成：接收信息拆分模块输出的新的待译码CB块信息，每个CB块都是信息拆分后的以“子块”信息存储格式存储的。另一方面，软信息存储模块202被构造成：接收反移位模块输出的当前正在译码的CB块的后验信息，对每次迭代更新的后验信息数据进存储备份。新CB和正在译码CB采用“乒乓”方式进行切换。另外，软信息存储模块202还根据控制模块201输出的读写地址信息，对待译码的先验信息进行读取输出，对新计算输出的后验信息进行存储更新。软信息存储模块202的存储位宽由预设的译码器并行度决定。
正移位模块203和反移位模块205可以分设，也可以合设。一种可选的方案是采用QSN(QC-LDPC Shift Network)移位网络来实现，QSN移位网络的优点是可以对不同大小的“子块”信息进行循环移位。正移位模块203和反移位模块205根据由译码控制模块201输入的移位值信息，对输入的待移位的“子块”信息进行相应的移位并输出。正移位模块203和反移位模块205根据预设并行度P，采用P输入P输出的移位网络。
计算模块204被构造成：根据输入的先验信息，计算变量节点信息、校验节点信息、后验信息，输出后验信息，并根据预设并行度P进行并行计算和存储。图7为计算模块的一种可选的结构示意图，如图7所示，该计算模块包括：P个并行的变量节点计算单元、P个并行的校验节点计算单元、P个并行的后验信息计算单元，以及并行度为P的变量节点存储单元和校验节点存储单元。
变量节点计算单元被构造成：通过输入的先验信息减去旧的校验节点信息计算变量节点信息，其中首次迭代计算过程中旧校验节点信息初始化为0。根据译码器并行度P，最多采用P个变量节点计算单元并行完成每个“子块”信息对应的变量节点信息的计算。
校验节点计算单元被构造成：根据输入的变量节点信息计算对应 的新的校验节点信息，其中新的校验节点信息的计算可以采用但不限于最小和(MS，Min-Sum)算法、归一化最小和(NMS，Normalised Offset)算法、偏移量最小和(OMS，Offset Min-Sum)算法中的一种或其他算法。根据译码器并行度P，最多采用P个校验节点计算单元并行完成每个“子块”信息对应的校验节点信息的计算。
后验信息计算单元被构造成：通过输入的变量节点信息加上新的校验节点信息计算后验信息。根据译码器并行度P，最多采用P个后验信息计算单元并行完成每个“子块”信息对应的后验信息的计算。
变量节点信息存储单元被构造成：对变量节点计算单元输出的变量节点信息进行存储，并将相应的变量节点信息输出给后验信息计算单元进行后验信息的计算。根据译码器并行度P，最多P个变量节点计算单元输出的变量节点数据并行存储在同一个地址，其存储位宽要保证P个变量节点数据能够并行写入或读出。
校验节点信息存储单元被构造成：将相应的旧校验节点信息输出给变量节点计算单元进行变量节点信息的计算，其中第一次译码迭代计算旧校验节点信息初始化为0。校验节点信息存储单元还被构造成：，利用本次译码迭代的校验节点计算单元输出的新校验节点信息对上一次迭代缓存的旧校验节点信息进行更新。根据译码器并行度P，最多P个校验节点计算单元输出的校验节点数据并行存储在同一个地址，其存储位宽要保证P个校验节点数据能够并行写入或读出。
硬判决模块206被构造成：对反移位模块输出的后验信息进行硬判决。硬判决过程是将以软信息形式表示的后验信息硬判决为硬比特信息。一种可选的实施方案是对软信息进行符号函数计算，即取软信息的符号位得到硬比特信息。根据译码器预设并行度P，硬判决模块支持并行度为P的符号计算。
硬比特信息存储模块207被构造成：对连续两次译码迭代输出的硬判决信息进行缓存。例如，本次迭代输出的硬判决结果与前一次迭代的硬判决结果进行乒乓缓存。一方面，硬判决存储模块在本次迭代 过程中对本次迭代输出的硬判决结果进行缓存。另一方面，在本次迭代计算的同时输出前一次迭代的硬判决结果，分别到校验模块和信息重组模块。校验模块对前一次迭代的硬判决结果进行校验；而信息重组模块对前一次迭代的硬判结果进行缓存备份。若校验模块校验通过，则对前一次迭代的硬判决结果进行信息重组并输出，否则释放前一次迭代硬判决结果的缓存。根据译码器并行度P，硬比特信息存储模块的存储位宽为P，深度能够乒乓存储两个最大硬比特CB块。
校验模块208被构造成：对一次迭代译码后硬判决结果进行校验，判断是否满足终止迭代译码的条件，若满足则输出译码终止信号，否则不输出，继续下一次迭代。译码迭代终止条件包括但不限于如下：1)H矩阵奇偶校验通过；2)CRC校验通过；3)H矩阵奇偶校验和CRC校验同时通过；4)满足最小迭代次数且达到最大迭代次数，等等。图8为本公开实施例的译码校验流程图。
信息重组模块30被构造成：根据预设译码器并行度P，待译码CB块的扩展因子Z，计算得到可采用的译码分时数T。在一个可选实施例中，分时数T也可以在译码器外部计算好后通过参数配置得到。图9为信息重组可采用的一种可选的实施方式，如图9所示，重组模块获得参数T后，在硬比特“子块”信息存储空间中索引读取属于同一“块”H k的所有“子块”信息
Figure PCTCN2019117991-appb-000049
所有T个“子块”信息重组后得到硬比特“块”信息H k，依次完成所有前K-L个代表信息列的硬比特“块”信息的重组和拼接，并以CB块的形式输出最终译码后结果。
本公开实施例还提供了一种译码器100，包括存储器110和处理器120，所述存储器110中存储有计算机程序，所述处理器120被设置为运行所述计算机程序以执行上述实施例的方法步骤。
本公开实施例还提供了一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述实施例的方法步骤。
在本公开提供的上述各实施例中，可以支持码器并行度灵活设置，用户可以结合流量、时延等需求与资源消耗、芯片面积等成本花费，选择最佳并行度来进行译码器设计，在满足译码器性能需求的前提下使成本花费降到最低。
另外，本公开提供的上述各实施例中，可以在不同并行度下支持译码器在线兼容多种扩展因子，在线兼容多种矩阵，在线兼容多种码率，译码器结构、资源消耗与矩阵大小无关，提高了译码器的灵活性与兼容性；
本公开提供的上述各实施例中，在译码过程中，可采用单个“块”并行处理，“块”与“块”之间串行流水的处理方式，所有“块”信息可以共享存储，无需为每个“块”信息独立分配存储，降低了存储资源的消耗；
显然，本领域的技术人员应该明白，上述的本公开的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种译码方法，包括：
    设置译码器的并行度P，并根据所述并行度P对待译码块的软信息进行信息拆分；
    根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息；以及
    根据所述并行度P将所述硬比特信息进行信息重组。
  2. 根据权利要求1所述的方法，其中，根据所述并行度P对所述待译码块的软信息进行信息拆分的步骤，包括：
    根据所述并行度P以及待译码块所配置的扩展因子Z将所述待译码块中所有大小为Z的块信息分别拆分为T个子块信息，其中，T为正整数。
  3. 根据权利要求2所述的方法，其中，根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息的步骤，包括：
    对所述待译码块进行分层译码计算，其中每层译码计算分T次分时计算完成，在每次分时计算过程中对子块信息进行并行处理，子块与子块之间串行流水处理，对译码后的子块信息进行硬判决并输出硬比特子块信息。
  4. 根据权利要求3所述的方法，其中，根据所述并行度P将所述硬比特信息进行信息重组的步骤，包括：
    根据所述并行度P以及所述扩展因子Z，将译码后输出的硬比特子块信息重组为对应的硬比特块信息，并将硬比特块信息重组为硬比特译码块输出。
  5. 根据权利要求2所述的方法，其中，所述并行度P小于或等于译码器所支持的扩展因子集中的最大扩展因子。
  6. 根据权利要求2所述的方法，其中，根据译码器的并行度P以及待译码块所配置的扩展因子Z将所述待译码块中所有大小为Z的块信息分别拆分为T个子块信息的步骤，包括：
    根据译码器的并行度P以及待译码块所配置的扩展因子Z确定译码分时数T，其中T为可以整除Z且不小于Z/P的最小正整数；以及
    将所述待译码块中所有大小为Z的块信息分别拆分为T个子块信息。
  7. 根据权利要求2所述的方法，其中，根据译码器的并行度P以及待译码块所配置的扩展因子Z将所述待译码块中所有大小为Z的块信息分别拆分为T个子块信息的步骤之后，所述方法包括：
    根据所述块信息在译码层对应的移位值S l,k计算其子块信息的索引i和子移位值
    Figure PCTCN2019117991-appb-100001
    其中：
    i＝Mod(S l,k+t,T)，
    Figure PCTCN2019117991-appb-100002
    其中，t为分时索引
    Figure PCTCN2019117991-appb-100003
    k为块信息编号，l为译码层编号。
  8. 根据权利要求3所述的方法，其中，对所述待译码块进行分层译码计算，其中每层译码计算分T次分时计算完成，在每次分时计算过程中对子块信息进行并行处理，子块与子块之间串行流水处理的步骤，包括：
    根据子块信息的索引i进行先验信息寻址；
    根据子块信息的子移位值对寻址得到的先验信息进行循环移位；
    用于根据所述先验信息，进行变量节点信息、校验节点信息和后验信息的计算，并输出所述后验信息；
    根据所述子移位值对所述后验信息进行逆循环移位，得到循环移位后的后验信息；以及
    用移位后的后验信息更新先验信息，并用更新后的先验信息更新对应的子块信息。
  9. 根据权利要求8所述的方法，其中，根据如下公式计算变量节点信息
    Figure PCTCN2019117991-appb-100004
    Figure PCTCN2019117991-appb-100005
    其中，k∈N(l)，
    Figure PCTCN2019117991-appb-100006
    表示第l层、第t次分时译码的第k个变量节点信息，
    Figure PCTCN2019117991-appb-100007
    表示第l层、第t次分时译码的第k个旧校验节点信息，在首次迭代译码时
    Figure PCTCN2019117991-appb-100008
    被初始化为0。
  10. 根据权利要求8所述的方法，其中，根据如下公式计算校验节点信息
    Figure PCTCN2019117991-appb-100009
    Figure PCTCN2019117991-appb-100010
    其中，k∈N(l)，
    Figure PCTCN2019117991-appb-100011
    表示第l层、第t次分时译码的第k个新校验节点信息，N(l)\k表示集合N(l)中除去k后的所有变量节点索引k′的集合，并且
    所述方法还包括：用新计算得到的校验节点信息
    Figure PCTCN2019117991-appb-100012
    更新旧校验节点信息
    Figure PCTCN2019117991-appb-100013
  11. 根据权利要求8所述的方法，其中，根据如下公式计算后验信息new_B′ k,t：
    Figure PCTCN2019117991-appb-100014
    其中，
    Figure PCTCN2019117991-appb-100015
    表示第l层、第t次分时译码的第k个变量节点信息。
  12. 一种译码装置，包括：
    信息拆分模块，被构造成设置译码器的并行度P,并根据所述并行度P对待译码块的软信息进行信息拆分；
    译码模块，被构造成根据所述拆分信息对所述待译码块进行译码计算，并输出译码后的硬比特信息；以及
    信息重组模块，被构造成根据所述并行度P将所述硬比特信息进行信息重组。
  13. 根据权利要求12所述的译码装置，其中，
    所述信息拆分模块，还被构造成根据译码器的并行度P以及待译码块所配置的扩展因子Z将所述待译码块中所有大小为Z的块信息分别拆分为T个子块信息，其中T为正整数；
    所述译码模块，还被构造成对所述待译码块进行分层译码计算，其中每层译码计算分T次分时计算完成，在每次分时计算过程中对子块信息进行并行处理，子块与子块之间串行流水处理，对译码后的子块信息进行硬判决并输出硬比特子块信息；并且
    所述信息重组模块，还被构造成根据所述并行度P以及所述扩展因子Z，将译码后输出的硬比特子块信息重组为对应的硬比特块信息，并将硬比特块信息重组为硬比特译码块输出。
  14. 根据权利要求13所述的译码装置，其中，
    所述信息拆分模块，还被构造成根据译码器的并行度P以及待译码块所配置的扩展因子Z确定译码分时数T，其中T为可以整除Z且不小于Z/P的最小正整数。
  15. 根据权利要求13所述的装置，其中，所述并行度P小于或等 于译码器所支持的扩展因子集中的最大扩展因子。
  16. 一种译码器，包括存储器和处理器，所述存储器中存储有计算机程序，其中，所述处理器被设置为运行所述计算机程序以执行所述权利要求1至11任一项中所述的方法。
  17. 一种存储介质，所述存储介质中存储有计算机程序，其中，所述计算机程序在被处理器运行时执行所述权利要求1至11任一项中所述的方法。
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