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WO2020042221A1 - 一种高浪涌电流能力碳化硅二极管及其制作方法 - Google Patents

一种高浪涌电流能力碳化硅二极管及其制作方法 Download PDF

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Publication number
WO2020042221A1
WO2020042221A1 PCT/CN2018/105133 CN2018105133W WO2020042221A1 WO 2020042221 A1 WO2020042221 A1 WO 2020042221A1 CN 2018105133 W CN2018105133 W CN 2018105133W WO 2020042221 A1 WO2020042221 A1 WO 2020042221A1
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type
silicon carbide
epitaxial layer
region
type well
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PCT/CN2018/105133
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English (en)
French (fr)
Inventor
朱袁正
杨卓
周锦程
叶鹏
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无锡新洁能股份有限公司
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Priority claimed from CN201810991533.9A external-priority patent/CN108899372A/zh
Priority claimed from CN201810991544.7A external-priority patent/CN109192789B/zh
Application filed by 无锡新洁能股份有限公司 filed Critical 无锡新洁能股份有限公司
Priority to US16/623,961 priority Critical patent/US11374094B2/en
Publication of WO2020042221A1 publication Critical patent/WO2020042221A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • the invention relates to a diode and a manufacturing method, in particular to a silicon carbide diode with high surge current capability and a manufacturing method thereof, and belongs to the technical field of manufacturing semiconductor devices.
  • Power devices and their modules provide an effective way to achieve conversion between various forms of electrical energy, and have been widely used in the fields of national defense construction, transportation, industrial production, medical and health. Since the application of the first power devices in the 1950s, the introduction of each generation of power devices has enabled more efficient conversion and use of energy.
  • silicon carbide (SiC) materials have become a hot research topic in power semiconductor devices.
  • silicon carbide (SiC) has the advantages of large band gap width, high breakdown field strength, and high thermal conductivity.
  • Forbidden Band Brown Silicon Carbide's intrinsic carrier concentration is low, which reduces the reverse current of the device; high breakdown field strength can greatly increase the reverse breakdown voltage of power devices, and can reduce the device on-time
  • High thermal conductivity can greatly increase the maximum operating temperature of the device; and in many high-power applications, such as: high-speed railways, hybrid vehicles, intelligent high-voltage DC power transmission and other fields, silicon carbide-based devices have been given very High expectations.
  • silicon carbide power devices can effectively reduce power loss, so they are known as "green energy” devices that drive the "new energy revolution.”
  • silicon carbide power devices include diodes and MOSFETs.
  • breakdown voltage, forward voltage drop, and junction capacitance charge are its main electrical parameters, and inrush current capability is its most important reliability parameter.
  • silicon carbide diodes often use junction barrier Schottky diodes (JBS), as shown in Figure 1 is a typical silicon carbide JBS structure. Under normal operating conditions of the device (small current), there is only a Schottky contact area. It is turned on, and the P-type well region does not participate in conduction, so the larger the area of the P-type well region, the larger the on-state voltage drop of the device under the same area condition, and the larger the conduction loss.
  • JBS junction barrier Schottky diodes
  • the PN junction Under the condition of high current (surge current comes), the PN junction is turned on, and the minority holes are injected into the drift region of the device, thereby improving the surge current capability of the device. Therefore, the larger the area of the P-type well region, the higher the surge of the device. The stronger the current capability.
  • the PN junction diode of silicon carbide Due to the high turn-on voltage of the PN junction diode of silicon carbide, it is difficult to effectively turn on the PN junction effectively when the surge current comes. Even if the PN junction is turned on, the forward voltage drop of the device is often too high, causing the chip temperature to rise. Faster and more prone to failure, resulting in poorer silicon carbide power surge current capability.
  • the purpose of the present invention is to overcome the shortcomings in the prior art, and propose a silicon carbide diode with high surge current capability and a method for manufacturing the same.
  • a silicon carbide diode with high surge current capability By adding an N-type high-resistance region below or below the P-type well region, Several discrete trenches are provided in the P-well interval, which makes the device greatly increase the surge current capability of the device under normal conduction working conditions.
  • the technical solution of the present invention is: a silicon carbide diode with a high surge current capability, which includes a semiconductor substrate, the semiconductor substrate includes an N-type silicon carbide substrate and N on the N-type silicon carbide substrate
  • a type of silicon carbide epitaxial layer is provided with a plurality of P-type well regions in the upper part of the N-type silicon carbide epitaxial layer, and is characterized in that an N-type high-resistance region is provided below or below the P-type well region, The resistivity of the N-type high-resistance region is greater than the resistivity of the N-type silicon carbide epitaxial layer.
  • a plurality of uniformly spaced block-shaped P-type regions are provided in the N-type high-resistance region, and the block-shaped P-type region extends from the junction of the N-type high-resistance region and the P-type well region to the N-type high-resistance region Or extend through the N-type high-resistance region into the N-type silicon carbide epitaxial layer.
  • the width of the block-shaped P-type region is not greater than the thickness of the N-type high-resistance region.
  • an N-type well region is provided in an adjacent P-type well interval, and the resistivity of the N-type well region is equal to or lower than that of the N-type silicon carbide epitaxial layer.
  • the technical solution of the present invention further includes: a silicon carbide diode with high surge current capability, including a semiconductor substrate, the semiconductor substrate including an N-type silicon carbide substrate and located on the N-type silicon carbide substrate N-type silicon carbide epitaxial layer is provided with a plurality of P-type well regions in the upper part of the N-type silicon carbide epitaxial layer, and is characterized in that an N-type high resistance is provided below or on the lower surface of the P-type well region.
  • the resistivity of the N-type high-resistance region is greater than the resistivity of the N-type silicon carbide epitaxial layer, a plurality of trenches are provided in the P-type well region, and the trenches located at the edge of the P-type well region and the N-type silicon carbide
  • the epitaxial layer is adjacent, and the trench extends from the upper surface of the semiconductor substrate through the P-type well region to the N-type high-resistance region or sequentially through the P-type well region, and the N-type high-resistance region extends into the N-type silicon carbide epitaxial layer.
  • the trench is filled with an insulating dielectric layer.
  • an anode metal is provided on an upper surface of the semiconductor substrate, the anode metal is in contact with the N-type epitaxial layer Schottky, and is in ohmic contact with a P-type well region; and a lower surface of the semiconductor substrate is provided Cathode metal, which is in ohmic contact with an N-type silicon carbide substrate.
  • the trench is provided with conductive polysilicon and an insulating dielectric layer surrounding the conductive polysilicon, and the conductive polysilicon is electrically connected to the anode metal.
  • an N-type well region is provided in an adjacent P-type well interval, the N-type well region is adjacent to the trench, and the resistivity of the N-type well region is smaller than that of the N-type high-resistance region.
  • the resistivity of the N-type well region is equal to or smaller than that of the N-type silicon carbide epitaxial layer.
  • the present invention also proposes a method for manufacturing a silicon carbide diode with high inrush current capability, which is characterized by including the following steps:
  • Step 1 Select an N-type silicon carbide substrate and use an epitaxial process to grow an N-type silicon carbide epitaxial layer on the upper surface of the N-type silicon carbide substrate;
  • Step 2 Under the cover of the first photoresist, selectively implant high-energy P-type impurities, and then selectively implant low-energy P-type impurities, and then perform high temperature annealing to form N-type high-resistance regions and P-type well regions, respectively. ;
  • the third step under the cover of the second photoresist, etching the N-type silicon carbide epitaxial layer to obtain a plurality of trenches located in the P-type well region;
  • the fourth step an insulating oxide layer is grown on the surface of the N-type silicon carbide epitaxial layer and in the trench, and the insulating oxide layer fills the trench;
  • the fifth step etching the insulating oxide layer, removing the insulating oxide layer on the surface of the N-type silicon carbide epitaxial layer, and forming an insulating dielectric layer in the trench;
  • the sixth step thinning the lower surface of the N-type silicon carbide substrate, and then depositing a metal layer to form a cathode metal, and depositing a metal on the upper surface of the N-type silicon carbide epitaxial layer to form an anode metal. Finally, a silicon carbide power diode is prepared. Device.
  • the insulating oxide layer in the fourth step does not fill the trench, and polysilicon is deposited on the insulating oxide layer so that the polysilicon fills the trench, and then the polysilicon and the insulating oxide layer on the surface of the device are sequentially removed.
  • Conductive polysilicon and an insulating dielectric layer encapsulating the conductive polysilicon are obtained inside, and the conductive polysilicon is electrically connected to the anode metal.
  • the present invention also proposes a method for manufacturing a silicon carbide diode with high inrush current capability, which is characterized by including the following steps:
  • Step 1 Select an N-type silicon carbide substrate and use an epitaxial process to grow an N-type silicon carbide epitaxial layer on the upper surface of the N-type silicon carbide substrate;
  • Step 2 Under the cover of the first photoresist, selectively implant high-energy P-type impurities, and then selectively implant low-energy P-type impurities, and then perform high temperature annealing to form N-type high-resistance regions and P-type well regions, respectively. ;
  • the third step thinning the lower surface of the N-type silicon carbide substrate, and then depositing a metal layer to form a cathode metal, and depositing a metal on the upper surface of the N-type silicon carbide epitaxial layer to form an anode metal. Finally, a silicon carbide power diode is prepared. Device.
  • a second photoresist is used to selectively implant P-type impurities and then perform high-temperature annealing to form a plurality of spaced-apart block P-type regions in the N-type high-resistance region.
  • the width of the block-shaped P-type region is not greater than the thickness of the N-type high-resistance region.
  • the N-type high-resistance region in the step 2 can also be obtained by an epitaxial process, specifically:
  • N-type high-resistance layer is grown on the upper surface of the N-type silicon carbide epitaxial layer
  • a low-energy P-type impurity is selectively implanted on the surface of the N-type high-resistance layer to remove the first photoresist;
  • an N-type impurity is selectively implanted on the surface of the N-type high-resistance layer to remove the third photoresist;
  • high temperature annealing is performed to form a P-type well region, an N-type well region located in the P-type well interval, and an N-type high-resistance region located below the P-type well region, respectively.
  • the resistivity of the N-type well region and the N-type silicon carbide epitaxial layer are both smaller than the resistivity of the N-type high-resistance region, and the resistivity of the N-type well region is equal to the resistivity of the N-type silicon carbide epitaxial layer or Resistivity smaller than N-type silicon carbide epitaxial layer.
  • the present invention Compared with the traditional silicon carbide diode device, the present invention has the following advantages:
  • an N-type high-resistance region is added below or below the P-type well region.
  • an electronic current flows from the anode Schottky junction into the device and flows through N.
  • Type high-resistance region and then diffuses out to the cathode at an angle of about 45 degrees.
  • the N-type high-resistance region below the P-type well region basically does not affect the flow of electron current, so the structure does not affect the forward voltage drop of the device;
  • Figure 26 under high current conditions, a considerable part of the electronic current will flow through the N-type high-resistance region below the P-type well region.
  • the present invention provides a plurality of discretely spaced trenches in the P-type well region.
  • the arrangement of the trenches can prolong the path of electronic current flow and increase the P-type well.
  • a plurality of discrete block-shaped P-type regions are provided in the N-type high-resistance region.
  • the arrangement of the block-shaped P-type region can prolong the flow of electronic current. Path, increasing the lateral resistance under the P-well region, thereby ensuring that the PN junction in the device opens more effectively under high current conditions, increasing the device's inrush current capability;
  • the present invention provides an N-type well region in the P-type well interval.
  • the resistivity of the N-type well region is smaller than that of the N-type epitaxial layer, and when the device is turned on, the on-resistance of the device can be significantly reduced.
  • FIG. 1 is a schematic structural diagram of a conventional silicon carbide Schottky diode.
  • FIG. 2 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 2 of the present invention.
  • FIG. 4 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 3 of the present invention.
  • FIG. 5 is a structural cross-sectional view of a silicon carbide Schottky diode according to Embodiment 4 of the present invention.
  • FIG. 6 is a schematic structural diagram of a silicon carbide Schottky diode with four block P-type regions according to Embodiment 5 of the present invention.
  • FIG. 7 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 6 of the present invention.
  • FIG. 8 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 7 of the present invention.
  • FIG. 9 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 8 of the present invention.
  • FIG. 10 is a structural cross-sectional view of a silicon carbide Schottky diode with four trenches according to Embodiment 9 of the present invention.
  • FIG. 11 is a schematic structural diagram of a silicon carbide Schottky diode according to Embodiment 10 of the present invention.
  • FIG. 12 is a schematic cross-sectional structure diagram of forming an N-type silicon carbide substrate and an N-type silicon carbide epitaxial layer in Embodiments 2 and 7 of the present invention.
  • FIG. 13 is a schematic cross-sectional structure diagram of forming a P-type well region and an N-type high-resistance region in Embodiments 2 and 7 of the present invention.
  • FIG. 14 is a schematic cross-sectional structure view of forming a block-shaped P-type region in Embodiment 2 of the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram of forming an N-type substrate, an N-type epitaxial layer, and an N-type high-resistance region in Embodiments 4 and 9 of the present invention.
  • FIG. 16 is a schematic cross-sectional structure view of forming a P-type well region in Embodiments 4 and 9 of the present invention.
  • FIG. 17 is a schematic cross-sectional structure diagram of forming an N-type well region in Embodiments 4 and 9 of the present invention.
  • FIG. 18 is a schematic cross-sectional structure view of forming a block-shaped P-type region in Embodiment 4 of the present invention.
  • FIG. 19 is a schematic cross-sectional structure view of an etched trench according to Embodiment 7 of the present invention.
  • FIG. 20 is a schematic cross-sectional view of a deposited insulating oxide layer and polysilicon according to Embodiment 7 of the present invention.
  • FIG. 21 is a schematic cross-sectional structure view of forming a conductive polysilicon and an insulating dielectric layer in Embodiment 7 of the present invention.
  • FIG. 22 is a schematic cross-sectional structure view of an etched trench according to Embodiment 9 of the present invention.
  • FIG. 23 is a schematic cross-sectional view of a deposited insulating oxide layer and polysilicon according to Embodiment 9 of the present invention.
  • FIG. 24 is a schematic cross-sectional structure view of forming a conductive polysilicon and an insulating dielectric layer in Embodiment 9 of the present invention.
  • FIG. 25 is an electronic current path diagram of the present invention under a small current condition.
  • FIG. 26 is a schematic diagram of a parasitic resistance in the N high-resistance region under a high current condition according to the present invention.
  • SYMBOLS 1. Cathode metal; 2. N-type silicon carbide substrate; 3. N-type silicon carbide epitaxial layer; 4. N-type high resistance region; 5. Trench; 6. P-type well region; 7. N-type well region; 8, anode metal; 9, N-type high-resistance layer; 10, insulating dielectric layer; 11, conductive polysilicon; 12, bulk P-type region.
  • Embodiment 1 As shown in FIG. 2, a silicon carbide diode with a high inrush current capability is provided. A cathode metal 1, an N-type silicon carbide substrate 2, and an N-type carbonization are sequentially arranged from the bottom to the top in the cross-sectional direction of the device. A silicon epitaxial layer 3 and an anode metal 8 are provided with a plurality of P-type well regions 6 in the N-type silicon carbide epitaxial layer 3, the anode metal 8 is in contact with the N-type epitaxial layer 3 Schottky, and is in contact with a P-type 6 ohm contact in the well area;
  • N-type high-resistance region 4 is provided below or on the lower surface of the P-type well region 6.
  • the width of the N-type high-resistance region 4 is the same as the width of the P-type well region 6.
  • the rate is higher than the N-type silicon carbide epitaxial layer 3;
  • Embodiment 2 As shown in FIG. 3, a silicon carbide diode with high inrush current capability is provided. Cathode metal 1, N-type silicon carbide substrate 2, and N-type carbonization are sequentially arranged from bottom to top in the cross-sectional direction of the device. A silicon epitaxial layer 3 and an anode metal 8 are provided with a plurality of P-type well regions 6 in the N-type silicon carbide epitaxial layer 3, the anode metal 8 is in contact with the N-type epitaxial layer 3 Schottky, and is in contact with a P-type 6 ohm contact in the well area;
  • An N-type high-resistance region 4 is provided below or on the lower surface of the P-type well region 6, and the resistivity of the N-type high-resistance region 4 is higher than that of the N-type silicon carbide epitaxial layer 3;
  • a block P-type region 12 is provided on both sides of the region 4, the block P-type region 12 is adjacent to the N-type silicon carbide epitaxial layer 3, and the bottom of the block P-type region 12 passes through the N-type high resistance region 4 extends into the N-type epitaxial layer 3, and the width of the bulk P-type region 12 is less than or equal to the thickness of the N-type high-resistance region 4.
  • Embodiment 3 As shown in FIG. 4, a silicon carbide diode with high surge current capability is provided. Cathode metal 1, N-type silicon carbide substrate 2, and N-type carbonization are sequentially arranged from bottom to top in the cross-sectional direction of the device. A silicon epitaxial layer 3 and an anode metal 8 are provided with a plurality of P-type well regions 6 in the N-type silicon carbide epitaxial layer 3, the anode metal 8 is in contact with the N-type epitaxial layer 3 Schottky, and is in contact with a P-type 6 ohm contact in the well area;
  • N-type high-resistance region 4 is provided below or on the lower surface of the P-type well region 6.
  • the width of the N-type high-resistance region 4 is the same as the width of the P-type well region 6.
  • the rate is higher than the N-type silicon carbide epitaxial layer 3;
  • An N-type well region 7 is provided between the adjacent P-type well regions 6, the N-type well region 7 is adjacent to the P-type well region 6, and the resistivity of the N-type well region 7 is smaller than the N-type silicon carbide epitaxy Layer 3 resistivity.
  • Embodiment 4 As shown in FIG. 5, this embodiment is different from Embodiment 1 in that an N-type well region 7 is provided between adjacent P-type well regions 6, and the N-type well regions 7 and P The type well region 6 is adjacent, and the resistivity of the N type well region 7 is smaller than that of the N type silicon carbide epitaxial layer 3;
  • Block-type P-type regions 12 are provided on both sides of the N-type high-resistance region 4, the block-type P-type regions 12 are adjacent to the N-type silicon carbide epitaxial layer 3, and the bottom of the block-type P-type regions 12 passes through The N-type high-resistance region 4 extends into the N-type epitaxial layer 3, and the width of the bulk P-type region 12 is less than or equal to the thickness of the N-type high-resistance region 4.
  • Embodiment 5 As shown in FIG. 6, a device cell is taken as an example. This embodiment is different from Embodiment 4 in that block P-type regions 12 are not only provided on both sides of the N-type high-resistance region 4, but also in the N-type. There are also two massive P-type regions 12 evenly arranged in the high-resistance region 4, and the bottom of the massive P-type region 12 penetrates the P-type well region 6, and the N-type high-resistance region 4 extends into the N-type silicon carbide epitaxial layer 3. ;
  • Example 5 shows that the present invention can further extend the current path of the electronic current by increasing the number of block-shaped P-type regions 12 in the cell of the device, and increase the lateral resistance under the P-type well region 6, thereby ensuring a large
  • the PN junction inside the device opens more effectively under current conditions, increasing the surge current capability of the device.
  • the number of block-shaped P-type regions 12 can be determined according to the actual device design current.
  • Embodiment 6 As shown in FIG. 7, a silicon carbide diode with high inrush current capability is provided. Cathode metal 1, N-type silicon carbide substrate 2, and N-type carbonization are sequentially arranged from bottom to top in the cross-sectional direction of the device. A silicon epitaxial layer 3 and an anode metal 8 are provided with a plurality of P-type well regions 6 in the N-type silicon carbide epitaxial layer 3, the anode metal 8 is in contact with the N-type epitaxial layer 3 Schottky, and is in contact with a P-type 6 ohm contact in the well area;
  • An N-type high-resistance region 4 is provided below or on the lower surface of the P-type well region 6.
  • the width of the N-type high-resistance region 4 is the same as the width of the P-type well region 6.
  • the rate is higher than that of the N-type silicon carbide epitaxial layer 3; trenches 5 are respectively provided on both sides of the P-type well region 6, the trench 5 is adjacent to the N-type silicon carbide epitaxial layer 3, and the trench 5 is filled with an insulating medium Layer 10, the bottom of the trench 5 extends through the N-type high-resistance region 4 into the N-type epitaxial layer 3.
  • Embodiment 7 As shown in FIG. 8, a silicon carbide diode with high inrush current capability is provided. Cathode metal 1, N-type silicon carbide substrate 2, and N-type carbonization are sequentially arranged from bottom to top in the cross-sectional direction of the device. A silicon epitaxial layer 3 and an anode metal 8 are provided with a plurality of P-type well regions 6 in the N-type silicon carbide epitaxial layer 3, the anode metal 8 is in contact with the N-type epitaxial layer 3 Schottky, and is in contact with a P-type 6 ohm contact in the well area;
  • An N-type high-resistance region 4 is provided below or on the lower surface of the P-type well region 6.
  • the width of the N-type high-resistance region 4 is the same as the width of the P-type well region 6.
  • the rate is higher than that of the N-type silicon carbide epitaxial layer 3; trenches 5 are provided on both sides of the P-type well region 6, the trench 5 is adjacent to the N-type silicon carbide epitaxial layer 3, and the bottom of the trench 5 penetrates Extending through the N-type high-resistance region 4 into the N-type epitaxial layer 3; the sidewall 5 and the bottom of the trench 5 are provided with an insulating dielectric layer 10, the insulating dielectric layer 10 is wrapped with conductive polysilicon 11, and the conductive The polysilicon 11 is electrically connected to the anode metal 8.
  • Embodiment 8 As shown in FIG. 9, a silicon carbide diode with high inrush current capability is provided. A cathode metal 1, an N-type silicon carbide substrate 2, and an N-type carbonization are sequentially arranged from the bottom to the top in the cross-sectional direction of the device. A silicon epitaxial layer 3 and an anode metal 8 are provided with a plurality of P-type well regions 6 in the N-type silicon carbide epitaxial layer 3, the anode metal 8 is in contact with the N-type epitaxial layer 3 Schottky, and is in contact with a P-type 6 ohm contact in the well area;
  • N-type high-resistance region 4 is provided below or on the lower surface of the P-type well region 6.
  • the width of the N-type high-resistance region 4 is the same as the width of the P-type well region 6.
  • the rate is higher than that of the N-type silicon carbide epitaxial layer 3; trenches 5 are provided on both sides of the P-type well region 6, the trench 5 is filled with an insulating dielectric layer 10, and the bottom of the trench 5 passes through
  • the N-type high-resistance region 4 extends into the N-type epitaxial layer 3;
  • N-type well region 7 is provided between the adjacent P-type well regions 6.
  • the N-type well region 7 is adjacent to the trench 5, and the resistivity of the N-type well region 7 is smaller than that of the N-type silicon carbide epitaxial layer 3. Resistivity.
  • Embodiment 9 As shown in FIG. 10, this embodiment is different from Embodiment 1 in that the sidewall 5 and the bottom of the trench 5 are provided with an insulating dielectric layer 10, and the insulating dielectric layer 10 is wrapped with conductive polysilicon 11.
  • the conductive polysilicon 11 is electrically connected to the anode metal 8; an N-type well region 7 is provided between the adjacent P-type well regions 6, the N-type well region 7 is adjacent to the trench 5, and the N-type well region is The resistivity of 7 is smaller than that of the N-type silicon carbide epitaxial layer 3.
  • Embodiment 10 As shown in FIG. 11, taking a device cell as an example, this embodiment is different from Embodiment 4 in that trenches 5 are not only provided on both sides of the P-type well region 6, but also in the P-type well region 6. Two trenches 5 are also arranged uniformly, and the bottom of the trench 5 passes through the P-type well region 6 and the N-type high-resistance region 4 in order to extend into the N-type silicon carbide epitaxial layer 3;
  • Example 10 illustrates that the present invention can further extend the current path of the electronic current by increasing the density of the trenches 5 in the cell of the device, and increasing the lateral resistance under the P-type well region 6, thereby ensuring the device under high current conditions.
  • the internal PN junction opens more effectively and increases the surge current capability of the device.
  • the number of trenches 5 can be determined according to the actual device design current.
  • the manufacturing method of the high inrush current capacity silicon carbide diode in Embodiment 2 of the present invention is as follows:
  • the first step selecting an N-type silicon carbide substrate 2 and using an epitaxial process to grow an N-type silicon carbide epitaxial layer 3 on the upper surface of the N-type silicon carbide substrate 2;
  • the second step under the cover of the first photoresist, selectively implant high-energy p-type impurities to form an N-type high-resistance region 4, and then selectively implant low-energy P-type impurities with After forming the P-type well region 6, and then removing the first photoresist, the dose of the first implantation of the P-type impurity (formation of the N-type high-resistance region 4) is smaller than that of the second implantation of the P-type impurity (formation of the P-type well region 6). ) Dose, and the order of the two injections can be replaced;
  • a high-energy P-type impurity is selectively implanted to form a bulk P-type region 12, and then annealed at a high temperature to form a P-type well region. 6.
  • the N-type high-resistance region 4 located below the P-type well region 6 and the block-shaped P-type region 12 located on both sides of the N-type high-resistance region 4;
  • the N-type high-resistance region 4 in Embodiment 2 of the present invention can also be obtained by an epitaxial process, which is specifically:
  • an N-type high-resistance layer 9 is grown on the upper surface of the N-type silicon carbide epitaxial layer 3;
  • a P-type impurity is selectively implanted with low energy on the surface of the N-type high-resistance layer 9 to form a P-type well region 6 to remove the first photoresist;
  • an N-type impurity is implanted on the surface of the N-type high-resistance layer 9 to remove the third photoresist;
  • High temperature annealing is then performed to form a P-type well region 6 and an N-type high-resistance region 4 located below the P-type well region 6.
  • an N-type high-resistance layer between adjacent P-type well regions 6 is formed.
  • the resistivity of 9 is the same as the resistivity of the N-type silicon carbide epitaxial layer 3 (that is, the resistivity of the N-type well region 7 is equal to the resistivity of the N-type silicon carbide epitaxial layer 3);
  • the resistivity of the N-type high-resistance layer 9 is the same as that of the N-type high-resistance region 4, and the resistivity of the N-type high-resistance region 4 is greater than that of the N-type silicon carbide epitaxial layer 3;
  • the bottom of the bulk P-type region 12 extends through the N-type high-resistance region 4 into the N-type silicon carbide epitaxial layer 3, and the width of the bulk P-type region 12 is smaller than the thickness of the N-type high-resistance region 4;
  • the fourth step thinning the back of the device, and depositing a metal layer on the lower surface of the device to form a cathode metal 1, which is in ohmic contact with the N-type silicon carbide substrate 2 on the device.
  • a metal is deposited on the surface to form an anode metal 8, which is in contact with the Schottky N-type silicon carbide epitaxial layer 3 and 6 ohms in the P-type well region, and finally a silicon carbide power diode device is obtained.
  • the manufacturing method of the high inrush current capability silicon carbide diode in Embodiment 4 of the present invention is as follows:
  • the first step is to select an N-type silicon carbide substrate 2 and use an epitaxial process to grow an N-type silicon carbide epitaxial layer 3 on the upper surface of the N-type silicon carbide substrate 2 and to form an N-type silicon carbide epitaxial layer.
  • N-type high-resistance layer 9 grown on the upper surface of 3;
  • the second step is to selectively implant P-type impurities on the surface of the N-type high-resistance layer 9 under the cover of the first photoresist.
  • This step is to form a P-type well region 6 and remove the first Photoresist
  • the third step is to implant N-type impurities on the surface of the N-type high-resistance layer 9 under the shielding of the third photoresist.
  • This step is to form the N-type well region 7 and remove the third photolithography. gum;
  • the resistivity of the N-type high-resistance region 4 is the same as that of the N-type high-resistance layer 9.
  • the resistivity of the N-type well region 7 is smaller than that of the N-type silicon carbide epitaxial layer 3.
  • the N-type silicon carbide epitaxy The resistivity of the layer 3 is smaller than that of the N-type high-resistance region 4;
  • the fourth step is to selectively implant P-type impurities under the mask of the second photoresist.
  • This step is to form a bulk P-type region 12, and then perform high temperature annealing to form a P-type well region. 6.
  • An N-type high-resistance region 4 located on the lower surface of the P-type well region 6, an N-type well region 7 located between the P-type well regions 6, and a block-shaped P-type region 12 located on both sides of the N-type high-resistance region 4;
  • the resistivity of the N-type high-resistance layer 9 is the same as that of the N-type high-resistance region 4.
  • the resistivity of the N-type high-resistance region 4 is greater than the resistance of the N-type silicon carbide epitaxial layer 3 and the N-type well region 7.
  • the resistivity of the N-type well region 7 is smaller than that of the N-type silicon carbide epitaxial layer 3;
  • the bottom of the bulk P-type region 12 extends through the N-type high-resistance region 4 into the N-type silicon carbide epitaxial layer 3, and the width of the bulk P-type region 12 is smaller than the thickness of the N-type high-resistance region 4;
  • the fifth step thinning the back of the device, and depositing a metal layer on the lower surface of the device to form a cathode metal 1, the cathode metal 1 is in ohmic contact with the N-type silicon carbide substrate 2 on the device A metal is deposited on the surface to form an anode metal 8, the anode metal 8 is in contact with the Schottky in the N-type well region 7 and 6 ohm in contact with the P-type well region, and finally a silicon carbide power diode device is obtained.
  • the manufacturing method of the silicon carbide diode with high surge current capability in Embodiment 7 of the present invention is as follows:
  • the first step selecting an N-type silicon carbide substrate 2 and using an epitaxial process to grow an N-type silicon carbide epitaxial layer 3 on the upper surface of the N-type silicon carbide substrate 2;
  • the second step under the cover of the first photoresist, selectively implant P-type impurities with high energy for forming the N-type high-resistance region 4, and then selectively implant P-type impurities with low energy.
  • the P-type well region 6 and the N-type high-resistance region 4 on the lower surface of the P-type well region 6 are formed, and then the first photoresist is removed;
  • the dose of the type impurity is smaller than the dose of the second injection of the P-type impurity, and the order of the two injections can be replaced;
  • the N-type high-resistance region 4 in Embodiment 7 of the present invention can also be obtained by an epitaxial process, which is specifically:
  • an N-type high-resistance layer 9 is grown on the upper surface of the N-type silicon carbide epitaxial layer 3;
  • a P-type impurity is selectively implanted with low energy on the surface of the N-type high-resistance layer 9 to remove the first photoresist;
  • an N-type impurity is implanted on the surface of the N-type high-resistance layer 9 to remove the third photoresist;
  • High temperature annealing is then performed to form a P-type well region 6 and an N-type high-resistance region 4 located below the P-type well region 6.
  • an N-type high-resistance layer between adjacent P-type well regions 6 is formed.
  • the resistivity of 9 is the same as the resistivity of the N-type silicon carbide epitaxial layer 3 (that is, the resistivity of the N-type well region 7 is equal to the resistivity of the N-type silicon carbide epitaxial layer 3);
  • the resistivity of the N-type high-resistance layer 9 is the same as that of the N-type high-resistance region 4, and the resistivity of the N-type high-resistance region 4 is greater than that of the N-type silicon carbide epitaxial layer 3;
  • the third step is to etch the surface of the device under the masking of the second photoresist to obtain a trench 5, the trench 5 and the P-type well region 6, and the N-type high-resistance region 4 Adjacency
  • the bottom of the trench 5 extends through the N-type high-resistance region 4 into the N-type silicon carbide epitaxial layer 3;
  • the fourth step depositing an insulating oxide layer on the surface of the device and the trench 5, depositing polysilicon on the insulating oxide layer, and filling the trench 5 with polysilicon;
  • the fifth step etching the polysilicon, the insulating oxide layer in order, removing the insulating oxide layer and the polysilicon on the surface of the device, and forming a conductive polysilicon 11 and an insulating dielectric layer 10 surrounding the conductive polysilicon 11 in the trench 5;
  • the sixth step thinning the back of the device, and depositing a metal layer on the lower surface of the device to form a cathode metal 1.
  • the cathode metal 1 is in ohmic contact with the N-type silicon carbide substrate 2 and is placed on the device.
  • a metal is deposited on the surface to form an anode metal 8, the anode metal 8 is in contact with the Schottky of the N-type silicon carbide epitaxial layer 3, is in 6-ohm contact with the P-type well region, and is electrically connected to the conductive polysilicon 11, and finally the silicon carbide power is obtained Diode device.
  • the manufacturing method of the silicon carbide diode with high surge current capability in Embodiment 9 of the present invention is as follows:
  • the first step is to select an N-type silicon carbide substrate 2 and use an epitaxial process to grow an N-type silicon carbide epitaxial layer 3 on the upper surface of the N-type silicon carbide substrate 2 and epitaxially form the N-type silicon carbide.
  • N-type high-resistance layer 9 is grown on the upper surface of layer 3;
  • the second step is to selectively implant P-type impurities on the surface of the N-type high-resistance layer 9 under the cover of the first photoresist.
  • This step is to form a P-type well region 6 and remove the first Photoresist
  • the third step is to implant N-type impurities on the surface of the N-type high-resistance layer 9 under the shielding of the third photoresist.
  • This step is to form the N-type well region 7 and remove the third photolithography. gum;
  • the resistivity of the N-type high-resistance region 4 is the same as that of the N-type high-resistance layer 9.
  • the resistivity of the N-type well region 7 is smaller than that of the N-type silicon carbide epitaxial layer 3.
  • the N-type silicon carbide epitaxy The resistivity of the layer 3 is smaller than that of the N-type high-resistance region 4;
  • the fourth step under the mask of the second photoresist, etching the upper surface of the device to obtain trenches 5, which are located on both sides of the P-type well region 6;
  • the bottom of the trench 5 extends through the N-type high-resistance region 4 into the N-type silicon carbide epitaxial layer 3;
  • the fifth step depositing an insulating oxide layer on the surface of the device and the trench 5, depositing polysilicon on the insulating oxide layer, and filling the trench 5 with polysilicon;
  • the sixth step etching the polysilicon, the insulating oxide layer in order, removing the insulating oxide layer and the polysilicon on the surface of the device, and forming a conductive polysilicon 11 and an insulating dielectric layer 10 surrounding the conductive polysilicon 11 in the trench 5;
  • the seventh step thin the back of the device, and deposit a metal layer on the lower surface of the device to form a cathode metal 1, which is in ohmic contact with the N-type silicon carbide substrate 2 on the device.
  • a metal is deposited on the surface to form an anode metal 8, the anode metal 8 is in contact with the Schottky in the N-type well region 7 and is in ohmic contact with the P-type well region 6 and is electrically connected to the conductive polysilicon 11 to finally obtain a silicon carbide power diode .
  • the P-type well region 6 can disperse the surface electric field of the device and improve the device's withstand voltage; at the moment when the device is turned on, the current will first pass through the Schottky contact position, while current flows through the N-type High-resistance region 4, which increases the pressure difference between the PN junction composed of P-type well region 6 and N-type high-resistance region 4.
  • the voltage difference reaches 3V, the PN junction opens and holes are injected into N-type silicon carbide epitaxial layer 3. At this time, the device is completely forward.

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Abstract

一种高浪涌电流能力碳化硅二极管及其制作方法，属于半导体器件制造技术领域，包括半导体基板，所述半导体基板包括N型碳化硅衬底（2）及位于N型碳化硅衬底（2）上的N型碳化硅外延层（3），在所述N型碳化硅外延层（3）内的上部设有若干个P型阱区（6），在所述P型阱区（6）下方或下表面设有N型高阻区（4），所述N型高阻区（4）的电阻率大于N型碳化硅外延层（3）的电阻率；通过在P型阱区（6）下设置N型高阻区（4），并在P型阱区（6）内设有多个沟槽（5）或N型高阻区（4）内设有若干个均匀间隔的块状P型区（12），使得器件在正常导通工作状态下，大幅增加了器件的浪涌电流能力。

Description

一种高浪涌电流能力碳化硅二极管及其制作方法 技术领域
本发明涉及一种二极管及制造方法，尤其是一种高浪涌电流能力碳化硅二极管及其制作方法，属于半导体器件的制造技术领域。
背景技术
功率器件及其模块为实现多种形式电能之间转换提供了有效的途径，在国防建设、交通运输、工业生产、医疗卫生等领域得到了广泛应用。自上世纪50年代第一款功率器件应用以来，每一代功率器件的推出，都使得能源更为高效地转换和使用。
传统功率器件及模块由硅基功率器件主导，主要以晶闸管、功率PIN器件、功率双极结型器件、功率MOSFET以及绝缘栅场效应晶体管等器件为主，在全功率范围内均得到了广泛的应用，以其悠久历史、十分成熟的设计技术和工艺技术占领了功率半导体器件的主导市场。然而，随着功率半导体技术发展的日渐成熟，硅基功率器件其特性已逐渐逼近其理论极限。研究人员在硅基功率器件狭窄的优化空间中努力寻求更佳参数的同时，也注意到了SiC、GaN等第三代宽带隙半导体材料在大功率、高频率、耐高温、抗辐射等领域中优异的材料特性。
碳化硅(SiC)材料凭借其优良的性能成为了国际上功率半导体器件的研究热点。碳化硅(SiC)相比传统的硅材料具有禁带宽度大、击穿场强高、热导率高等优势。禁带宽度大使碳化硅的本征载流子浓度低，从而减小了器件的反向电流；高的击穿场强可以大大提高功率器件的反向击穿电压，并且可以降低器件导通时的电阻；高热导率可以大大提高器件可以工作的最高工作温度；并且在众多高功率应用场合，比如：高速铁路、混合动力汽车、智能高压直流输电等领域，碳化硅基器件均被赋予了很高的期望。同时，碳化硅功率器件能够有效降低功率损耗，故此被誉为带动“新能源革命”的“绿色能源”器件。
目前，碳化硅功率器件注意包括二极管和MOSFET。对于碳化硅二极管，击穿电压、正向导通压降和结电容电荷是其最主要电学参数，浪涌电流能力是其最重要的可靠性参数。目前碳化硅二极管往往采用结势垒肖特基二极管(JBS)，如图1所示为典型的碳化硅JBS结构，在器件正常导通工作状态下(小电流)，仅仅有肖特基接触区域导通，P型阱区不参与导电，因此P型阱区面积越大，在相同面积条件下器件的导通压降越大，导通损耗越大。在大电流条件下(浪涌电流来临时)，PN结导通，向器件的漂移区注入少子空穴，从而提高器件的浪涌电流能力，因此P型阱区面积越大，器件的浪涌电流能力越强。然而，由于碳化硅的PN结二极管开启电压较高，浪涌电流来临时很难有效的保证PN结有效开启，即使PN结开启，也常常存在器件正向导通压降过高，导致芯片温度上升较快，极易失效，从而导致碳化硅功率浪涌电流能力较差。另一方 面，如果大幅增加JBS二极管P型阱区的面积，可以有效的提高器件的浪涌电流能力，但导致器件的正向导通损耗较大，在系统中应用时对电能的转换效率有不利的影响。
故而，亟需一种正向导通压降较小、浪涌电流大的碳化硅JBS器件，以克服现有技术所存在的不足。
发明内容
本发明的目的是克服现有技术中存在的不足，提出了一种高浪涌电流能力碳化硅二极管及其制作方法，通过在P型阱区下方或下表面增加了一个N型高阻区，并在P型阱区间设有若干个间隔分立的沟槽，使得器件在正常导通工作状态下，大幅增加了器件的浪涌电流能力。
为实现以上技术目的，本发明的技术方案是：一种高浪涌电流能力碳化硅二极管，包括半导体基板，所述半导体基板包括N型碳化硅衬底及位于N型碳化硅衬底上的N型碳化硅外延层，在所述N型碳化硅外延层内的上部设有若干个P型阱区，其特征在于，在所述P型阱区下方或下表面设有N型高阻区，所述N型高阻区的电阻率大于N型碳化硅外延层的电阻率。
进一步地，在N型高阻区内设有若干个均匀间隔的块状P型区，且块状P型区从N型高阻区与P型阱区交界处延伸到N型高阻区内或穿过N型高阻区延伸到N型碳化硅外延层内。
进一步地，所述块状P型区的宽度不大于N型高阻区的厚度。
进一步地，在相邻的P型阱区间设有N型阱区，所述N型阱区的电阻率等于N型碳化硅外延层的电阻率或小于N型碳化硅外延层的电阻率。
为了进一步实现以上技术目的，本发明的技术方案还包括：一种高浪涌电流能力碳化硅二极管，包括半导体基板，所述半导体基板包括N型碳化硅衬底及位于N型碳化硅衬底上的N型碳化硅外延层，在所述N型碳化硅外延层内的上部设有若干个P型阱区，其特征在于，在所述P型阱区下方或下表面设有N型高阻区，所述N型高阻区的电阻率大于N型碳化硅外延层的电阻率，在P型阱区内设有多个沟槽，位于P型阱区边缘的沟槽与N型碳化硅外延层邻接，且沟槽从半导体基板的上表面穿过P型阱区延伸到N型高阻区内或依次穿过P型阱区、N型高阻区延伸到N型碳化硅外延层内，所述沟槽内填充有绝缘介质层。
进一步地，在所述半导体基板的上表面设有阳极金属，所述阳极金属与所述N型外延层肖特基接触，与P型阱区欧姆接触；在所述半导体基板的下表面设有阴极金属，所述阴极金属与N型碳化硅衬底欧姆接触。
进一步地，所述沟槽内设有导电多晶硅及包裹导电多晶硅的绝缘介质层，所述导电多晶硅与阳极金属电连接。
进一步地，在相邻的P型阱区间设有N型阱区，所述N型阱区与沟槽邻接，所述N型阱区的电阻率小于N型高阻区的电阻率，所述N型阱区的电阻率等于N型碳化硅外延层的电阻率或小于N型碳化硅外延层的电阻率。
为了进一步实现以上技术目的，本发明还提出一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于，包括以下步骤：
第一步：选取N型碳化硅衬底，采用外延工艺，在N型碳化硅衬底的上表面生长N型碳化硅外延层；
第二步：在第一光刻胶的遮挡下，选择性高能量注入P型杂质，再选择性低能量注入P型杂质，然后进行高温退火，分别形成N型高阻区、P型阱区；
第三步；在第二光刻胶的遮挡下，对N型碳化硅外延层进行刻蚀，得到位于P型阱区内的多个沟槽；
第四步：在N型碳化硅外延层表面及沟槽内生长绝缘氧化层，所述绝缘氧化层填满沟槽；
第五步：对绝缘氧化层进行刻蚀，去除N型碳化硅外延层表面的绝缘氧化层，在沟槽内形成绝缘介质层；
第六步：对N型碳化硅衬底下表面进行背面减薄，然后淀积金属层形成阴极金属，在N型碳化硅外延层上表面通过淀积金属形成阳极金属，最终制备得到碳化硅功率二极管器件。
进一步地，在第四步中的绝缘氧化层不填满沟槽，并在绝缘氧化层上淀积多晶硅，使多晶硅填满沟槽，然后依次去除器件表面的多晶硅和绝缘氧化层，在沟槽内得到导电多晶硅及包裹导电多晶硅的绝缘介质层，所述导电多晶硅与阳极金属电连接。
为了进一步实现以上技术目的，本发明还提出一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于，包括以下步骤：
第一步：选取N型碳化硅衬底，采用外延工艺，在N型碳化硅衬底的上表面生长N型碳化硅外延层；
第二步：在第一光刻胶的遮挡下，选择性高能量注入P型杂质，再选择性低能量注入P型杂质，然后进行高温退火，分别形成N型高阻区、P型阱区；
第三步：对N型碳化硅衬底下表面进行背面减薄，然后淀积金属层形成阴极金属，在N型碳化硅外延层上表面通过淀积金属形成阳极金属，最终制备得到碳化硅功率二极管器件。
进一步地，在所述步骤二后，使用第二光刻胶的遮挡，选择性注入P型杂质，然后进行高温退火，在N型高阻区内形成多个间隔分布的块状P型区。
进一步地，所述块状P型区的宽度不大于N型高阻区的厚度。
进一步地，所述步骤二中的N型高阻区还可以通过外延工艺得到，具体为：
在N型碳化硅外延层上表面生长N型高阻层；
在第一光刻胶的遮挡下，在N型高阻层表面选择性低能量注入P型杂质，去除第一光刻胶；
在第三光刻胶的遮挡下，在N型高阻层表面选择性注入N型杂质，去除第三光刻胶；
然后进行高温退火，分别形成P型阱区、位于P型阱区间的N型阱区及位于P型阱区下方的N型高阻区。
进一步地，所述N型阱区和N型碳化硅外延层的电阻率均小于N型高阻区的电阻率，所述N型阱区的电阻率等于N型碳化硅外延层的电阻率或小于N型 碳化硅外延层的电阻率。
与传统碳化硅二极管件相比，本发明具有以下优点：
1)本发明通过在P型阱区下方或下表面增加了一个N型高阻区，如图25所示，在小电流条件下，电子电流从阳极肖特基结流入器件内部，流过N型高阻区，然后以约45度角向阴极扩散流出，P型阱区下方的N型高阻区基本不影响电子电流的流动，因此该结构不会影响器件的正向导通压降；如图26所示，在大电流条件下，将有相当一部分电子电流流过P型阱区下方的N型高阻区，在N型高阻区中存在寄生电阻，因此在N型高阻区内会产生横向压降，导致P型阱区中心下方的电势可以明显降低，器件内的PN结可以更有效的打开，实现更高的电流能力，从而使得器件具备较高的浪涌电流能力；
2)本发明通过在P型阱区内设有若干个间隔分立的沟槽，当电子电流流过N型高阻区时，沟槽的设置可以延长电子电流的流通路径，增加了P型阱区下方的横向电阻，从而保证在大电流条件下器件内的PN结更有效的打开，增加器件的浪涌电流能力；
3)通过在沟槽内设置与阳极金属电连接的导电多晶硅，当器件耐压时，导电多晶硅与其相邻的N型碳化硅外延层或N型阱区横向耗尽，产生横向电场，可提高器件耐压能力；
4)本发明通过在N型高阻区内设有若干个间隔分立的块状P型区，当电子电流流过N型高阻区时，块状P型区的设置可以延长电子电流的流通路径，增加了P型阱区下方的横向电阻，从而保证在大电流条件下器件内的PN结更有效的打开，增加器件的浪涌电流能力；
5)本发明在P型阱区间设置N型阱区，当N型阱区的电阻率小于N型外延层的电阻率，且当器件导通时，能明显降低器件的导通电阻。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1为现有的碳化硅肖特基二极管的结构示意图。
图2为本发明实施例1碳化硅肖特基二极管的结构示意图。
图3为本发明实施例2碳化硅肖特基二极管的结构示意图。
图4为本发明实施例3碳化硅肖特基二极管的结构示意图。
图5为本发明实施例4的碳化硅肖特基二极管的结构剖视图。
图6为本发明实施例5带有4个块状P型区碳化硅肖特基二极管的结构示意图。
图7为本发明实施例6碳化硅肖特基二极管的结构示意图。
图8为本发明实施例7碳化硅肖特基二极管的结构示意图。
图9为本发明实施例8碳化硅肖特基二极管的结构示意图。
图10为本发明实施例9带有4个沟槽的碳化硅肖特基二极管的结构剖视图。
图11为本发明实施例10碳化硅肖特基二极管的结构示意图。
图12为本发明实施例2和实施例7形成N型碳化硅衬底与N型碳化硅外延层的剖视结构示意图。
图13为本发明实施例2和实施例7形成P型阱区与N型高阻区的剖视结构示意图。
图14为本发明实施例2形成块状P型区的剖视结构示意图。
图15为本发明实施例4和实施例9形成N型衬底、N型外延层和N型高阻区的剖视结构示意图。
图16为本发明实施例4和实施例9形成P型阱区的剖视结构示意图。
图17为本发明实施例4和实施例9形成N型阱区的剖视结构示意图。
图18为本发明实施例4形成块状P型区的剖视结构示意图。
图19为本发明实施例7刻蚀沟槽的剖视结构示意图。
图20为本发明实施例7淀积绝缘氧化层和多晶硅的剖视结构示意图。
图21为本发明实施例7形成导电多晶硅与绝缘介质层的剖视结构示意图。
图22为本发明实施例9刻蚀沟槽的剖视结构示意图。
图23为本发明实施例9淀积绝缘氧化层和多晶硅的剖视结构示意图。
图24为本发明实施例9形成导电多晶硅与绝缘介质层的剖视结构示意图。
图25为本发明在小电流条件下的电子电流路径图。
图26为本发明在大电流条件下的N高阻区内的寄生电阻示意图。
附图标记说明：1、阴极金属；2、N型碳化硅衬底；3、N型碳化硅外延层；4、N型高阻区；5、沟槽；6、P型阱区；7、N型阱区；8、阳极金属；9、N型高阻层；10、绝缘介质层；11、导电多晶硅；12、块状P型区。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
实施例1：如图2所示，提供一种高浪涌电流能力碳化硅二极管，在器件的截面方向上，自下而上依次设置阴极金属1、N型碳化硅衬底2、N型碳化硅外延层3及阳极金属8，在所述N型碳化硅外延层3内设置若干个P型阱区6，所述阳极金属8与所述N型外延层3肖特基接触，与P型阱区6欧姆接触；
在所述P型阱区6的下方或下表面设有N型高阻区4，N型高阻区4的宽度与P型阱区6的宽度相同，所述N型高阻区4的电阻率比N型碳化硅外延层3高；
实施例2：如图3所示，提供一种高浪涌电流能力碳化硅二极管，在器件的截面方向上，自下而上依次设置阴极金属1、N型碳化硅衬底2、N型碳化硅外延层3及阳极金属8，在所述N型碳化硅外延层3内设置若干个P型阱区6，所述阳极金属8与所述N型外延层3肖特基接触，与P型阱区6欧姆接触；
在所述P型阱区6的下方或下表面设有N型高阻区4，所述N型高阻区4的电阻率比N型碳化硅外延层3高；在所述N型高阻区4两侧设有块状P型区12，所述块状P型区12与N型碳化硅外延层3邻接，所述块状P型区12的底 部穿过所述N型高阻区4延伸至N型外延层3内，所述块状P型区12的宽度小于或等于N型高阻区4的厚度。
实施例3：如图4所示，提供一种高浪涌电流能力碳化硅二极管，在器件的截面方向上，自下而上依次设置阴极金属1、N型碳化硅衬底2、N型碳化硅外延层3及阳极金属8，在所述N型碳化硅外延层3内设置若干个P型阱区6，所述阳极金属8与所述N型外延层3肖特基接触，与P型阱区6欧姆接触；
在所述P型阱区6的下方或下表面设有N型高阻区4，N型高阻区4的宽度与P型阱区6的宽度相同，所述N型高阻区4的电阻率比N型碳化硅外延层3高；
在相邻的所述P型阱区6之间设置N型阱区7，所述N型阱区7与P型阱区6邻接，且N型阱区7的电阻率小于N型碳化硅外延层3的电阻率。
实施例4：如图5所示，本实施例与实施例1不同的是，在相邻的所述P型阱区6之间设置N型阱区7，所述N型阱区7与P型阱区6邻接，且N型阱区7的电阻率小于N型碳化硅外延层3的电阻率；
在所述N型高阻区4两侧设有块状P型区12，所述块状P型区12与N型碳化硅外延层3邻接，所述块状P型区12的底部穿过所述N型高阻区4延伸至N型外延层3内，所述块状P型区12的宽度小于或等于N型高阻区4的厚度。
实施例5：如图6所示，以一个器件元胞为例，本实施例与实施例4不同的是，不仅在N型高阻区4两侧设置块状P型区12，在N型高阻区4内也均匀设置两个块状P型区12，且块状P型区12的底部依次穿通P型阱区6、N型高阻区4延伸到N型碳化硅外延层3内；
实施例5说明本发明还可通过增加器件元胞内块状P型区12的个数，来进一步的延长电子电流的流通路径，增加了P型阱区6下方的横向电阻，从而保证在大电流条件下器件内的PN结更有效的打开，增加器件的浪涌电流能力，块状P型区12的个数可根据实际器件设计电流大小而定。
实施例6：如图7所示，提供一种高浪涌电流能力碳化硅二极管，在器件的截面方向上，自下而上依次设置阴极金属1、N型碳化硅衬底2、N型碳化硅外延层3及阳极金属8，在所述N型碳化硅外延层3内设置若干个P型阱区6，所述阳极金属8与所述N型外延层3肖特基接触，与P型阱区6欧姆接触；
在所述P型阱区6的下方或下表面设有N型高阻区4，N型高阻区4的宽度与P型阱区6的宽度相同，所述N型高阻区4的电阻率比N型碳化硅外延层3高；在P型阱区6两侧分别设有沟槽5，所述沟槽5与N型碳化硅外延层3邻接，且沟槽5内填充有绝缘介质层10，所述沟槽5的沟槽底部穿过所述N型高阻区4延伸至N型外延层3内。
实施例7：如图8所示，提供一种高浪涌电流能力碳化硅二极管，在器件的截面方向上，自下而上依次设置阴极金属1、N型碳化硅衬底2、N型碳化硅外延层3及阳极金属8，在所述N型碳化硅外延层3内设置若干个P型阱区6，所述阳极金属8与所述N型外延层3肖特基接触，与P型阱区6欧姆接触；
在所述P型阱区6的下方或下表面设有N型高阻区4，N型高阻区4的宽 度与P型阱区6的宽度相同，所述N型高阻区4的电阻率比N型碳化硅外延层3高；在P型阱区6两侧设有沟槽5，所述沟槽5与N型碳化硅外延层3邻接，所述沟槽5的沟槽底部穿过所述N型高阻区4延伸至N型外延层3内；所述沟槽5的侧壁及底部设有绝缘介质层10，所述绝缘介质层10包裹着导电多晶硅11，所述导电多晶硅11与阳极金属8电连接。
实施例8：如图9所示，提供一种高浪涌电流能力碳化硅二极管，在器件的截面方向上，自下而上依次设置阴极金属1、N型碳化硅衬底2、N型碳化硅外延层3及阳极金属8，在所述N型碳化硅外延层3内设置若干个P型阱区6，所述阳极金属8与所述N型外延层3肖特基接触，与P型阱区6欧姆接触；
在所述P型阱区6的下方或下表面设有N型高阻区4，N型高阻区4的宽度与P型阱区6的宽度相同，所述N型高阻区4的电阻率比N型碳化硅外延层3高；在P型阱区6两侧设有沟槽5，所述沟槽5内填充有绝缘介质层10，所述沟槽5的沟槽底部穿过所述N型高阻区4延伸至N型外延层3内；
在相邻的所述P型阱区6之间设置N型阱区7，所述N型阱区7与沟槽5邻接，且N型阱区7的电阻率小于N型碳化硅外延层3的电阻率。
实施例9：如图10所示，本实施例与实施例1不同的是，所述沟槽5的侧壁及底部设有绝缘介质层10，所述绝缘介质层10包裹着导电多晶硅11，所述导电多晶硅11与阳极金属8电连接；在相邻的所述P型阱区6之间设置N型阱区7，所述N型阱区7与沟槽5邻接，且N型阱区7的电阻率小于N型碳化硅外延层3的电阻率。
实施例10：如图11所示，以一个器件元胞为例，本实施例与实施例4不同的是，不仅在P型阱区6两侧设置沟槽5，在P型阱区6内也均匀设置两个沟槽5，且沟槽5的底部依次穿通P型阱区6、N型高阻区4延伸到N型碳化硅外延层3内；
实施例10说明本发明还可通过增加器件元胞内沟槽5的密度，来进一步的延长电子电流的流通路径，增加了P型阱区6下方的横向电阻，从而保证在大电流条件下器件内的PN结更有效的打开，增加器件的浪涌电流能力，沟槽5的个数可根据实际器件设计电流大小而定。
本发明实施例2中的高浪涌电流能力碳化硅二极管的制作方法，具体制作步骤如下：
如图12所示，第一步：选取N型碳化硅衬底2，采用外延工艺，在N型碳化硅衬底2的上表面生长N型碳化硅外延层3；
如图13所示，第二步：在第一光刻胶的遮挡下，选择性高能量注入p型杂质，用于形成N型高阻区4，再选择性低能量注入P型杂质，用于形成P型阱区6，然后去除第一光刻胶，这里第一次注入P型杂质(形成N型高阻区4)的剂量小于第二次注入P型杂质(形成P型阱区6)的剂量，且两次的注入顺序可置换；
如图14所示，第三步；在第二光刻胶的遮挡下，选择性注入高能量的P型杂质，用于形成块状P型区12，然后进行高温退火，形成P型阱区6、位于P 型阱区6下方的N型高阻区4及位于N型高阻区4两侧的块状P型区12；
本发明实施例2中的N型高阻区4还可以通过外延工艺得到，具体为：
如图15所示，在N型碳化硅外延层3上表面生长N型高阻层9；
如图16所示，在第一光刻胶的遮挡下，在N型高阻层9表面选择性低能量注入P型杂质，用于形成P型阱区6，去除第一光刻胶；
如图17所示，在第三光刻胶的遮挡下，在N型高阻层9表面注入N型杂质，去除第三光刻胶；
然后进行高温退火，形成P型阱区6及位于P型阱区6下方的N型高阻区4，同时由于N型杂质的注入，使得相邻P型阱区6间的N型高阻层9的电阻率与N型碳化硅外延层3的电阻率相同(即N型阱区7的电阻率等于N型碳化硅外延层3的电阻率)；
本实施例中N型高阻层9的电阻率与N型高阻区4的电阻率相同，N型高阻区4的电阻率大于N型碳化硅外延层3的电阻率；
本实施例中块状P型区12底部穿过N型高阻区4延伸至N型碳化硅外延层3内，且块状P型区12的宽度小于N型高阻区4的厚度；
如图3所示，第四步：对器件背部进行减薄，并在器件下表面淀积金属层形成阴极金属1，所述阴极金属1与N型碳化硅衬底2欧姆接触，在器件上表面淀积金属形成阳极金属8，所述阳极金属8与N型碳化硅外延层3肖特基接触，与P型阱区6欧姆接触，最终制备获得碳化硅功率二极管器件。
本发明实施例4中的高浪涌电流能力碳化硅二极管的制作方法，具体制作步骤如下：
如图15所示，第一步：选取N型碳化硅衬底2，采用外延工艺，在N型碳化硅衬底2的上表面生长N型碳化硅外延层3，在N型碳化硅外延层3的上表面生长的到N型高阻层9；
如图16所示，第二步：在第一光刻胶的遮挡下，在N型高阻层9表面选择性注入P型杂质，这一步骤是为了形成P型阱区6，去除第一光刻胶；
如图17所示，第三步：在第三光刻胶的遮挡下，在N型高阻层9表面注入N型杂质，这一步骤是为了形成N型阱区7，去除第三光刻胶；
本实施例中N型高阻区4的电阻率与N型高阻层9的电阻率相同，N型阱区7的电阻率小于N型碳化硅外延层3的电阻率，N型碳化硅外延层3的电阻率小于N型高阻区4的电阻率；
如图18所示，第四步；在第二光刻胶的遮挡下，选择性注入P型杂质，这一步骤是为了形成块状P型区12，然后进行高温退火，形成P型阱区6、位于P型阱区6下表面的N型高阻区4、位于P型阱区6间的N型阱区7及位于N型高阻区4两侧的块状P型区12；
本实施例中N型高阻层9的电阻率与N型高阻区4的电阻率相同，N型高阻区4的电阻率大于N型碳化硅外延层3、N型阱区7的电阻率，且N型阱区7的电阻率小于N型碳化硅外延层3的电阻率；
本实施例中块状P型区12底部穿过N型高阻区4延伸至N型碳化硅外延 层3内，且块状P型区12的宽度小于N型高阻区4的厚度；
如图5所示，第五步：对器件背部进行减薄，并在器件下表面淀积金属层形成阴极金属1，所述阴极金属1与N型碳化硅衬底2欧姆接触，在器件上表面淀积金属形成阳极金属8，所述阳极金属8与N型阱区7肖特基接触，与P型阱区6欧姆接触，最终制备获得碳化硅功率二极管器件。
本发明实施例7中的高浪涌电流能力碳化硅二极管的制作方法，具体制作步骤如下：
如图12所示，第一步：选取N型碳化硅衬底2，采用外延工艺，在N型碳化硅衬底2的上表面生长N型碳化硅外延层3；
如图13所示，第二步：在第一光刻胶的遮挡下，选择性高能量注入P型杂质，用于形成N型高阻区4，再选择性低能量注入P型杂质，用于形成P型阱区6，然后进行高温退火，形成P型阱区6及位于P型阱区6下表面的N型高阻区4，然后去除第一光刻胶；这里第一次注入P型杂质的剂量小于第二次注入P型杂质的剂量，且两次的注入顺序可置换；
本发明实施例7中的N型高阻区4还可以通过外延工艺得到，具体为：
如图15所示，在N型碳化硅外延层3上表面生长N型高阻层9；
如图16所示，在第一光刻胶的遮挡下，在N型高阻层9表面选择性低能量注入P型杂质，去除第一光刻胶；
如图17所示，在第三光刻胶的遮挡下，在N型高阻层9表面注入N型杂质，去除第三光刻胶；
然后进行高温退火，形成P型阱区6及位于P型阱区6下方的N型高阻区4，同时由于N型杂质的注入，使得相邻P型阱区6间的N型高阻层9的电阻率与N型碳化硅外延层3的电阻率相同(即N型阱区7的电阻率等于N型碳化硅外延层3的电阻率)；
本实施例中N型高阻层9的电阻率与N型高阻区4的电阻率相同，N型高阻区4的电阻率大于N型碳化硅外延层3的电阻率；
如图19所示，第三步；在第二光刻胶的遮挡下，对器件表面进行刻蚀，得到沟槽5，所述沟槽5与P型阱区6、N型高阻区4邻接；
本实施例中沟槽5底部穿过N型高阻区4延伸至N型碳化硅外延层3内；
如图20所示，第四步：在器件表面及沟槽5内淀积一层绝缘氧化层，在所述绝缘氧化层上淀积多晶硅，多晶硅填满沟槽5；
如图21所示，第五步：依次刻蚀多晶硅、绝缘氧化层，去除器件表面的绝缘氧化层和多晶硅，在沟槽5内形成导电多晶硅11及包裹导电多晶硅11的绝缘介质层10；
如图8所示，第六步：对器件背部进行减薄，并在器件下表面淀积金属层形成阴极金属1，所述阴极金属1与N型碳化硅衬底2欧姆接触，在器件上表面淀积金属形成阳极金属8，所述阳极金属8与N型碳化硅外延层3肖特基接触，与P型阱区6欧姆接触，并与导电多晶硅11电连接，最终制备获得碳化硅功率二极管器件。
本发明实施例9中的高浪涌电流能力碳化硅二极管的制作方法，具体制作步骤如下：
如图15所示，第一步：选取一N型碳化硅衬底2，采用外延工艺，在N型碳化硅衬底2的上表面生长N型碳化硅外延层3，在N型碳化硅外延层3的上表面生长的到N型高阻层9；
如图16所示，第二步：在第一光刻胶的遮挡下，在N型高阻层9表面选择性注入P型杂质，这一步骤是为了形成P型阱区6，去除第一光刻胶；
如图17所示，第三步：在第三光刻胶的遮挡下，在N型高阻层9表面注入N型杂质，这一步骤是为了形成N型阱区7，去除第三光刻胶；
然后进行高温退火，形成P型阱区6、位于P型阱区6下表面的N型高阻区4及位于P型阱区6间的N型阱区7；
本实施例中N型高阻区4的电阻率与N型高阻层9的电阻率相同，N型阱区7的电阻率小于N型碳化硅外延层3的电阻率，N型碳化硅外延层3的电阻率小于N型高阻区4的电阻率；
如图22所示，第四步；在第二光刻胶的遮挡下，对器件上表面进行刻蚀，得到沟槽5，所述沟槽5位于P型阱区6两侧；
本实施例中沟槽5底部穿过N型高阻区4延伸至N型碳化硅外延层3内；
如图23所示，第五步：在器件表面及沟槽5内淀积一层绝缘氧化层，在所述绝缘氧化层上淀积多晶硅，多晶硅填满沟槽5；
如图24所示，第六步：依次刻蚀多晶硅、绝缘氧化层，去除器件表面的绝缘氧化层和多晶硅，在沟槽5内形成导电多晶硅11及包裹导电多晶硅11的绝缘介质层10；
如图10所示，第七步：对器件背部进行减薄，并在器件下表面淀积金属层形成阴极金属1，所述阴极金属1与N型碳化硅衬底2欧姆接触，在器件上表面淀积金属形成阳极金属8，所述阳极金属8与N型阱区7肖特基接触，与P型阱区6欧姆接触，并与导电多晶硅11电连接，最终制备获得碳化硅功率二极管器件。
当本发明器件耐压时，P型阱区6能够分散器件的表面电场，提高器件耐压；在器件导通瞬间，电流会先从肖特基接触的位置经过，同时有电流流过N型高阻区4，这使得P型阱区6与N型高阻区4组成的PN结的压差增加，当压差达到3V时，PN结开启并向N型碳化硅外延层3注入空穴，此时器件彻底地正向导通。
以上对本发明及其实施方式进行了描述，该描述没有限制性，附图中所示的也只是本发明的实施方式之一，实际结构并不局限于此。总而言之如果本领域的普通技术人员受其启示，在不脱离本发明创造宗旨的情况下，不经创造性的设计出与该技术方案相似的结构方式及实施例，均应属于本发明的保护范围。

Claims (15)

  1. 一种高浪涌电流能力碳化硅二极管，包括半导体基板，所述半导体基板包括N型碳化硅衬底及位于N型碳化硅衬底上的N型碳化硅外延层，在所述N型碳化硅外延层内的上部设有若干个P型阱区，其特征在于，在所述P型阱区下方或下表面设有N型高阻区，所述N型高阻区的电阻率大于N型碳化硅外延层的电阻率。
  2. 根据权利要求1所述的一种高浪涌电流能力碳化硅二极管，其特征在于：在N型高阻区内设有若干个均匀间隔的块状P型区，且块状P型区从N型高阻区与P型阱区交界处延伸到N型高阻区内或穿过N型高阻区延伸到N型碳化硅外延层内。
  3. 根据权利要求2所述的一种高浪涌电流能力碳化硅二极管，其特征在于：所述块状P型区的宽度不大于N型高阻区的厚度。
  4. 根据权利要求1所述的一种高浪涌电流能力碳化硅二极管，其特征在于：在相邻的P型阱区间设有N型阱区，所述N型阱区的电阻率等于N型碳化硅外延层的电阻率或小于N型碳化硅外延层的电阻率。
  5. 一种高浪涌电流能力碳化硅二极管，包括半导体基板，所述半导体基板包括N型碳化硅衬底及位于N型碳化硅衬底上的N型碳化硅外延层，在所述N型碳化硅外延层内的上部设有若干个P型阱区，其特征在于，在所述P型阱区下方或下表面设有N型高阻区，所述N型高阻区的电阻率大于N型碳化硅外延层的电阻率，在P型阱区内设有多个沟槽，位于P型阱区边缘的沟槽与N型碳化硅外延层邻接，且沟槽从半导体基板的上表面穿过P型阱区延伸到N型高阻区内或依次穿过P型阱区、N型高阻区延伸到N型碳化硅外延层内，所述沟槽内填充有绝缘介质层。
  6. 根据权利要求1或5所述的一种高浪涌电流能力碳化硅二极管，其特征在于：在所述半导体基板的上表面设有阳极金属，所述阳极金属与所述N型外延层肖特基接触，与P型阱区欧姆接触；在所述半导体基板的下表面设有阴极金属，所述阴极金属与N型碳化硅衬底欧姆接触。
  7. 根据权利要求6所述的一种高浪涌电流能力碳化硅二极管，其特征在于：所述沟槽内设有导电多晶硅及包裹导电多晶硅的绝缘介质层，所述导电多晶硅与阳极金属电连接。
  8. 根据权利要求5所述的一种高浪涌电流能力碳化硅二极管，其特征在于：在相邻的P型阱区间设有N型阱区，所述N型阱区与沟槽邻接，所述N型阱区的电阻率小于N型高阻区的电阻率，所述N型阱区的电阻率等于N型碳化硅外延层的电阻率或小于N型碳化硅外延层的电阻率。
  9. 一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于，包括以下步骤：
    第一步：选取N型碳化硅衬底，采用外延工艺，在N型碳化硅衬底的上表面生长N型碳化硅外延层；
    第二步：在第一光刻胶的遮挡下，选择性高能量注入P型杂质，再选择性低能量注入P型杂质，然后进行高温退火，分别形成N型高阻区、P型阱区；
    第三步；在第二光刻胶的遮挡下，对N型碳化硅外延层进行刻蚀，得到位于P型阱区内的多个沟槽；
    第四步：在N型碳化硅外延层表面及沟槽内生长绝缘氧化层，所述绝缘氧化层填满沟槽；
    第五步：对绝缘氧化层进行刻蚀，去除N型碳化硅外延层表面的绝缘氧化层，在沟槽内形成绝缘介质层；
    第六步：对N型碳化硅衬底下表面进行背面减薄，然后淀积金属层形成阴极金属，在N型碳化硅外延层上表面通过淀积金属形成阳极金属，最终制备得到碳化硅功率二极管器件。
  10. 根据权利要求9所述的一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于：在第四步中的绝缘氧化层不填满沟槽，并在绝缘氧化层上淀积多晶硅，使多晶硅填满沟槽，然后依次去除器件表面的多晶硅和绝缘氧化层，在沟槽内得到导电多晶硅及包裹导电多晶硅的绝缘介质层，所述导电多晶硅与阳极金属电连接。
  11. 一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于，包括以下步骤：
    第一步：选取N型碳化硅衬底，采用外延工艺，在N型碳化硅衬底的上表面生长N型碳化硅外延层；
    第二步：在第一光刻胶的遮挡下，选择性高能量注入P型杂质，再选择性低能量注入P型杂质，然后进行高温退火，分别形成N型高阻区、P型阱区；
    第三步：对N型碳化硅衬底下表面进行背面减薄，然后淀积金属层形成阴极金属，在N型碳化硅外延层上表面通过淀积金属形成阳极金属，最终制备得到碳化硅功率二极管器件。
  12. 根据权利要求11所述的一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于：在所述步骤二后，使用第二光刻胶的遮挡，选择性注入P型杂质，然后进行高温退火，在N型高阻区内形成多个间隔分布的块状P型区。
  13. 根据权利要求12所述的一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于：所述块状P型区的宽度不大于N型高阻区的厚度。
  14. 根据权利要求9或11所述的一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于：所述步骤二中的N型高阻区还可以通过外延工艺得到，具体为：
    在N型碳化硅外延层上表面生长N型高阻层；
    在第一光刻胶的遮挡下，在N型高阻层表面选择性低能量注入P型杂质，去除第一光刻胶；
    在第三光刻胶的遮挡下，在N型高阻层表面选择性注入N型杂质，去除第三光刻胶；
    然后进行高温退火，分别形成P型阱区、位于P型阱区间的N型阱区及位 于P型阱区下方的N型高阻区。
  15. 根据权利要求14所述的一种高浪涌电流能力碳化硅二极管的制造方法，其特征在于：所述N型阱区和N型碳化硅外延层的电阻率均小于N型高阻区的电阻率，所述N型阱区的电阻率等于N型碳化硅外延层的电阻率或小于N型碳化硅外延层的电阻率。
PCT/CN2018/105133 2018-08-29 2018-09-12 一种高浪涌电流能力碳化硅二极管及其制作方法 WO2020042221A1 (zh)

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