WO2018102981A1

WO2018102981A1 - Full-duplex and half-duplex serial port signal conversion circuit, and robot

Info

Publication number: WO2018102981A1
Application number: PCT/CN2016/108660
Authority: WO
Inventors: 郝磊
Original assignee: 吉蒂机器人私人有限公司; 郝磊
Priority date: 2016-12-06
Filing date: 2016-12-06
Publication date: 2018-06-14
Also published as: CN109313621B; CN109313621A

Abstract

A full-duplex and half-duplex serial port signal conversion circuit, and a robot, wherein said circuit comprises: a first logic gate branch circuit and a second logic gate branch circuit. The first logic gate branch circuit is connected between a full-duplex signal output terminal and a half-duplex signal transceiver terminal, and is used to transmit a logic signal outputted by the full-duplex signal output terminal to the half-duplex signal transceiver terminal, as well as to output an enabling signal generated according to the logic signal outputted by the full-duplex signal output terminal from an enabling signal output terminal of the first logic gate branch circuit to an enabling output terminal of the second logic gate branch circuit; the second logic gate branch circuit is connected between a full-duplex signal receiving terminal and the half-duplex signal transceiver terminal, and is used to correspondingly switch the second logic gate branch circuit on or off according to the enabling signal received by the enabling output terminal of the second logic gate branch circuit, and when the second logic gate branch circuit is switched on, the logic signal outputted by the half-duplex signal transceiver terminal is transmitted to the full-duplex signal receiving terminal.

Description

Full-duplex and half-duplex serial signal conversion circuit and robot

Technical field

The present application relates to electronic circuit technology, for example, to a full-duplex and half-duplex serial port signal conversion circuit and a robot.

Background technique

In recent years, the application of robots has become more and more extensive, and various robot motors have appeared accordingly. Among them, the digital servo motor uses a half-duplex serial port signal to connect multiple motors in series. The control signal of the digital servo motor is Half-duplex serial signal. In order to facilitate the serial connection of the digital servo motor, the full-duplex serial port signal is usually changed into a half-duplex serial port signal, so that the control line of the digital servo motor has both a transmitting signal and an accepting signal, but they are time-sharing. produced.

The full-duplex and half-duplex serial port signal conversion circuits in the related art use software to control the transmission and reception of signals, and the reliability of serial port signal conversion will be affected by software programs, and program development will change the design cycle. Long, increased costs due to increased control signals.

Summary of the invention

The application provides a full-duplex and half-duplex serial port signal conversion circuit and a robot, so as to realize hardware-based conversion of a full-duplex serial port signal and a half-duplex serial port signal.

In a first aspect, the embodiment of the present application provides a full-duplex and a half-duplex serial port signal conversion circuit, including: a first logic gate branch and a second logic gate branch; wherein

The first logic gate branch is connected between the full-duplex signal output end and the half-duplex signal transceiver end, and is used for transmitting the logic signal outputted by the full-duplex signal output end to the half-duplex signal transceiver end, and The enable signal generated by the logic signal outputted from the duplex signal output is output from the enable signal output end of the first logic gate branch to the enable output end of the second logic gate branch;

The second logic gate branch is connected between the full-duplex signal receiving end and the half-duplex signal transceiver end, and is configured to be turned on according to an enable signal received by the enable output end of the second logic gate branch. The second logic gate branch is disconnected, and when the second logic gate branch is turned on, the logic signal outputted by the half duplex signal transceiver end is transmitted to the full duplex signal receiving end.

Optionally, the first logic gate branch includes: a first buffer, a second buffer, and an inverter; wherein

The input end of the first buffer is connected to the full duplex signal output end, the output end of the first buffer is connected to the input end of the second buffer, and the output end of the first buffer is enabled as the first logic gate branch Signal output

The output of the second buffer is coupled to the half-duplex signal transceiver;

The input of the inverter is coupled to the output of the first buffer, and the output of the inverter is coupled to the enable output of the second buffer.

Optionally, the second logic gate branch includes: a third buffer; wherein

The input end of the third buffer is connected to the half-duplex signal transceiver end, the output end of the third buffer is connected to the full-duplex signal receiving end, and the enable output end of the third buffer is used as the second logic gate branch. Can output.

In a second aspect, the embodiment of the present application further provides a robot, including a CPU having a full-duplex communication serial port, at least one digital servo motor having a half-duplex communication serial port, and any of the methods provided by the embodiments of the present application. a full-duplex and a half-duplex serial port signal conversion circuit, wherein the CPU is connected to the digital servo motor through the full-duplex and half-duplex serial port signal conversion circuit provided by the first aspect, and the full-duplex The half-duplex serial port signal conversion circuit implements bidirectional transmission of communication signals between the CPU and the digital servo motor.

The embodiment of the present application completes the conversion of the full-duplex signal and the half-duplex signal by hardware, and solves the problem of using the software to control the signal transmission and reception, the reliability is affected by the software program, and the design cycle caused by the program development is prolonged, and the cost is increased. Can improve reliability and responsiveness.

DRAWINGS

1 is a schematic structural diagram of a full-duplex and half-duplex serial port signal conversion circuit in Embodiment 1 of the present application;

FIG. 2 is a schematic structural diagram of a robot in Embodiment 2 of the present application.

detailed description

The present application will be described below in conjunction with the accompanying drawings and embodiments. The alternative embodiments described herein are merely illustrative of the application and are not intended to be limiting. For the convenience of description, only some but not all of the structures related to the present application are shown in the drawings. The features in the embodiments and the embodiments may be arbitrarily combined with each other without conflict.

Embodiment 1

1 is a schematic structural diagram of a full-duplex and a half-duplex serial port signal conversion circuit according to Embodiment 1 of the present application. This embodiment is applicable to conversion of a full-duplex signal and a half-duplex signal. Referring to FIG. 1 and FIG. 2, The full-duplex and half-duplex serial port signal conversion circuit 1 includes: a first logic gate branch 10 and a second logic gate branch 20;

The first logic gate branch 10 is connected between the full-duplex signal output terminal 310 and the half-duplex signal transceiver terminal 410 for transmitting the logic signal output by the full-duplex signal output terminal 310 to the half-duplex signal transceiver terminal 410. And an enable signal generated by the logic signal output from the full-duplex signal output terminal 310 is output from the enable signal output terminal 110 of the first logic gate branch 10 to the enable output terminal 210 of the second logic gate branch 20. ;

The second logic gate branch 20 is connected between the full duplex signal receiving terminal 320 and the half duplex signal transceiver terminal 410 for receiving the enable signal according to the enable output terminal 210 of the second logic gate branch 20, Correspondingly, the second logic gate branch 20 is turned on or off. When the second logic gate branch 20 is turned on, the logic signal outputted by the half-duplex signal transceiver terminal 410 is transmitted to the full-duplex signal receiving terminal 320.

As shown in FIG. 1, the full duplex signal output terminal 310 of the first microprocessor 3 is used to transmit a communication signal, the full duplex signal receiving terminal 320 is used to receive a communication signal, and the half duplex signal of the second microprocessor 4 is shown. The transceiver terminal 410 is configured to send and receive communication signals. It can be understood that the first microprocessor 3 and the second microprocessor 4 shown in FIG. 1 are only examples and are not limiting.

The full-duplex and half-duplex serial port signal conversion circuit generates intermediate control signals by pure hardware according to the characteristics of the full-duplex serial port signal and the half-duplex serial port signal, thereby realizing bidirectional transmission of signals.

Optionally, the first logic gate branch 10 includes: a first buffer 101, a second buffer 102, and an inverter 103;

The input end of the first buffer 101 is connected to the full-duplex signal output terminal 310, the output end of the first buffer 101 is connected to the input end of the second buffer 102, and the output end of the first buffer 101 is used as the first logic gate. The enable signal output terminal 110 of the branch 10;

The output of the second buffer 102 is connected to the half-duplex signal transceiver 410;

The input of the inverter 103 is connected to the output of the first buffer 101, and the output of the inverter 103 is connected to the enable output of the second buffer 102.

The first buffer 101 is a conventional buffer gate, and the output logic is the same as the input logic, and has no logic conversion function. The second buffer 102 is a three-state buffer, and the three-state output is controlled by the enable output. When the enable output is valid, the device implements a normal logic state output (logic 0, logic 1). When the enable input is invalid, the output is output. In a high resistance state. Output logic of inverter 103 Contrary to the input logic, that is, the inverter input logic 0, then output logic 1; input logic 1, then output logic 0.

Optionally, the second logic gate branch 20 includes: a third buffer 201, where

The input end of the third buffer 201 is connected to the half-duplex signal receiving end 410, the output end of the third buffer 201 is connected to the full-duplex signal receiving end 320, and the enabled output end of the third buffer 201 is used as the second logic. The enable output 210 of the gate leg 20 is provided.

The third buffer 201 is a three-state buffer.

When the full duplex signal output terminal 310 transmits the signal "1", the first buffer 101 outputs "1", and the inverter 103 outputs "0" to the enable output terminal of the second buffer 102, so that the second buffer 102 is disabled and the output of the second buffer 102 is pulled up to transmit the "1" transmitted by the full-duplex signal output 310 to the half-duplex signal transceiver 410. When the full duplex signal output terminal 310 transmits the signal "0", the first buffer 101 outputs "0", the inverter 103 outputs "1", and then the second buffer 102 is turned on, and the second buffer 102 outputs " The 0' to half-duplex signal transceiver terminal 410 transmits the "0" transmitted by the full-duplex signal output terminal 310 to the half-duplex signal transceiver terminal 410.

When the half-duplex signal transmitting and receiving terminal 410 transmits a signal to the full-duplex signal receiving terminal 320, the full-duplex signal output terminal 310 outputs "1", and the first buffer 101 outputs "1", so that the third buffer 201 is turned on. Thus, the signal sent by the half duplex signal transceiver terminal 410 is transmitted to the full duplex signal receiving terminal 320.

The technical solution of the embodiment solves the conversion of the full-duplex signal and the half-duplex signal by hardware, and solves the problem of using the software to control the transmission and reception of the signal, the reliability is affected by the software program, and the design cycle caused by the program development is prolonged and increased. The problem of cost, improve reliability, and respond quickly.

Embodiment 2

2 is a schematic structural diagram of a robot according to Embodiment 2 of the present application. The robot R1 includes a CPU (Central Processing Unit) 5 having a full-duplex communication serial port and at least one digital half-duplex communication serial port. The servo motor 6, the CPU 5 is connected by the full-duplex and half-duplex serial signal conversion circuit 1 and the digital servo motor 6 provided in the first embodiment, and realizes the CPU 5 and the digital through the full-duplex and half-duplex serial port signal conversion circuit 1. Bidirectional transmission of communication signals between servo motors 6. For example, the robot R1 may be a humanoid robot, and may include a CPU with a full-duplex communication serial port, and a plurality of digital servo motors with a half-duplex communication serial port, and the CPU passes the full-duplex communication serial port to the digital servo. The motor sends a command and receives a feedback signal, and the digital servo motor receives the command sent by the CPU through the half-duplex communication serial port, and the CPU The feedback signal is sent, so that the digital servo motor can drive the limb of the humanoid robot to perform corresponding actions according to the instruction issued by the CPU.

In FIG. 2, the robot R1 has only one digital servo motor 6 as an example, and the CPU 5 is connected through the full-duplex and half-duplex serial port signal conversion circuit 1 and the digital servo motor 6. Alternatively, the full-duplex signal output of the CPU 5 is selected. The terminal 510 is connected to the first logic gate branch 10 of the full-duplex and half-duplex serial port signal conversion circuit 1 and the half-duplex signal transceiver terminal 610 of the digital servo motor 6. The full-duplex signal receiving end 520 of the CPU 5 passes The second logic gate branch 20 in the full-duplex and half-duplex serial port signal conversion circuit 1 is connected to the half-duplex signal transceiver terminal 610 of the digital servo motor 6. The communication process of the CPU 5 and the digital servo motor 6 is as follows. A technical solution provided.

The above is only an alternative embodiment of the present application. It will be appreciated by those skilled in the art that the present invention may be susceptible to various modifications, adaptations and substitutions without departing from the scope of the invention. The present application has been described by the above embodiments, but the present application may include other equivalent embodiments, and the scope of the present application is determined by the scope of the appended claims.

Industrial applicability

The embodiment of the present application provides a full-duplex and half-duplex serial port signal conversion circuit and a robot, which realizes conversion of a full-duplex signal and a half-duplex signal by hardware, thereby having high reliability and rapid response.

Claims

Full-duplex and half-duplex serial port signal conversion circuit, comprising: a first logic gate branch and a second logic gate branch; wherein the first logic gate branch is connected to the full-duplex signal output terminal and the half-duplex signal transceiver Between the ends, the logic signal for outputting the full-duplex signal output terminal is transmitted to the half-duplex signal transceiver end, and the enable signal generated according to the logic signal outputted by the full-duplex signal output terminal is used by the first logic gate The enable signal output of the circuit is output to an enable output of the second logic gate;

The second logic gate branch is connected between the full-duplex signal receiving end and the half-duplex signal transceiver end, and is configured to be turned on according to an enable signal received by the enable output end of the second logic gate branch. The second logic gate branch is disconnected, and when the second logic gate branch is turned on, the logic signal outputted by the half duplex signal transceiver end is transmitted to the full duplex signal receiving end.
The circuit of claim 1 wherein the first logic gate comprises: a first buffer, a second buffer and an inverter; wherein

The input end of the first buffer is connected to the full duplex signal output end, the output end of the first buffer is connected to the input end of the second buffer, and the output end of the first buffer is enabled as the first logic gate branch Signal output

The output of the second buffer is coupled to the half-duplex signal transceiver;

The input of the inverter is coupled to the output of the first buffer, and the output of the inverter is coupled to the enable output of the second buffer.
The circuit of claim 1 wherein the second logic gate comprises: a third buffer; wherein the input of the third buffer is coupled to the half-duplex signal transceiver, and the output of the third buffer is The full-duplex signal receiving end is connected, and the enabled output end of the third buffer is used as an enabling output end of the second logic gate branch.
A robot comprising a CPU having a full-duplex communication serial port, at least one digital servo motor having a half-duplex communication serial port, and full-duplex and half-duplex serial port signal conversion according to any one of claims 1-3 Circuit, where

The CPU is connected to the digital servo motor by the full-duplex and half-duplex serial port signal conversion circuit according to any one of claims 1-3, and is implemented by the full-duplex and half-duplex serial port signal conversion circuit. Bidirectional transmission of communication signals between the CPU and the digital servo motor.