WO2018004663A1

WO2018004663A1 - Two transistor memory cell with metal oxide semiconductors and silicon transistors

Info

Publication number: WO2018004663A1
Application number: PCT/US2016/040742
Authority: WO
Inventors: Van H. Le; Gilbert William DEWEY; Rafael Rios; Jack T. Kavalieros; Marko Radosavljevic; Shriram SHIVARAMAN; Mesut Meterelliyoz
Original assignee: Intel Corporation
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2018-01-04

Abstract

A two transistor memory cell is described with amorphous oxide semiconductors and silicon transistors. In some examples a memory cell includes a sensing transistor having a source coupled to a read bit line and a drain coupled to a read word line, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transistor.

Description

TWO TRANSISTOR MEMORY CELL WITH METAL OXIDE SEMICONDUCTORS AND

SILICON TRANSISTORS

FIELD

The present description is related to memory cells for semiconductors and, in particular, to two transistor memory cells using amorphous oxide semiconductors.

BACKGROUND

In silicon semiconductor processors, memory is critical for performing many functions. For particularly high speed memory SRAM (Static Random Access Memory) is used. The SRAM circuits are usually embedded into the same die as logic circuitry, although discrete SRAM dies are also made. For embedded applications, the memory is built on the same die as the processor and so compatibility with CMOS (Complementary Metal Oxide Semiconductor) logic circuitry allows costs to be reduced. On the other hand a typical SRAM circuit has six transistors and so is expensive to produce in large numbers. SRAM also requires frequent refresh cycles and so it consumes power and generates heat.

2T (two transistor) or 3T memory gain cells are normally used for DRAM (Dynamic Random Access Memory). DRAM is not as fast as 6T SRAM but is less expensive and requires less frequent refresh cycles. A DRAM cell stores the memory state in a capacitor and so for optimum performance DRAM is built on separate dies for which the design of the capacitor is optimized. With a separate die, the DRAM can be made using the best or lowest cost techniques available for DRAM without regard to the logic circuitry. Nevertheless, there are still high off- state leakages that limit the retention times of the corresponding memory cell. Therefore, constant refresh cycles are required to retain the state stored in the memory. The refresh cycles require power so that DRAM also requires constant power and generates significant heat.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

Figure 1 is a circuit diagram of a two transistor memory cell according to an

embodiment.

Figure 2 is a diagram of a two transistor memory cell array according to an embodiment. Figure 3 is a cross-sectional side view diagram of a memory cell with a charging transistor in a metal layer above silicon logic according to an embodiment. Figure 4 is a cross-sectional side view diagram of an alternative memory cell with a charging transistor in a metal layer above silicon logic according to an embodiment.

Figure 5 is a process flow diagram of fabricating a two transistor memory cell according to an embodiment.

Figure 6 is a block diagram of a computing device incorporating a die with a memory cell array according to an embodiment.

DETAILED DESCRIPTION

As described herein a low off-state leakage write transistor such as a metal oxide semiconductor, or an amorphous oxide semiconductor (AOS) such as IGZO (Indium Gallium Zinc Oxide), transistor may be fabricated for use in a memory cell. This may be combined with higher mobility silicon MOSFET (Metal Oxide Semiconductor Field Effect Transistor) read and pass gate transistors in a 2T memory cell. Non-Si based transistors such as metal oxide semiconductors with high mobility and low off-state leakage current are suitable for use in very high speed memory applications, such as those normally reserved for SRAM. In addition, these materials can be deposited in the back end layers of a silicon die stack to allow for vertical; 3-D integration. Stacking the memory over other logic increases the scaling density of the die.

Embedded memory becomes increasingly important in efforts to reduce the total number of dies and also to increase speed. A reduced overall memory array footprint helps reduce aerial density scaling and cost. This is particularly true of memory which comes in large arrays and with traditional SRAM that uses six transistors. A 3-D vertical 2T memory array that can be created in the back end layers presents real benefits. The described fabrication of 2T memory can replace 6T SRAM for certain on-die memory applications, thereby allowing for higher density and lower costs.

2T memory cells are used in some high speed memory applications and offer a speed in between that of SRAM and DRAM. In a 2T cell, the gate capacitance of one of the transistors is used as the storage element and the gate capacitance of the other transistor is used as the charging element. The retention time of the memory cell is limited by the total leakage in the OFF state. Moreover, the current in the sensing transistor varies by orders of magnitude between a "0" or OFF state and the "1" or ON state, providing wide read margins. The read speed depends at least on part on the speed of the sensing transistor.

Figure 1 is a circuit diagram of a single 2T memory cell 102. It has a charging transistor 104 with a source coupled to a write bitline WBL and a gate coupled to a write word line WWL. The drain is coupled to the gate of a read or sensing transistor 106. The source of the sensing transistor is coupled to a read bit line RBL and the drain is coupled to a read word line RWL. As mentioned above, there is an inherent capacitance 108 between the drain of the charging transistor and the gate of the sensing transistor. There may also be a physical actual capacitor in this location.

The charging or write transistor may be formed with a very low off-state leakage using a metal oxide semiconductor, or an AOS such as IGZO as the channel material. The sense or read transistor may be fabricated with a high mobility low leakage silicon MOSFET design formed in the front side layers of a silicon die. This provides for a fast and very small sensing gate transistor. The charge may then be stored in the channel of the charging transistor very quickly for fast write times. No additional capacitor is required using an AOS charging transistor.

The metal oxide semiconductor channel construction allows the charging transistor to be fabricated in metal and dielectric without doped silicon wells. This is indicated with various contacts of the transistors being labeled by a metal layer indicator from Ml to M2. These are provided as examples. Different metal layers may be used to suit different implementations. In addition, memory cells may be stacked over each other so that one memory cell may use metal layers M1-M2 and another uses M4-M5 or any other desired pattern to suit the intended memory array design.

Figure 2 is an example of a 2T memory cell array 122 with rows across the horizontal direction and columns down the vertical direction. The rows share bitlines and the columns share word lines. Each 2T grouping provides one bit of storage as ON or OFF. Considering one of the cells 124 in position (0,1) labeled as transistor A, it is shown as storing a "1" or ON state.

This state was written by activating or setting to ON or high WBL1 and WWL0 for as long as it takes to store a sufficient charge.

In order to read the same cell, RBL1 is charged to "1" for a precharge phase. Next RWL0 is pulled to "0" to select cell (1,0). The other RWL remain at "1." The ON or "1" state of transistor A is then sensed on RWL0 through the sense transistor.

Figure 3 is a cross-sectional side view diagram of a 3D vertical configuration for a memory cell 202 in metal layers over silicon logic circuitry. The 2T memory cell is formed as embedded memory in a die that contains other logic. The other logic may be for a central processor chip, a graphics processor chip, an image processing chip, a digital signal processor, or any of a variety of other types of logic and processing circuitry. The die is built on a substrate

204, such as a silicon substrate and logic circuitry 206 is formed on the front side of the substrate. This typically referred to as FEOL (Front End of the Line). The application of the metal layers alternating with dielectric layers is typically referred to as the BEOL (Back End of the Line) and is used to provide connections between the logic components transistors, capacitors, resistors, etc. of the FEOL. The BEOL also uses vias through the dielectric between metal layers to provide connections from the logic to pads for external connections. The dielectric layers are sometimes referred to as ILD (Interlayer

Dielectric) with numbers to indicate the number of layers.

In the illustrated example there is a bottom metal layer 208 applied over one or more metal and dielectric (ILD) layers over the logic circuitry 206. This layer is labeled Ml, suggesting that there is another layer M0 below it, however, any other layer may be used instead. The bottom metal layer may be copper, aluminum, tungsten or any other suitable metal material. A dielectric layer 210 is applied over the bottom metal layer. The dielectric may be formed of any of a variety of different materials including SnC>2, ITO, or IZO. A second metal layer, M2, 212 is applied over the first dielectric 210. Another dielectric layer 214 is applied over the second metal layer 212 and a top metal layer, M3, 216 is applied over the second dielectric. While three metal layers are sufficient to form the memory cell, there may be more layers for other purposes above and below the memory cell.

The memory cell is formed of a sensing transistor (not shown) coupled together within the logic circuitry of the silicon substrate and coupled to a charging transistor in the metal layers. The charging transistor 220 is built in the metal layers with a via 222 between the source 224 of the charging transistor in the first metal layer through the first dielectric 210 to the gate of the sensing transistor. The via may connect directly to the gate or be coupled to the gate through other traces, components or lines in the logic circuitry. In this example, the via connects first to the bottom metal layer which routes the connection to the sensing transistor in the silicon logic circuity 206.

The sensing transistor is a thick gate, low leakage transistor. This sensing transistor will be similar to other logic circuitry Si transistors except with a thicker gate oxide. The gate oxide thickness may be balanced against capacitance and response times. High speed is valued since the sensing transistor may limit the read times. The thick gate is selected to reduce the gate leakage in the sensing transistor. This improves retention times and reduces power consumption. This transistor may have a very low Lg. Smaller lengths improve density scaling, and give higher drive currents. This is further balanced against tolerable subthreshold swing control with the thicker gate oxide.

The charging transistor 220 has a source 224 and a drain 226 in the second metal layer 212 or any other metal layer depending on the particular implementation. The source 224 connects to the via 222 from the gate of the sensing transistor. An amorphous oxide

semiconductor (AOS) layer 230 is formed as a channel in the dielectric layer 214 and between the source and the drain. For a typical memory cell, this layer may be 6-8nm thick and is in direct electrical contact with the source and drain. The AOS material is selected for low leakage so that the charge may be stored longer with less frequent refreshes. One suitable material is Indium Gallium Zinc Oxide (IGZO). As further alternatives, the channel material may be IZO (Indium Zinc Oxide, In203, Sn02, ITO (Indium Tin Oxide), ZnO, or other materials. While the channel is referred to as AOS, any metal oxide may be used and the oxide may be in an amorphous, crystalline, or polycrystalline state, or it may change states during use. A high K dielectric layer 232 is formed over the AOS layer. This layer may be 5-10nm thick and the thickness is selected based on a balance of leakage and electrostatics for the device. A metal gate layer 234 is formed over the high K dielectric to form the gate.

A conductive via 238 such as a filled copper via is formed over the gate to connect to the next metal layer 216 through the dielectric layer 214 in which the gate has been formed. The charging transistor stores charge in the connection 222 between the source of the charging transistor and the gate of the sensing transistor. In this example, the connection is a via through the first dielectric. By using a very low leakage gate in the charging transistor, the stored charge is maintained longer for a lower refresh rate. The sensing transistor is a thin gate high mobility device to support very fast reads.

The metal gate 234 above the storage node 222 is coupled through another via 238 to a connection pad 240 on the metal layer 214 above the gate. This connection pad serves as the gate electrode for connection to the WWL. The metal layer is used for routing the WWL, connecting to other memory cells and connecting to the write circuitry and controllers in the logic circuitry layer 206. These controllers may be in the logic circuitry 206 below the metal layers or in another location. Other vias may be used to connect other components to form the memory array. Addressing, refresh, and read circuity may be formed in the logic circuitry 206 below the memory array and be connected to the metal layers using vertical vias.

As an alternative construction, the metal gates may be formed directly over and in contact with the metal electrodes 224, 226 of the transistor below to form a direct electrical contact. The dielectric may then be formed over the metal gate and the metal oxide channel over the dielectric. Instead of using vias to reach down and contact the gate, the vias from the next layer up reach down to contact the gate channel. Accordingly, the source and drain of a transistor is above the gate channel and connect using vias, while the gate electrode is below the gate and is a direct connection with the lower metal layer. The source in the lower metal layer of the transistor below becomes the storage node instead of the via. This inverted approach may provide for a better redistribution within the metal layers than the illustrated approach.

Figure 4 is a cross-sectional side view diagram of an alternative structure for the AOS 2T memory cell of Figure 3. The structure is similar in that the source and drain contacts for the charging transistor 262 is formed in metal layers of the BEOL. A metal gate 266 is formed in the dielectric layers between the metal layers. An AOS channel 270 is formed over the source and drain and is isolated from the metal gate by a high K dielectric 268. This is an example of a Damascene-like approach. Rather than using substractive methods, the films are deposited include a pre-formed trench between the source and the drain. As a result the IGZO channel is deposited without any damage to the film.

In the example of Figure 3, the AOS channel and the high K dielectric are in horizontal layers only. In the example of Figure 4, both the AOS channel 270 and the high K dielectric 268 wrap around the sides of the metal gate. The bottom of the gate over the source and drain and the sides of the gate within the dielectric layer are covered by these two layers.

Figure 5 is a process flow diagram for forming a 3T memory cell array with charging transistors in BEOL layers as shown in Figures 3 and 4. At 502 the logic circuitry is formed on the silicon die, this includes the sensing transistor for each memory cell of the array as well as the read, write, refresh and other circuitry. The sensing transistor is designed for low leakage with thick gates and for fast reads. The logic circuitry layer also includes the RBL, RWL, and WWL for the memory cell and the necessary circuitry to activate and drive these lines. At 504 an interlayer dielectric is applied over the logic circuitry. There may also be other layers applied over the logic circuitry depending on the particular implementation.

At 506 a CMP (chemical metal planarization) is applied over the dielectric layer. A via is formed over the gate of the sensing transistor by etching an opening into the planarized ILD and then filling the opening with copper or another suitable conductor. The metal layer is then patterned and applied at 508 over the via and the rest of the dielectric to form the source and drain areas of the charging transistor. At 510, the next layer of dielectric is applied over the second metal layer. The metal may first be planarized and protected with a nitride etch stop layer before the next layer of ILD is applied.

At 512, the dielectric is etched to open areas for an AOS channel and metal gate. In this operation, the ILD and nitride etch stop layer are removed to expose the metal lines

corresponding to the source and drain.

With the gate opening made at 514 a blanket AOS deposition is made using e.g. CVD so that the AOS is in contact with the source and drain of the charging transistor. For the charging transistor, an AOS with a low off state leakage, such as IGZO is chosen to reduce the refresh rate of the memory cell. The AOS deposition may be done using CVD (Chemical Vapor Deposition) or in any of a variety of other ways. Next at 516 a high K dielectric is applied using, for example, ALD (Atomic Layer Deposition) or any of a variety of other techniques. At 518 a fill metal is deposited to form the gate of the charging transistor. A damascene approach may be used. The deposit may be only on the bottom of the opening as shown in Figure 3 or also on the sidewalls of each previous layer as shown in Figure 4. In any case, the deposits are blanket layer deposition so that the AOS material is in contact with the source and the drain.

At 520 CMP is used again to planarize the CDN over the metal of the gate. A nitride etch stop deposition is performed over the gate metal at 522 then ILD is deposited to form the level of the next metal layer. The ILD is planarized and then the via to the metal gate is formed.

At 524 openings are etched for vias to the metal gate and to the lower metal layers for any other desired connections and at 526 these are filled with a conductor. Finally at 528 the next metal layer with a gate electrode and any other routing such as WBL are formed in the next metal layer. These operations may be performed simultaneously for thousands or millions of memory cells in the same layers at the same time to produce a memory array that is very close to the logic circuitry and which does not add to the area of the die, only the height. If the array is formed in metal layers that are otherwise required, then the height also is not increased.

At 530 after the metal layers and ILD have been formed with an embedded memory array and any other components, then the die is finished with routing layers, contact pads, solder balls and any other desired components. Additional operations may also be applied to the back side of the die, such as thinning, applying heat spreaders and other operations.

Figure 6 illustrates a computing device 11 in accordance with one implementation. The computing device 11 houses a board 2. The board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6. The processor 4 is physically and electrically coupled to the board 2. In some implementations the at least one communication chip 6 is also physically and electrically coupled to the board 2. In further implementations, the communication chip 6 is part of the processor 4.

Depending on its applications, computing device 11 may include other components that may or may not be physically and electrically coupled to the board 2. These other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e.g., ROM) 9, flash memory (not shown), a graphics processor 12, a digital signal processor (not shown), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown), digital versatile disk (DVD) (not shown), and so forth). These components may be connected to the system board 2, mounted to the system board, or combined with any of the other components.

The communication chip 6 enables wireless and/or wired communications for the transfer of data to and from the computing device 11. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 6 may implement any of a number of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet derivatives thereof, as well as any other wireless and wired protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 11 may include a plurality of communication chips 6. For instance, a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second

communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

In some implementations, the integrated circuit die of the processor, memory devices, communication devices, or other components are fabricated to include two transistor memory cells with an AOS as described herein. The described memory cells may be embedded as memory for other components in a CMOS or other logic processing die or a standalone memory array may be made on its own die. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

In various implementations, the computing device 11 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 11 may be any other electronic device that processes data including a wearable device. Embodiments may be implemented as a part of one or more memory chips, controllers, CPUs (Central Processing Unit), microchips or integrated circuits interconnected using a motherboard, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA).

References to "one embodiment", "an embodiment", "example embodiment", "various embodiments", etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.

In the following description and claims, the term "coupled" along with its derivatives, may be used. "Coupled" is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.

As used in the claims, unless otherwise specified, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common element, merely indicate that different instances of like elements are being referred to, and are not intended to imply that the elements so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.

The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications. Some embodiments pertain to a structure that includes a sensing transistor having a source coupled to a read bit line and a drain coupled to a read word line, a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor, and a gate electrode in a second metal layer coupled to the gate of the charging transistor.

Further embodiments include a third metal layer between the source of the charging transistor and the sensing transistor, wherein the sensing transistor is in silicon logic circuitry below the third metal layer, wherein the source of the charging transistor is coupled to the third metal layer through a via and wherein the sensing transistor gate is coupled to the third metal layer.

In further embodiments the metal oxide semiconductor of the charging transistor is selected as a low off state leakage material.

In further embodiments the metal oxide semiconductor of the charging transistor is an indium gallium zinc oxide.

Further embodiments include an interlayer dielectric between the first metal layer and a front side of a silicon substrate and wherein the gate of the sensing transistor is formed in silicon on the silicon substrate.

Further embodiments include a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.

Further embodiments include a conductive via over the charging transistor gate, wherein the gate of the charging transistor further comprises a dielectric over the metal oxide semiconductor and a metal over the dielectric, and wherein the gate electrode is coupled to the metal of the gate through the conductive via.

In further embodiments the first metal layer is on a semiconductor die over logic circuitry of the die, wherein the second metal layer is over the first metal layer.

In further embodiments the sensing transistor is in the logic circuitry of the die.

Further embodiments include a write bit line coupled to the first metal layer and a write word line in the second metal layer.

Some embodiments pertain to a method that includes patterning logic circuitry over a silicon substrate to form a sensing transistor in silicon of a silicon substrate, applying a first interlayer dielectric (ILD) over the logic circuitry, forming a via over the gate of the sensing transistor, patterning a first metal layer to form a source and a drain of a charging transistor over the gate of the sensing transistor wherein the source of the charging transistor is coupled to the via, applying a second ILD over the first metal layer, depositing a low off state leakage metal oxide semiconductor material in an opening in the second ILD as charging transistor gate channel, depositing a metal over the charging transistor gate channel as a gate, forming a second via over the charging transistor gate, and patterning a third metal layer with a gate electrode coupled to the second via.

In further embodiments the low off state leakage metal oxide semiconductor is an indium gallium zinc oxide.

Further embodiments include depositing a high K dielectric over the metal oxide semiconductor material before depositing the metal.

Further embodiments include etching the second ILD to form a trench for the charging transistor gate channel before depositing the metal oxide semiconductor material.

Some embodiments pertain to a computing system that includes a memory having instructions stored thereon, and a processor coupled to the memory to execute the instructions, the processor having silicon logic circuitry formed on a silicon substrate and embedded memory, the embedded memory having a sensing transistor in the silicon logic circuitry having a source coupled to a read bit line and a drain coupled to a read word line, a charging transistor having a source and a drain in a first metal layer above the silicon logic circuitry and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.

Further embodiments include a third metal layer between the source of the charging transistor and the sensing transistor, wherein the sensing transistor is in the silicon logic circuitry below the third metal layer, wherein the source of the charging transistor is coupled to the third metal layer through a via and wherein the sensing transistor gate is coupled to the third metal layer, the via forming a storage node of the charging transistor.

In further embodiments the embedded memory comprises a plurality of sensing transistors and charging transistors in an array coupled to a shared write bit line and a shared write word line.

Claims

1. A memory cell comprising:

a sensing transistor having a source coupled to a read bit line and a drain coupled to a read word line;

a charging transistor having a source and a drain in a first metal layer and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor; and

a gate electrode in a second metal layer coupled to the gate of the charging transistor.

2. The memory cell of Claim 1, further comprising a third metal layer between the source of the charging transistor and the sensing transistor, wherein the sensing transistor is in silicon logic circuitry below the third metal layer, wherein the source of the charging transistor is coupled to the third metal layer through a via and wherein the sensing transistor gate is coupled to the third metal layer.

3. The memory cell of Claim 1 or 2, wherein the metal oxide semiconductor of the charging transistor is selected as a low off state leakage material.

4. The memory cell of Claim 1, 2, or 3, wherein the metal oxide semiconductor of the charging transistor is an indium gallium zinc oxide, an indium gallium oxide, or an indium tin oxide.

5. The memory cell of any one or more of the above claims, further comprising an interlayer dielectric between the first metal layer and a front side of a silicon substrate and wherein the gate of the sensing transistor is formed in silicon on the silicon substrate.

6. The memory cell of Claim 5, further comprising a conductive via through the interlayer dielectric coupled to the gate of the sensing transistor and to the source of the charging transistor, the via forming a storage node of the charging transistor.

7. The memory cell of any one or more of the above claims, further comprising a conductive via over the charging transistor gate, wherein the gate of the charging transistor further comprises a dielectric over the metal oxide semiconductor and a metal over the dielectric, and wherein the gate electrode is coupled to the metal of the gate through the conductive via.

8. The memory cell of any one or more of the above claims, wherein the first metal layer is on a semiconductor die over logic circuitry of the die, wherein the second metal layer is over the first metal layer.

9. The memory cell of Claim 8, wherein the sensing transistor is in the logic circuitry of the die.

10. The memory cell of Claim 1, further comprising a write bit line coupled to the first metal layer and a write word line in the second metal layer.

11. A method comprising:

patterning logic circuitry over a silicon substrate to form a sensing transistor in silicon of a silicon substrate;

applying a first interlay er dielectric (ILD) over the logic circuitry;

forming a via over the gate of the sensing transistor;

patterning a first metal layer to form a source and a drain of a charging transistor over the gate of the sensing transistor wherein the source of the charging transistor is coupled to the via; applying a second ILD over the first metal layer;

depositing a low off state leakage metal oxide semiconductor material in an opening in the second ILD as charging transistor gate channel;

depositing a metal over the charging transistor gate channel as a gate;

forming a second via over the charging transistor gate; and

patterning a third metal layer with a gate electrode coupled to the second via.

12. The method of Claim 11, wherein the low off state leakage metal oxide semiconductor is an indium gallium zinc oxide.

13. The method of Claim 11 or 12, further comprising depositing a high K dielectric over the metal oxide semiconductor material before depositing the metal.

14. The method of any one or more claims 11-13, further comprising etching the second ILD to form a trench for the charging transistor gate channel before depositing the metal oxide semiconductor material.

15. A computing system comprising:

a memory having instructions stored thereon; and

a processor coupled to the memory to execute the instructions, the processor having silicon logic circuitry formed on a silicon substrate and embedded memory, the embedded memory having a sensing transistor in the silicon logic circuitry having a source coupled to a read bit line and a drain coupled to a read word line, a charging transistor having a source and a drain in a first metal layer above the silicon logic circuitry and a gate between the source and the drain, wherein the gate has a channel between and coupled to the source and the drain, the channel formed of a metal oxide semiconductor, wherein the source of the charging transistor is coupled to a gate of the sensing transistor, and a gate electrode in a third metal layer coupled to the gate of the charging transistor.

16. The computing system of Claim 15, further comprising a third metal layer between the source of the charging transistor and the sensing transistor, wherein the sensing transistor is in the silicon logic circuitry below the third metal layer, wherein the source of the charging transistor is coupled to the third metal layer through a via and wherein the sensing transistor gate is coupled to the third metal layer, the via forming a storage node of the charging transistor.

17. The computing system of Claim 15 or 16, wherein the metal oxide semiconductor of the charging transistor is selected as a low off state leakage material.

18. The computing system of any one or more of claims 15-17, wherein the metal oxide semiconductor of the charging transistor is an indium gallium zinc oxide.

19. The computing system of any one or more of claims 15-18, further comprising a write bit line coupled to the first metal layer and a write word line in the second metal layer.

20. The computing system of Claim 19, wherein the embedded memory comprises a plurality of sensing transistors and charging transistors in an array coupled to a shared write bit line and a shared write word line.