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WO2014112305A1 - Method for forming through-via and method for manufacturing electronic device - Google Patents

Method for forming through-via and method for manufacturing electronic device Download PDF

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Publication number
WO2014112305A1
WO2014112305A1 PCT/JP2013/084637 JP2013084637W WO2014112305A1 WO 2014112305 A1 WO2014112305 A1 WO 2014112305A1 JP 2013084637 W JP2013084637 W JP 2013084637W WO 2014112305 A1 WO2014112305 A1 WO 2014112305A1
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WIPO (PCT)
Prior art keywords
film
forming
insulating film
substrate
polymer film
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PCT/JP2013/084637
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French (fr)
Japanese (ja)
Inventor
俊彦 城
吉平 杉田
橋本　浩幸
原田　宗生
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東京エレクトロン株式会社
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Publication of WO2014112305A1 publication Critical patent/WO2014112305A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for forming a penetrating via and a method for manufacturing an electronic product.
  • the vertical wiring technology includes wire wiring using fine metal wires such as wire bonding, but one of the most practical means is through-silicon via (TSV).
  • TSV through-silicon via
  • the through-silicon via is to form a vertical wiring by opening a hole penetrating the silicon LSI chip and embedding a conductor therein.
  • Such a through silicon via has an advantage that the mounting area can be made more compact as compared with a method in which a fine metal wire is externally attached to the outside of the LSI chip.
  • the vertical wiring formed inside the LSI chip is generally referred to as “through via”.
  • An example of a method for forming a through via is described in Patent Document 1, for example.
  • Copper is regarded as a promising conductor used for through-vias because of its good electrical conductivity.
  • copper has the property of easily diffusing into an interlayer insulating film made of, for example, silicon oxide and destroying the insulating properties of the interlayer insulating film. For this reason, in the LSI chip, a structure is adopted in which copper is surrounded by a barrier film and copper is confined in the barrier film.
  • the through via it is necessary to grind / polish the silicon wafer from the back surface to expose the conductor used for the through via to the outside, and to take out the conductor in a convex shape outside the LSI chip.
  • the back surface of the silicon wafer and the periphery of the surface of the convex conductor are covered with an insulating film to electrically insulate the convex conductors from each other.
  • the insulating film and the convex conductor are polished, and the convex conductor is exposed to the outside from the surface of the insulating film. If copper is used for the conductor, the polishing of copper proceeds from the time when copper is exposed to the outside.
  • the silicon wafer on which the insulating film is formed is ground / polished for taking out the conductor, and the thickness is very thin.
  • the silicon wafer is warped although it is minute due to the compressive stress or tensile stress of the insulating film. Even though the warpage is minute, it is difficult to process the warped silicon wafer with high accuracy.
  • a dense and hard film such as a silicon oxide film or a silicon nitride film is used as the insulating film, a large stress is applied to the silicon wafer. For this reason, the situation where a silicon wafer warps appears more notably.
  • the present invention even when copper is used as a conductor, it is possible to suppress the diffusion of copper and to form a through via that can suppress the warpage of the substrate even when the thickness of the substrate is reduced.
  • the present invention provides a method and a method for manufacturing an electronic product using the method of forming a through via.
  • a method for forming a through via comprising: (1) a step of forming a hole-shaped trench from the surface of a substrate toward the substrate; and (2) a first in the trench. (3) a step of forming a conductive film to be a through via in the trench in which the first insulating film is formed, and (4) a surface opposite to the surface of the substrate.
  • An electronic product manufacturing method is an electronic product manufacturing method provided with a through via, wherein the through via is formed according to the through via forming method according to the first aspect. To do.
  • the present invention even if copper is used as the conductor, diffusion of copper can be suppressed, and even when the thickness of the substrate is reduced, the through via that can suppress the warpage of the substrate. And a method of manufacturing an electronic product using the through via formation method.
  • Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention The figure which shows the relationship between the depth of a backside polymer film, and Cu density
  • Method for forming through vias 1A to 1J are sectional views showing an example of a method for forming a through via according to an embodiment of the present invention for each main process.
  • a semiconductor device such as a transistor is formed in a semiconductor substrate (wafer), for example, a silicon substrate 1.
  • a semiconductor substrate wafer
  • a semiconductor substrate wafer
  • details of the semiconductor device are omitted, but a region 2 in FIG. 1A is a device formation region in which the semiconductor device is formed.
  • a hole-shaped trench 3 is formed on the silicon substrate 1 from the device formation region 2 side of the silicon substrate 1, for example.
  • the trench 3 becomes a through hole into which a through via is embedded later.
  • a liner polymer film 4 is formed on the device formation region 2 in which the trench 3 is formed.
  • an insulating polymer film is used as the liner polymer film 4.
  • the liner polymer film 4 becomes an insulating film that insulates the through via from the silicon substrate 1.
  • the liner polymer film 4 can be formed by using, for example, a vapor deposition polymerization method.
  • the liner polymer film 4 using the vapor deposition polymerization method is excellent in film formability and is one of effective means for forming a film in a deep trench like the trench 3.
  • An example of the liner polymer film 4 is a polyimide film.
  • the polyimide film using the vapor deposition polymerization method includes, for example, pyromellitic dianhydride (PMDA: C 10 H 2 O 6 ) as the first monomer and 4,4′-oxydianiline (ODA: ODA: second monomer).
  • PMDA pyromellitic dianhydride
  • ODA 4,4′-oxydianiline
  • C 12 H 12 N 2 O can be formed by supplying those vaporized respectively into the processing chamber of the film formation apparatus.
  • a seed and barrier film 5 is formed on the liner polymer film 4.
  • An example of the seed and barrier film 5 is a tantalum (Ta) film.
  • the conductor film 6 is formed on the seed / barrier film 5 by, for example, a plating method using the seed / barrier film 5 as a seed layer for plating.
  • An example of the conductor film 6 is a copper (Cu) film, and this copper film functions as a through via.
  • the conductor film 6, the seed / barrier film 5, and the liner polymer film 4 are subjected to, for example, chemical mechanical polishing (CMP), and the conductor film 6, the seed / barrier film 5.
  • CMP chemical mechanical polishing
  • the liner polymer film 4 is embedded in the trench 3.
  • the liner polymer film 4 is polished in this example.
  • the liner polymer film 4 may be left on the device formation region 2 without being polished.
  • an internal wiring layer (Interconnect layers (BEOL)) 7 is formed on the device formation region 2.
  • a plurality of internal wirings are formed in the horizontal direction and the vertical direction for connecting the semiconductor devices in accordance with the intended function. In the present specification, details of the internal wiring formed in the internal wiring layer 7 are omitted.
  • a front bump electrode 8 is formed on the internal wiring layer 7.
  • the front bump electrode 8 is electrically connected to the internal via formed in the internal wiring layer 7 and the through via 6V via the internal wiring, and functions as one of the external terminals of the LSI chip.
  • the silicon substrate 1 is inverted, for example.
  • the silicon substrate 1 is ground / polished from the back surface to reduce the original thickness T1 of the silicon substrate 1 to the thickness T2.
  • the through-via 6V wrapped with the liner polymer film 4 is projected from the back surface of the silicon substrate 1 in a convex shape.
  • an etchant that is easy to etch the silicon substrate 1 and difficult to etch the liner polymer film 4 may be dry or wet etched. In this case, the through via 6V wrapped with the liner polymer film 4 can be protruded greatly from the back surface of the silicon substrate 1 in a convex shape.
  • the liner polymer film 4 has excellent chemical resistance. For this reason, it is possible to increase the etching selectivity between the silicon substrate 1 and the liner polymer film 4. For this reason, the process of reducing the thickness of the silicon substrate 1 is completed more quickly than when, for example, a silicon oxide film or a silicon nitride film is used instead of the liner polymer film 4. You can also. This is a useful advantage for improving throughput.
  • the through via 6V when the thickness of the silicon substrate 1 is reduced, the through via 6V is wrapped with the liner polymer film 4 and the seed / barrier film 5 as shown in FIG. 1G. Yes. For this reason, even when copper is used for the through via 6V, the copper is not exposed to the outside. Therefore, an advantage that diffusion of copper onto the back surface of the silicon substrate 1 can be suppressed can be obtained.
  • a backside polymer film 9 is formed on the back surface of the silicon substrate 1 and on the liner polymer film 4 protruding from the back surface.
  • an insulating polymer film is used similarly to the liner polymer film 4.
  • the backside polymer film 9 becomes an insulating film that insulates the silicon substrate 1 from the outside.
  • the backside polymer film 9 can be formed by using, for example, a vapor deposition polymerization method.
  • the material and the film formation method can be the same as the material and film formation method of the liner polymer film 4 described above.
  • the backside polymer film 9, the liner polymer film 4, the seed / barrier film 5 and the through via 6V are subjected to, for example, chemical mechanical polishing (CMP), and the through via 6V is formed. Expose to the outside.
  • CMP chemical mechanical polishing
  • a back bump electrode 10 is formed on the back side polymer film 9 and the through via 6V.
  • the back bump electrode 10 of the present embodiment is electrically connected to the through via 6V, for example.
  • the back bump electrode 10 functions as one of the external terminals of the LSI chip together with the front bump electrode 8.
  • the LSI chip 100 using the through via forming method according to the embodiment of the present invention is completed.
  • FIG. 2 is a diagram showing the relationship between the depth of the backside polymer film and the copper (Cu) concentration.
  • FIG. 2 shows the result of measuring the concentration of copper (isotope nuclide 63 Cu) in the backside polymer film 9 using secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • a sample simulating the through-via 6V formed in an actual LSI chip as shown in FIG. 3 was prepared, and a location along the line AA (backside height in the figure) of this sample was created. The portion of the molecular film 9) was measured.
  • sample creation method Here, a sample creation method will be described.
  • 4A to 4D are cross-sectional views showing a method for producing a sample.
  • a thermal oxide film 101 is formed on the surface of the silicon substrate 1.
  • a barrier layer 102 is formed on the thermal oxide film 101.
  • the barrier layer 102 is made of tantalum, for example.
  • a copper film 103 is formed on the barrier layer 102 by a sputtering method.
  • a photoresist is applied on the copper film 103 to form a photoresist film 104.
  • a hole-like hole 105 is formed in the photoresist film 104 by using a photolithography method.
  • the photoresist film 104 is removed.
  • a tantalum film is formed on the copper film 103 and the pseudo through-via 6VS.
  • This tantalum film becomes the barrier film 5S.
  • a polymer film is formed on the barrier film 5S.
  • This polymer film becomes the pseudo backside polymer film 9S.
  • the pseudo backside polymer film 9S is formed by vapor deposition polymerization.
  • pyromellitic dianhydride (PMDA: C 10 H 2 O 6 ) is used as the first monomer, and 4,4 is used as the second monomer.
  • PMDA pyromellitic dianhydride
  • ODA 4′-oxydianiline
  • the formed pseudo backside polymer film 9S is a polyimide film.
  • the pseudo backside polymer film 9S, the barrier film 5S, and the pseudo through-via 6VS are chemically mechanically polished (CMP) to expose the pseudo through-via 6VS to the outside.
  • CMP chemically mechanically polished
  • the concentration of copper in the pseudo backside polymer film 9S having a film thickness of about 4 ⁇ m is 10 16 atoms / cm 3 or less, and copper is contained in the pseudo backside polymer film 9S. It turns out that there is hardly any. This indicates that copper does not spread on the surface of the pseudo backside polymer film 9S even when the pseudo backside polymer film 9S is chemically mechanically polished. That is, the so-called “copper drag phenomenon” can be suppressed by forming the pseudo backside polymer film 9S by the polymer film formed by using the vapor deposition polymerization method.
  • the influence of copper diffusion for example, the concern that the insulating property of the backside insulating film (backside polymer film 9) is lowered is eliminated. can do.
  • the presence of a little copper is recognized near the surface of the pseudo backside polymer film 9S, for example, to a depth of about 1 ⁇ m. This can be concluded as follows.
  • the primary ions are struck against the sample, and the secondary ions are knocked out from the sample.
  • the component contained in the sample is examined by analyzing the mass of the secondary ions.
  • a gold coating 106 for allowing the charged particles e to escape is formed on the surface of the sample in order to prevent the sample from being charged up.
  • the gold coating 106 is formed only for the purpose of escaping the charged particles e, and the purity is not high.
  • the gold coating 106 contains impurities such as copper.
  • copper contained in the gold coating 106 is knocked on by primary ions, copper is pushed into the vicinity of the surface of the pseudo backside polymer film 9S. Copper derived from impurities in the gold film 106 was observed near the surface of the pseudo backside polymer film 9S, for example, to a depth of about 1 ⁇ m.
  • a back side polymer film 9 formed by vapor deposition polymerization is used as the back side insulating film.
  • a backside polymer film 9 can reduce stress on the silicon substrate 1 as compared with, for example, a silicon oxide film or a silicon nitride film. For this reason, even if the thickness of the silicon substrate 1 is reduced, the situation where the silicon substrate 1 is warped can be improved. That is, the backside polymer film 9 formed on the backside insulating film by using the vapor deposition polymerization method as compared with, for example, an LSI chip using a silicon oxide film or a silicon nitride film as the backside insulating film. The LSI chip 100 using the can be made thinner.
  • the through via forming method according to the embodiment of the present invention even when the thickness of the silicon substrate 1 is reduced, the warp of the silicon substrate 1 can be suppressed. be able to.
  • the thickness of the LSI chip 100 can be made thinner. Therefore, for example, as shown in the perspective view of FIG. 6, when the LSI chip 100 is three-dimensionally mounted, the entire thickness T can be further reduced. Such an advantage is one of the advantages useful for miniaturization of LSI products mounted three-dimensionally.
  • the through via forming method according to the above embodiment is also useful for application to a manufacturing method of an electronic product, for example, a semiconductor integrated circuit device (LSI chip).
  • LSI chip semiconductor integrated circuit device
  • FIG. 7 shows a schematic cross-sectional view of a terminal rearrangement board 200 as an example of an interposer.
  • the terminal rearrangement board 200 shown in FIG. 7 converts, for example, the arrangement pitch P-LSI of the LSI chip side terminals 8a into the arrangement pitch P-CKT of the circuit board side terminals 10a.
  • the arrangement pitch P-CKT in the terminal rearrangement substrate 200 is wider than the arrangement pitch P-LSI.
  • the through via forming method according to the above-described embodiment can be effectively applied to the formation of the through via 6V that connects the front side and the back side of the terminal rearrangement substrate 200 as described above.
  • the through via is formed in the silicon substrate (silicon wafer), but the substrate is not limited to silicon. If it is a board
  • SYMBOLS 1 Silicon substrate, 2 ... Device formation area, 3 ... Trench, 4 ... Liner polymer film, 5 ... Seed and barrier film, 6 ... Conductor film, 6V ... Through-via, 7 ... Internal wiring layer, 8 ... Front bump Electrode, 9 ... backside polymer film, 10 ... back bump electrode, 100 ... LSI chip, 200 ... interposer (terminal rearrangement substrate).

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Abstract

The present invention discloses a method for forming a through-via. The through-via is formed by a method comprising: a step of forming a hole-like trench (3) from the surface of a substrate (1) toward the inside of the substrate (1); a step of forming a first insulating film (4) in the trench (3); a step of forming a conductor film (6V) which will form the through-via in the trench (3) having the first insulating film (4) formed therein; a step of causing the rear surface of the substrate (1) to be withdrawn such that the first insulating film (4) covering the conductor film (6V) inside protrudes from the rear surface of the substrate (1); a step of forming a second insulating film (9) on the rear surface of the substrate (1) and on the first insulating film (4) protruding from the rear surface of the substrate (1); and a step of causing the second insulating film (9), the first insulating film (4), and the conductor film (6V) to be withdrawn such that the conductor film (6V) is exposed to the outside. The second insulating film (9) is formed with a polymer film.

Description

貫通ヴィアの形成方法および電子製品の製造方法Method for forming through via and method for manufacturing electronic product
　この発明は、貫通ヴィアの形成方法および電子製品の製造方法に関する。 The present invention relates to a method for forming a penetrating via and a method for manufacturing an electronic product.
　電子機器の小型化、高速化、多機能化などの高性能化は、ＬＳＩ製造プロセスの微細化によってもたらされてきた。これまで、ＬＳＩチップの微細化は、シリコンウエハ平面での微細化が中心であった。しかし、平面だけでの微細化には、技術的な限界が見えてきている。 High performance such as miniaturization, high speed, and multi-functionality of electronic devices has been brought about by miniaturization of LSI manufacturing processes. Until now, LSI chip miniaturization has been centered on the silicon wafer plane. However, there is a technical limit to miniaturization using only a plane.
　それを打開する技術の一つとして注目されているのが、ＬＳＩチップの三次元実装である。三次元実装を実現するための根幹的技術の一つが、上下に積層されたＬＳＩチップどうしを接続する垂直配線技術である。 [3] One of the technologies to overcome this is the three-dimensional mounting of LSI chips. One of the fundamental technologies for realizing three-dimensional mounting is a vertical wiring technology for connecting LSI chips stacked one above the other.
　垂直配線技術には、ワイヤボンディングなどに代表される金属細線を使った有線配線といった手段があるが、中でも実用性が高い手段の一つがシリコン貫通ヴィア(Through-silicon　via：ＴＳＶ)である。シリコン貫通ヴィアは、シリコン製ＬＳＩチップ中に、このチップを貫通する孔を開け、ここに導電体を埋め込むことで垂直配線を形成するものである。このようなシリコン貫通ヴィアは、ＬＳＩチップの外部に金属細線を外付けする方式に比較して、実装面積をよりコンパクトできる、という利点がある。以下、本明細書においては、ＬＳＩチップの内部に形成される垂直配線を総じて“貫通ヴィア”と呼ぶ。貫通ヴィアの形成方法の例としては、例えば、特許文献１に記載されている。 The vertical wiring technology includes wire wiring using fine metal wires such as wire bonding, but one of the most practical means is through-silicon via (TSV). The through-silicon via is to form a vertical wiring by opening a hole penetrating the silicon LSI chip and embedding a conductor therein. Such a through silicon via has an advantage that the mounting area can be made more compact as compared with a method in which a fine metal wire is externally attached to the outside of the LSI chip. Hereinafter, in this specification, the vertical wiring formed inside the LSI chip is generally referred to as “through via”. An example of a method for forming a through via is described in Patent Document 1, for example.
特開２０１１－６６３８３号公報JP 2011-66383 A
　貫通ヴィアに用いられる導電体は、電気伝導率の良さから銅が有力視されている。しかし、銅は、例えば、シリコン酸化物などからなる層間絶縁膜中に容易に拡散し、層間絶縁膜の絶縁性を破壊する、という性質を持つ。このため、ＬＳＩチップの内部においては、銅の周囲をバリア膜によって取り囲み、銅をバリア膜中に閉じ込めてしまう構造が採用されている。 Copper is regarded as a promising conductor used for through-vias because of its good electrical conductivity. However, copper has the property of easily diffusing into an interlayer insulating film made of, for example, silicon oxide and destroying the insulating properties of the interlayer insulating film. For this reason, in the LSI chip, a structure is adopted in which copper is surrounded by a barrier film and copper is confined in the barrier film.
　しかし、貫通ヴィアは、シリコンウエハを裏面から研削／研磨して貫通ヴィアに用いられた導電体を外部に露出させ、導電体をＬＳＩチップの外部に凸状に取り出す必要がある。導電体を凸状に取り出した後、シリコンウエハの裏面上、および凸状の導電体の表面周囲を絶縁膜で被覆し、凸状の導電体どうしを電気的に絶縁する。この後、絶縁膜、および凸状の導電体を研磨し、凸状の導電体を絶縁膜表面から外部に露出させる。もし、導電体に銅が用いられていた場合には、銅が外部に露出した時点から銅の研磨が進む。このため、絶縁膜の表面に、例えば、研磨に起因したマイクロスクラッチなどが発生してしまうと、このマイクロスクラッチに沿って銅微粒子が絶縁膜の表面上に拡がってしまうことがある。いわゆる“銅の引き摺り現象”である。このため、銅の拡散による影響、例えば、絶縁膜の絶縁性の低下等が懸念される。 However, in the through via, it is necessary to grind / polish the silicon wafer from the back surface to expose the conductor used for the through via to the outside, and to take out the conductor in a convex shape outside the LSI chip. After the conductor is taken out in a convex shape, the back surface of the silicon wafer and the periphery of the surface of the convex conductor are covered with an insulating film to electrically insulate the convex conductors from each other. Thereafter, the insulating film and the convex conductor are polished, and the convex conductor is exposed to the outside from the surface of the insulating film. If copper is used for the conductor, the polishing of copper proceeds from the time when copper is exposed to the outside. For this reason, for example, if micro scratches due to polishing occur on the surface of the insulating film, the copper fine particles may spread on the surface of the insulating film along the micro scratches. This is the so-called “copper drag phenomenon”. For this reason, there is a concern about the influence due to the diffusion of copper, for example, the deterioration of the insulating property of the insulating film.
　さらに、上記絶縁膜を形成する工程であるが、絶縁膜を形成するシリコンウエハは、導電体の取り出しのために研削／研磨されており、肉厚が非常に薄くなっている。肉厚が非常に薄いシリコンウエハ上に絶縁膜を成膜すると、この絶縁膜が持つ圧縮ストレスもしくは引張ストレスによってシリコンウエハが微小ながらも反ってしまう。微小な反りであるとはいえ、反ったシリコンウエハに対しては、以後、精度の高い加工を施すことは困難である。特に、上記絶縁膜に、シリコン酸化物膜やシリコン窒化物膜等の緻密で硬い膜を用いた場合には、大きなストレスがシリコンウエハに対して及ぼされる。このため、シリコンウエハが反る事情が、より顕著に現れる。 Further, in the step of forming the insulating film, the silicon wafer on which the insulating film is formed is ground / polished for taking out the conductor, and the thickness is very thin. When an insulating film is formed on a silicon wafer having a very thin thickness, the silicon wafer is warped although it is minute due to the compressive stress or tensile stress of the insulating film. Even though the warpage is minute, it is difficult to process the warped silicon wafer with high accuracy. In particular, when a dense and hard film such as a silicon oxide film or a silicon nitride film is used as the insulating film, a large stress is applied to the silicon wafer. For this reason, the situation where a silicon wafer warps appears more notably.
　この発明は、導電体に銅を使用した場合でも、銅の拡散を抑制することができ、かつ、基板の肉厚が薄くなっても、基板の反りを抑制することが可能な貫通ヴィアの形成方法、およびその貫通ヴィアの形成方法を利用した電子製品の製造方法を提供する。 In the present invention, even when copper is used as a conductor, it is possible to suppress the diffusion of copper and to form a through via that can suppress the warpage of the substrate even when the thickness of the substrate is reduced. The present invention provides a method and a method for manufacturing an electronic product using the method of forming a through via.
　この発明の第１の態様に係る貫通ヴィアの形成方法は、（１）基板の表面から、前記基板内に向かってホール状のトレンチを形成する工程と、（２）前記トレンチ内に、第１の絶縁膜を形成する工程と、（３）前記第１の絶縁膜が形成されたトレンチ内に、貫通ヴィアとなる導電体膜を形成する工程と、（４）前記基板の表面に相対した、前記基板の裏面を後退させ、前記基板の裏面から、内側に前記導電体膜を包んでいる前記第１の絶縁膜を突出させる工程と、（５）前記基板の裏面上、および前記基板の裏面から突出された前記第１の絶縁膜上に、第２の絶縁膜を形成する工程と、（６）前記第２の絶縁膜、前記第１の絶縁膜、および前記導電体膜を後退させ、前記導電体膜を外部に露出させる工程と、を具備し、前記第２の絶縁膜を、高分子膜にて形成する。 According to a first aspect of the present invention, there is provided a method for forming a through via, comprising: (1) a step of forming a hole-shaped trench from the surface of a substrate toward the substrate; and (2) a first in the trench. (3) a step of forming a conductive film to be a through via in the trench in which the first insulating film is formed, and (4) a surface opposite to the surface of the substrate. Retreating the back surface of the substrate and projecting the first insulating film enclosing the conductor film from the back surface of the substrate, (5) on the back surface of the substrate, and on the back surface of the substrate A step of forming a second insulating film on the first insulating film projecting from (6) retreating the second insulating film, the first insulating film, and the conductor film; Exposing the conductive film to the outside, and the second insulating film It is formed by a polymer film.
　この発明の第２の態様に係る電子製品の製造方法は、貫通ヴィアを備えた電子製品の製造方法であって、前記貫通ヴィアを、上記第１の態様に係る貫通ヴィアの形成方法にしたがって形成する。 An electronic product manufacturing method according to a second aspect of the present invention is an electronic product manufacturing method provided with a through via, wherein the through via is formed according to the through via forming method according to the first aspect. To do.
　この発明によれば、導電体に銅を使用しても、銅の拡散を抑制することができ、かつ、基板の肉厚が薄くなっても、基板の反りを抑制することが可能な貫通ヴィアの形成方法、およびその貫通ヴィアの形成方法を利用した電子製品の製造方法を提供できる。 According to the present invention, even if copper is used as the conductor, diffusion of copper can be suppressed, and even when the thickness of the substrate is reduced, the through via that can suppress the warpage of the substrate. And a method of manufacturing an electronic product using the through via formation method.
この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法の一例を示す断面図Sectional drawing which shows an example of the formation method of the penetration via concerning one embodiment of this invention バックサイド高分子膜の深さとＣｕ濃度との関係を示す図The figure which shows the relationship between the depth of a backside polymer film, and Cu density | concentration 測定に使用したサンプルの断面図Cross section of sample used for measurement サンプルの作成方法を示す断面図Sectional view showing sample preparation method サンプルの作成方法を示す断面図Sectional view showing sample preparation method サンプルの作成方法を示す断面図Sectional view showing sample preparation method サンプルの作成方法を示す断面図Sectional view showing sample preparation method ノックオン現象を示す断面図Cross-sectional view showing knock-on phenomenon この発明の一実施形態に係る貫通ヴィアの形成方法から得られる利点の一例を示す斜視図The perspective view which shows an example of the advantage acquired from the formation method of the penetration via concerning one embodiment of this invention この発明の一実施形態に係る貫通ヴィアの形成方法を用いて形成されたインターポーザの一例を概略的に示す断面図Sectional drawing which shows schematically an example of the interposer formed using the formation method of the penetration via concerning one embodiment of this invention
　以下、この発明の一実施形態を、図面を参照して説明する。なお、全図にわたり、共通の部分には共通の参照符号を付す。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that common parts are denoted by common reference numerals throughout the drawings.
　　（貫通ヴィアの形成方法）
　図１Ａ～図１Ｊは、この発明の一実施形態に係る貫通ヴィアの形成方法の一例を主要な工程毎に示す断面図である。 (Method for forming through vias)
1A to 1J are sectional views showing an example of a method for forming a through via according to an embodiment of the present invention for each main process.
　なお、貫通ヴィアの形成方法には、大きく下記の３つの手法がある。
　　(１)　貫通ヴィアを、デバイスを形成する前に形成する(Via-First)
　　(２)　貫通ヴィアを、デバイスを形成している途中に形成する(Via-Middle)
　　(３)　貫通ヴィアを、デバイスを形成した後に形成する(Via-Last)
　この発明の一実施形態は、上記(１)～(３)のいずれの手法にも適用することが可能であるが、本一実施形態においては、上記(３)の手法に基づいた例を説明することにする。 In addition, there are the following three methods for forming through-vias.
(1) Forming a through-via before forming a device (Via-First)
(2) Forming a through-via in the middle of forming a device (Via-Middle)
(3) Forming through vias after forming the device (Via-Last)
One embodiment of the present invention can be applied to any of the above methods (1) to (3), but in this embodiment, an example based on the method (3) is described. I will do it.
　まず、図１Ａに示すように、半導体基板(ウエハ)、例えば、シリコン基板１内に、トランジスタ等の半導体デバイスを形成する。本明細書においては、半導体デバイスの詳細については省略するが、図１Ａ中の領域(Devices)２が、半導体デバイスが形成されたデバイス形成領域である。 First, as shown in FIG. 1A, a semiconductor device such as a transistor is formed in a semiconductor substrate (wafer), for example, a silicon substrate 1. In the present specification, details of the semiconductor device are omitted, but a region 2 in FIG. 1A is a device formation region in which the semiconductor device is formed.
　次に、図１Ｂに示すように、例えば、シリコン基板１のデバイス形成領域２側から、シリコン基板１に対して、例えば、ホール状のトレンチ３を形成する。トレンチ３は、後に貫通ヴィアが埋め込まれる貫通孔となる。 Next, as shown in FIG. 1B, for example, a hole-shaped trench 3 is formed on the silicon substrate 1 from the device formation region 2 side of the silicon substrate 1, for example. The trench 3 becomes a through hole into which a through via is embedded later.
　次に、図１Ｃに示すように、トレンチ３が形成されたデバイス形成領域２上に、ライナー高分子膜４を形成する。ライナー高分子膜４には、絶縁性の高分子膜が用いられる。これによって、ライナー高分子膜４は、貫通ヴィアとシリコン基板１とを絶縁する絶縁膜となる。ライナー高分子膜４は、例えば、蒸着重合法を用いて形成することができる。なお、蒸着重合法を用いたライナー高分子膜４は成膜性に優れており、トレンチ３のように深いトレンチ内への成膜に、有効な手段の一つである。ライナー高分子膜４の一例は、ポリイミド膜である。蒸着重合法を用いたポリイミド膜は、例えば、第１のモノマーとしてピロメリット酸二無水物（ＰＭＤＡ：Ｃ１０Ｈ２Ｏ６）、第２のモノマーとして４，４´－オキシジアニリン（ＯＤＡ：Ｃ１２Ｈ１２Ｎ２Ｏ）を用い、これらをそれぞれ気化させたものを成膜装置の処理室内に供給することで形成することができる。 Next, as shown in FIG. 1C, a liner polymer film 4 is formed on the device formation region 2 in which the trench 3 is formed. As the liner polymer film 4, an insulating polymer film is used. Thus, the liner polymer film 4 becomes an insulating film that insulates the through via from the silicon substrate 1. The liner polymer film 4 can be formed by using, for example, a vapor deposition polymerization method. The liner polymer film 4 using the vapor deposition polymerization method is excellent in film formability and is one of effective means for forming a film in a deep trench like the trench 3. An example of the liner polymer film 4 is a polyimide film. The polyimide film using the vapor deposition polymerization method includes, for example, pyromellitic dianhydride (PMDA: C 10 H 2 O 6 ) as the first monomer and 4,4′-oxydianiline (ODA: ODA: second monomer). C 12 H 12 N 2 O) can be formed by supplying those vaporized respectively into the processing chamber of the film formation apparatus.
　次に、図１Ｄに示すように、ライナー高分子膜４上に、シード兼バリア膜５を形成する。シード兼バリア膜５の一例は、タンタル（Ｔａ）膜である。次いで、シード兼バリア膜５上に、例えば、シード兼バリア膜５をめっきのシード層として利用しためっき法により、導電体膜６を形成する。導電体膜６の一例は、銅（Ｃｕ）膜であり、この銅膜が貫通ヴィアとして機能することになる。 Next, as shown in FIG. 1D, a seed and barrier film 5 is formed on the liner polymer film 4. An example of the seed and barrier film 5 is a tantalum (Ta) film. Next, the conductor film 6 is formed on the seed / barrier film 5 by, for example, a plating method using the seed / barrier film 5 as a seed layer for plating. An example of the conductor film 6 is a copper (Cu) film, and this copper film functions as a through via.
　次に、図１Ｅに示すように、導電体膜６、シード兼バリア膜５、およびライナー高分子膜４を、例えば、化学的機械研磨（ＣＭＰ）し、導電体膜６、シード兼バリア膜５、およびライナー高分子膜４を、トレンチ３の内部に埋め込む。これにより、導電体膜６はトレンチ３ごとに分離され、貫通ヴィア６Ｖとなる。なお、ライナー高分子膜４については、本例では研磨してしまう例を示しているが、ライナー高分子膜４を研磨せず、デバイス形成領域２上に残すようにしてもよい。次いで、デバイス形成領域２上に、内部配線層(Interconnect　layers(BEOL))７を形成する。内部配線層７中には、半導体デバイスどうしを目的とする機能に合わせて接続する水平方向、および垂直方向に複数の内部配線が形成される。本明細書においては、内部配線層７中に形成された内部配線の詳細については省略する。 Next, as shown in FIG. 1E, the conductor film 6, the seed / barrier film 5, and the liner polymer film 4 are subjected to, for example, chemical mechanical polishing (CMP), and the conductor film 6, the seed / barrier film 5. The liner polymer film 4 is embedded in the trench 3. As a result, the conductor film 6 is separated for each trench 3 and becomes a through via 6V. The liner polymer film 4 is polished in this example. However, the liner polymer film 4 may be left on the device formation region 2 without being polished. Next, an internal wiring layer (Interconnect layers (BEOL)) 7 is formed on the device formation region 2. In the internal wiring layer 7, a plurality of internal wirings are formed in the horizontal direction and the vertical direction for connecting the semiconductor devices in accordance with the intended function. In the present specification, details of the internal wiring formed in the internal wiring layer 7 are omitted.
　次に、図１Ｆに示すように、内部配線層７上にフロントバンプ電極８を形成する。フロントバンプ電極８は、内部配線層７中に形成された内部配線や、内部配線を介して貫通ヴィア６Ｖに電気的に接続され、ＬＳＩチップの外部端子の一つとして機能する。 Next, as shown in FIG. 1F, a front bump electrode 8 is formed on the internal wiring layer 7. The front bump electrode 8 is electrically connected to the internal via formed in the internal wiring layer 7 and the through via 6V via the internal wiring, and functions as one of the external terminals of the LSI chip.
　次に、図１Ｇに示すように、シリコン基板１を、例えば、反転させる。次いで、シリコン基板１を裏面から研削／研磨し、シリコン基板１の元来の肉厚Ｔ１を肉厚Ｔ２へと薄くする。これとともに、ライナー高分子膜４で包まれた貫通ヴィア６Ｖを、シリコン基板１の裏面から凸状に突出させる。貫通ヴィア６Ｖを突出させる際には、例えば、シリコン基板１をエッチングしやすく、ライナー高分子膜４をエッチングしにくいエッチャントを用いて、ドライ、もしくはウェットエッチングするようにしても良い。このようにすると、ライナー高分子膜４で包まれた貫通ヴィア６Ｖを、シリコン基板１の裏面から凸状に大きく突出させることも可能である。 Next, as shown in FIG. 1G, the silicon substrate 1 is inverted, for example. Next, the silicon substrate 1 is ground / polished from the back surface to reduce the original thickness T1 of the silicon substrate 1 to the thickness T2. At the same time, the through-via 6V wrapped with the liner polymer film 4 is projected from the back surface of the silicon substrate 1 in a convex shape. When projecting the through-via 6V, for example, an etchant that is easy to etch the silicon substrate 1 and difficult to etch the liner polymer film 4 may be dry or wet etched. In this case, the through via 6V wrapped with the liner polymer film 4 can be protruded greatly from the back surface of the silicon substrate 1 in a convex shape.
　また、ライナー高分子膜４には、耐薬品性に優れたものがある。このため、シリコン基板１とライナー高分子膜４との間で、エッチング選択比を大きくとることも可能である。このため、シリコン基板１の肉厚を薄くする工程を、例えば、ライナー高分子膜４の代わりに、シリコン酸化物膜やシリコン窒化物膜などを用いた場合に比較して、より速く完了させることもできる。これは、スループットの向上に有用な利点である。 Also, the liner polymer film 4 has excellent chemical resistance. For this reason, it is possible to increase the etching selectivity between the silicon substrate 1 and the liner polymer film 4. For this reason, the process of reducing the thickness of the silicon substrate 1 is completed more quickly than when, for example, a silicon oxide film or a silicon nitride film is used instead of the liner polymer film 4. You can also. This is a useful advantage for improving throughput.
　また、本一実施形態においては、シリコン基板１の肉厚を薄くする際、図１Ｇに示されているように、貫通ヴィア６Ｖがライナー高分子膜４とシード兼バリア膜５とで包まれている。このため、貫通ヴィア６Ｖに銅を使用していた場合においても、銅は外部に露出しない。よって、銅の、シリコン基板１の裏面上への拡散を抑制できる、という利点をも得ることができる。 In the present embodiment, when the thickness of the silicon substrate 1 is reduced, the through via 6V is wrapped with the liner polymer film 4 and the seed / barrier film 5 as shown in FIG. 1G. Yes. For this reason, even when copper is used for the through via 6V, the copper is not exposed to the outside. Therefore, an advantage that diffusion of copper onto the back surface of the silicon substrate 1 can be suppressed can be obtained.
　次に、図１Ｈに示すように、シリコン基板１の裏面上、およびこの裏面から突出したライナー高分子膜４上に、バックサイド高分子膜９を形成する。バックサイド高分子膜９は、ライナー高分子膜４と同様に、絶縁性の高分子膜が用いられる。これによって、バックサイド高分子膜９は、シリコン基板１を外部から絶縁する絶縁膜となる。バックサイド高分子膜９についても、ライナー高分子膜４と同様に、例えば、蒸着重合法を用いて形成することができる。また、その材料や、成膜方法についても、上述したライナー高分子膜４の材料や、成膜方法と同様のものを使うことができる。 Next, as shown in FIG. 1H, a backside polymer film 9 is formed on the back surface of the silicon substrate 1 and on the liner polymer film 4 protruding from the back surface. As the backside polymer film 9, an insulating polymer film is used similarly to the liner polymer film 4. Thus, the backside polymer film 9 becomes an insulating film that insulates the silicon substrate 1 from the outside. Similarly to the liner polymer film 4, the backside polymer film 9 can be formed by using, for example, a vapor deposition polymerization method. In addition, the material and the film formation method can be the same as the material and film formation method of the liner polymer film 4 described above.
　次に、図１Ｉに示すように、バックサイド高分子膜９、ライナー高分子膜４、シード兼バリア膜５、および貫通ヴィア６Ｖを、例えば、化学的機械研磨（ＣＭＰ）し、貫通ヴィア６Ｖを外部に露出させる。 Next, as shown in FIG. 1I, the backside polymer film 9, the liner polymer film 4, the seed / barrier film 5 and the through via 6V are subjected to, for example, chemical mechanical polishing (CMP), and the through via 6V is formed. Expose to the outside.
　次に、図１Ｊに示すように、バックサイド高分子膜９、および貫通ヴィア６Ｖ上に、バックバンプ電極１０を形成する。本一実施形態のバックバンプ電極１０は、例えば、貫通ヴィア６Ｖに電気的に接続される。これにより、バックバンプ電極１０は、フロントバンプ電極８とともに、ＬＳＩチップの外部端子の一つとして機能する。 Next, as shown in FIG. 1J, a back bump electrode 10 is formed on the back side polymer film 9 and the through via 6V. The back bump electrode 10 of the present embodiment is electrically connected to the through via 6V, for example. Thus, the back bump electrode 10 functions as one of the external terminals of the LSI chip together with the front bump electrode 8.
　以上のような工程を経ることにより、この発明の一実施形態に係る貫通ヴィアの形成方法を利用したＬＳＩチップ１００が完成する。 Through the above steps, the LSI chip 100 using the through via forming method according to the embodiment of the present invention is completed.
　　（バックサイド高分子膜に対する銅汚染の有無）
　本願発明者らは、バックサイド高分子膜９に対する銅汚染の有無を調べた。以下、バックサイド高分子膜９に対する銅汚染の有無について説明する。 (Presence or absence of copper contamination on the backside polymer film)
The inventors of the present application examined the presence or absence of copper contamination on the backside polymer film 9. Hereinafter, the presence or absence of copper contamination on the backside polymer film 9 will be described.
　図２は、バックサイド高分子膜の深さと銅（Ｃｕ）濃度との関係を示す図である。図２には、二次イオン質量分析（ＳＩＭＳ）法を用いて、バックサイド高分子膜９の銅（同位体核種６３Ｃｕ）の濃度を測定した結果が示されている。なお、測定に際しては、図３に示すような、実際のＬＳＩチップに形成される貫通ヴィア６Ｖを模擬したサンプルを作成し、このサンプルの、図中Ａ－Ａ線に沿った箇所（バックサイド高分子膜９の部分）を測定した。 FIG. 2 is a diagram showing the relationship between the depth of the backside polymer film and the copper (Cu) concentration. FIG. 2 shows the result of measuring the concentration of copper (isotope nuclide 63 Cu) in the backside polymer film 9 using secondary ion mass spectrometry (SIMS). In the measurement, a sample simulating the through-via 6V formed in an actual LSI chip as shown in FIG. 3 was prepared, and a location along the line AA (backside height in the figure) of this sample was created. The portion of the molecular film 9) was measured.
　　（サンプル作成方法）
　ここで、サンプルの作成方法を説明する。　
　図４Ａ～図４Ｄは、サンプルの作成方法を示す断面図である。 (Sample creation method)
Here, a sample creation method will be described.
4A to 4D are cross-sectional views showing a method for producing a sample.
　まず、図４Ａに示すように、シリコン基板１の表面上に熱酸化膜１０１を形成する。次いで、熱酸化膜１０１上に、バリア層１０２を形成する。バリア層１０２は、例えば、タンタル製である。次いで、バリア層１０２上に、スパッタ法を用いて銅膜１０３を形成する。次いで、銅膜１０３上にホトレジストを塗布し、ホトレジスト膜１０４を形成する。次いで、ホトリソグラフィ法を用いて、ホトレジスト膜１０４にホール状の開孔１０５を形成する。 First, as shown in FIG. 4A, a thermal oxide film 101 is formed on the surface of the silicon substrate 1. Next, a barrier layer 102 is formed on the thermal oxide film 101. The barrier layer 102 is made of tantalum, for example. Next, a copper film 103 is formed on the barrier layer 102 by a sputtering method. Next, a photoresist is applied on the copper film 103 to form a photoresist film 104. Next, a hole-like hole 105 is formed in the photoresist film 104 by using a photolithography method.
　次に、図４Ｂに示すように、開孔１０５の底に露呈した銅膜１０３を種として、開孔１０５の内部に銅をめっき成長させ、柱状の銅膜を形成する。この柱状の銅膜は、疑似貫通ヴィア６ＶＳとなる。 Next, as shown in FIG. 4B, using the copper film 103 exposed at the bottom of the opening 105 as a seed, copper is plated and grown inside the opening 105 to form a columnar copper film. This columnar copper film becomes a pseudo through-via 6VS.
　次に、図４Ｃに示すように、ホトレジスト膜１０４を除去する。 Next, as shown in FIG. 4C, the photoresist film 104 is removed.
　次に、図４Ｄに示すように、銅膜１０３、および疑似貫通ヴィア６ＶＳ上にタンタル膜を形成する。このタンタル膜は、バリア膜５Ｓとなる。次いで、バリア膜５Ｓ上に高分子膜を形成する。この高分子膜は、疑似バックサイド高分子膜９Ｓとなる。なお、疑似バックサイド高分子膜９Ｓは蒸着重合法を用いて形成され、例えば、第１のモノマーとしてピロメリット酸二無水物（ＰＭＤＡ：Ｃ１０Ｈ２Ｏ６）、第２のモノマーとして４，４´－オキシジアニリン（ＯＤＡ：Ｃ１２Ｈ１２Ｎ２Ｏ）を用い、これらをそれぞれ気化させたものを成膜装置の処理室内に供給することで形成した。形成される疑似バックサイド高分子膜９Ｓは、ポリイミド膜である。 Next, as shown in FIG. 4D, a tantalum film is formed on the copper film 103 and the pseudo through-via 6VS. This tantalum film becomes the barrier film 5S. Next, a polymer film is formed on the barrier film 5S. This polymer film becomes the pseudo backside polymer film 9S. The pseudo backside polymer film 9S is formed by vapor deposition polymerization. For example, pyromellitic dianhydride (PMDA: C 10 H 2 O 6 ) is used as the first monomer, and 4,4 is used as the second monomer. This was formed by using 4′-oxydianiline (ODA: C 12 H 12 N 2 O) and supplying the vaporized materials to the processing chamber of the film forming apparatus. The formed pseudo backside polymer film 9S is a polyimide film.
　最後に、図３に示すように、疑似バックサイド高分子膜９Ｓ、バリア膜５Ｓ、および疑似貫通ヴィア６ＶＳを、化学的機械研磨（ＣＭＰ）し、疑似貫通ヴィア６ＶＳを外部に露出させる。なお、研磨後の疑似バックサイド高分子膜９Ｓの膜厚は、およそ４μｍであった。 Finally, as shown in FIG. 3, the pseudo backside polymer film 9S, the barrier film 5S, and the pseudo through-via 6VS are chemically mechanically polished (CMP) to expose the pseudo through-via 6VS to the outside. The film thickness of the pseudo backside polymer film 9S after polishing was approximately 4 μm.
　　（測定結果）
　図２に示すように、およそ４μｍの膜厚を持つ疑似バックサイド高分子膜９Ｓ中の銅の濃度は１０１６atoms/cm３以下であり、疑似バックサイド高分子膜９Ｓ中には、銅がほとんど存在していないことが判明した。これは、疑似バックサイド高分子膜９Ｓを化学的機械研磨しても、疑似バックサイド高分子膜９Ｓの表面上には銅が拡がらないことを示している。つまり、蒸着重合法を用いて形成された高分子膜によって、疑似バックサイド高分子膜９Ｓを形成することで、いわゆる“銅の引き摺り現象”を抑制することができる。よって、この発明の一実施形態に係る貫通ヴィアの形成方法によれば、銅の拡散による影響、例えば、バックサイド絶縁膜（バックサイド高分子膜９）の絶縁性が低下する等の懸念を払拭することができる。 (Measurement result)
As shown in FIG. 2, the concentration of copper in the pseudo backside polymer film 9S having a film thickness of about 4 μm is 10 16 atoms / cm 3 or less, and copper is contained in the pseudo backside polymer film 9S. It turns out that there is hardly any. This indicates that copper does not spread on the surface of the pseudo backside polymer film 9S even when the pseudo backside polymer film 9S is chemically mechanically polished. That is, the so-called “copper drag phenomenon” can be suppressed by forming the pseudo backside polymer film 9S by the polymer film formed by using the vapor deposition polymerization method. Therefore, according to the method for forming a through via according to an embodiment of the present invention, the influence of copper diffusion, for example, the concern that the insulating property of the backside insulating film (backside polymer film 9) is lowered is eliminated. can do.
　なお、図２に示したように、疑似バックサイド高分子膜９Ｓの表面付近、例えば、１μｍ程度の深さまで、やや銅の存在が認められる。これは、次のように結論づけることができる。 In addition, as shown in FIG. 2, the presence of a little copper is recognized near the surface of the pseudo backside polymer film 9S, for example, to a depth of about 1 μm. This can be concluded as follows.
　図５に示すように、ＳＩＭＳによる分析においては、一次イオンをサンプルにぶつけ、サンプルから二次イオンをたたき出す。この二次イオンの質量を分析することによって、サンプル中に含まれる成分を調べる。このため、サンプルの表面には、サンプルがチャージアップしてしまうことを防止するために、荷電粒子ｅを逃すための金被膜１０６が形成される。金被膜１０６は、荷電粒子ｅを逃すだけの目的で形成されるものであり、純度は高くない。このため、金被膜１０６には、銅などの不純物が含まれる。この金被膜１０６に含まれた銅が一次イオンによりノックオンされると、疑似バックサイド高分子膜９Ｓの表面付近に銅が押し込まれる。このような金被膜１０６中の不純物に由来した銅が、疑似バックサイド高分子膜９Ｓの表面付近、例えば、１μｍ程度の深さまでの間に、観測された。 As shown in FIG. 5, in the analysis by SIMS, the primary ions are struck against the sample, and the secondary ions are knocked out from the sample. The component contained in the sample is examined by analyzing the mass of the secondary ions. For this reason, a gold coating 106 for allowing the charged particles e to escape is formed on the surface of the sample in order to prevent the sample from being charged up. The gold coating 106 is formed only for the purpose of escaping the charged particles e, and the purity is not high. For this reason, the gold coating 106 contains impurities such as copper. When copper contained in the gold coating 106 is knocked on by primary ions, copper is pushed into the vicinity of the surface of the pseudo backside polymer film 9S. Copper derived from impurities in the gold film 106 was observed near the surface of the pseudo backside polymer film 9S, for example, to a depth of about 1 μm.
　以上のように、この発明の一実施形態に係る貫通ヴィアの形成方法によれば、導電体に銅を使用した場合でも、銅の拡散を抑制することができる、という利点を得ることができる。 As described above, according to the through via forming method according to an embodiment of the present invention, even when copper is used as the conductor, an advantage that copper diffusion can be suppressed can be obtained.
　さらに、バックサイド絶縁膜として、本例では、蒸着重合法を用いて形成されたバックサイド高分子膜９を用いる。このようなバックサイド高分子膜９は、例えば、シリコン酸化物膜やシリコン窒化物膜に比較して、シリコン基板１に及ぼすストレスを小さくすることができる。このため、シリコン基板１の肉厚を薄くしても、シリコン基板１が反りかえってしまうような事情についても改善することができる。即ち、バックサイド絶縁膜に、例えば、シリコン酸化物膜やシリコン窒化物膜を用いたＬＳＩチップに比較して、バックサイド絶縁膜に、蒸着重合法を用いて形成されたバックサイド高分子膜９を用いたＬＳＩチップ１００によれば、よりその厚みを薄くすることが可能である。 Further, as the back side insulating film, in this example, a back side polymer film 9 formed by vapor deposition polymerization is used. Such a backside polymer film 9 can reduce stress on the silicon substrate 1 as compared with, for example, a silicon oxide film or a silicon nitride film. For this reason, even if the thickness of the silicon substrate 1 is reduced, the situation where the silicon substrate 1 is warped can be improved. That is, the backside polymer film 9 formed on the backside insulating film by using the vapor deposition polymerization method as compared with, for example, an LSI chip using a silicon oxide film or a silicon nitride film as the backside insulating film. The LSI chip 100 using the can be made thinner.
　したがって、この発明の一実施形態に係る貫通ヴィアの形成方法によれば、シリコン基板１の肉厚が薄くなっても、シリコン基板１の反りを抑制することが可能である、という利点についても得ることができる。 Therefore, according to the through via forming method according to the embodiment of the present invention, even when the thickness of the silicon substrate 1 is reduced, the warp of the silicon substrate 1 can be suppressed. be able to.
　そして、シリコン基板１の肉厚をより薄くできる結果、ＬＳＩチップ１００の厚みを、より薄くすることが可能となる。このため、例えば、図６の斜視図に示すように、ＬＳＩチップ１００を三次元実装した際、その全体の厚みＴを、さらに薄くすることも可能となる。このような利点は、三次元実装されたＬＳＩ製品の小型化に、有用な利点の一つとなる。 And as a result of being able to make the thickness of the silicon substrate 1 thinner, the thickness of the LSI chip 100 can be made thinner. Therefore, for example, as shown in the perspective view of FIG. 6, when the LSI chip 100 is three-dimensionally mounted, the entire thickness T can be further reduced. Such an advantage is one of the advantages useful for miniaturization of LSI products mounted three-dimensionally.
　また、上記一実施形態に係る貫通ヴィアの形成方法は、電子製品、例えば、半導体集積回路装置（ＬＳＩチップ）の製造方法への適用にも有用である。 In addition, the through via forming method according to the above embodiment is also useful for application to a manufacturing method of an electronic product, for example, a semiconductor integrated circuit device (LSI chip).
　以上、この発明を一実施形態に従って説明したが、この発明は、上記実施形態に限定されることは無く、その趣旨を逸脱しない範囲で種々変形可能である。また、この発明の実施形態は、上記一実施形態が唯一の実施形態でもない。 As mentioned above, although this invention was demonstrated according to one Embodiment, this invention is not limited to the said embodiment, A various deformation | transformation is possible in the range which does not deviate from the meaning. In the embodiment of the present invention, the above-described embodiment is not the only embodiment.
　例えば、上記一実施形態においては、ＬＳＩチップに形成された貫通ヴィアを例示したが、貫通ヴィアは、ＬＳＩチップに限って形成されるものではない。上記一実施形態は、例えば、三次元実装における中継配線基板や、外部端子を外部電子機器との端子に対して整合させる端子再配置基板として用いられるインターポーザ中の貫通ヴィアにも適用することができる。図７にインターポーザの一例として、端子再配置基板２００の概略的な断面図を示す。図７に示す端子再配置基板２００は、例えば、ＬＳＩチップ側端子８ａの配置ピッチＰ-ＬＳＩを、回路基板側端子１０ａの配置ピッチＰ-ＣＫＴに変換するものである。端子再配置基板２００における配置ピッチＰ-ＣＫＴは、配置ピッチＰ-ＬＳＩよりも広い。このような端子再配置基板２００の、表側と裏面側とを接続する貫通ヴィア６Ｖの形成にも、上記一実施形態に係る貫通ヴィアの形成方法は、有効に適用することができる。 For example, in the above-described embodiment, the through via formed in the LSI chip is illustrated, but the through via is not limited to the LSI chip. The above-described embodiment can also be applied to, for example, a through-wiring in an interposer used as a relay wiring board in three-dimensional mounting or a terminal rearrangement board that aligns external terminals with terminals with external electronic devices. . FIG. 7 shows a schematic cross-sectional view of a terminal rearrangement board 200 as an example of an interposer. The terminal rearrangement board 200 shown in FIG. 7 converts, for example, the arrangement pitch P-LSI of the LSI chip side terminals 8a into the arrangement pitch P-CKT of the circuit board side terminals 10a. The arrangement pitch P-CKT in the terminal rearrangement substrate 200 is wider than the arrangement pitch P-LSI. The through via forming method according to the above-described embodiment can be effectively applied to the formation of the through via 6V that connects the front side and the back side of the terminal rearrangement substrate 200 as described above.
　また、上記一実施形態においては、貫通ヴィアをシリコン基板（シリコンウエハ）に形成したが、基板についてもシリコンに限られるものではない。電子製品を作るための基板であれば、この発明に係る貫通ヴィアの形成方法は適用することができる。 In the above embodiment, the through via is formed in the silicon substrate (silicon wafer), but the substrate is not limited to silicon. If it is a board | substrate for making an electronic product, the formation method of the penetration via concerning this invention is applicable.
　その他、この発明はその要旨を逸脱しない範囲で様々に変形することができる。 In addition, the present invention can be variously modified without departing from the gist thereof.
　１…シリコン基板、２…デバイス形成領域、３…トレンチ、４…ライナー高分子膜、５…シード兼バリア膜、６…導電体膜、６Ｖ…貫通ヴィア、７…内部配線層、８…フロントバンプ電極、９…バックサイド高分子膜、１０…バックバンプ電極、１００…ＬＳＩチップ、２００…インターポーザ（端子再配置基板）。 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Device formation area, 3 ... Trench, 4 ... Liner polymer film, 5 ... Seed and barrier film, 6 ... Conductor film, 6V ... Through-via, 7 ... Internal wiring layer, 8 ... Front bump Electrode, 9 ... backside polymer film, 10 ... back bump electrode, 100 ... LSI chip, 200 ... interposer (terminal rearrangement substrate).

Claims (10)

  1. 　（１）　基板の表面から、前記基板内に向かってホール状のトレンチを形成する工程と、
    　（２）　前記トレンチ内に、第１の絶縁膜を形成する工程と、
    　（３）　前記第１の絶縁膜が形成されたトレンチ内に、貫通ヴィアとなる導電体膜を形成する工程と、
    　（４）　前記基板の表面に相対した、前記基板の裏面を後退させ、前記基板の裏面から、内側に前記導電体膜を包んでいる前記第１の絶縁膜を突出させる工程と、
    　（５）　前記基板の裏面上、および前記基板の裏面から突出された前記第１の絶縁膜上に、第２の絶縁膜を形成する工程と、
    　（６）　前記第２の絶縁膜、前記第１の絶縁膜、および前記導電体膜を後退させ、前記導電体膜を外部に露出させる工程と、を具備し、
    　前記第２の絶縁膜を、高分子膜にて形成する貫通ヴィアの形成方法。     (1) forming a hole-shaped trench from the surface of the substrate into the substrate;
    (2) forming a first insulating film in the trench;
    (3) forming a conductive film to be a through via in the trench in which the first insulating film is formed;
    (4) retreating the back surface of the substrate relative to the surface of the substrate, and projecting the first insulating film enclosing the conductor film on the inside from the back surface of the substrate;
    (5) forming a second insulating film on the back surface of the substrate and on the first insulating film protruding from the back surface of the substrate;
    (6) retreating the second insulating film, the first insulating film, and the conductor film, and exposing the conductor film to the outside,
    A method of forming a penetrating via, wherein the second insulating film is formed of a polymer film.
  2. 　前記第２の絶縁膜は、蒸着重合法を用いて形成される請求項１に記載の貫通ヴィアの形成方法。 The method for forming a through via according to claim 1, wherein the second insulating film is formed using a vapor deposition polymerization method.
  3. 　前記第２の絶縁膜は、ポリイミド膜である請求項１に記載の貫通ヴィアの形成方法。 The method for forming a through via according to claim 1, wherein the second insulating film is a polyimide film.
  4. 　前記第１の絶縁膜を、高分子膜にて形成する請求項１に記載の貫通ヴィアの形成方法。 The method for forming a through via according to claim 1, wherein the first insulating film is formed of a polymer film.
  5. 　前記第１の絶縁膜は、蒸着重合法を用いて形成される請求項４に記載の貫通ヴィアの形成方法。 The method for forming a through via according to claim 4, wherein the first insulating film is formed by using a vapor deposition polymerization method.
  6. 　前記第１の絶縁膜は、ポリイミド膜である請求項４に記載の貫通ヴィアの形成方法。 The method for forming a through via according to claim 4, wherein the first insulating film is a polyimide film.
  7. 　前記（６）工程を、研磨により行う請求項１に記載の貫通ヴィアの形成方法。 The method for forming a through via according to claim 1, wherein the step (6) is performed by polishing.
  8. 　前記導電体膜は、銅を含む請求項１に記載の貫通ヴィアの形成方法。 2. The through via formation method according to claim 1, wherein the conductor film contains copper.
  9. 　貫通ヴィアを備えた電子製品の製造方法であって、
    　前記貫通ヴィアを、請求項１に記載の貫通ヴィアの形成方法にしたがって形成する電子製品の製造方法。     A method of manufacturing an electronic product with a through via,
    The manufacturing method of the electronic product which forms the said penetration via according to the formation method of the penetration via of Claim 1.
  10. 　前記電子製品は、半導体集積回路チップ、およびインターポーザの少なくともいずれか１つである請求項９に記載の電子製品の製造方法。 10. The method of manufacturing an electronic product according to claim 9, wherein the electronic product is at least one of a semiconductor integrated circuit chip and an interposer.
PCT/JP2013/084637 2013-01-17 2013-12-25 Method for forming through-via and method for manufacturing electronic device WO2014112305A1 (en)

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JP2009503906A (en) * 2005-08-05 2009-01-29 マイクロン テクノロジー， インク． Method for forming a through-wafer interconnect and structure resulting therefrom
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