[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

WO2013095341A1 - Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture - Google Patents

Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture Download PDF

Info

Publication number
WO2013095341A1
WO2013095341A1 PCT/US2011/065914 US2011065914W WO2013095341A1 WO 2013095341 A1 WO2013095341 A1 WO 2013095341A1 US 2011065914 W US2011065914 W US 2011065914W WO 2013095341 A1 WO2013095341 A1 WO 2013095341A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
group
nanowire
substrate
group iii
Prior art date
Application number
PCT/US2011/065914
Other languages
French (fr)
Inventor
Marko Radosavljevic
Ravi Pillarisetty
Gilbert Dewey
Niloy Mukherjee
Jack Kavalieros
Willy Rachmady
Van Le
Benjamin Chu-Kung
Matthew V. Metz
Robert Chau
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to CN201710001499.1A priority Critical patent/CN106847814B/en
Priority to PCT/US2011/065914 priority patent/WO2013095341A1/en
Priority to DE112011105970.1T priority patent/DE112011105970B4/en
Priority to CN201180075625.9A priority patent/CN103999226B/en
Priority to US13/976,411 priority patent/US9123567B2/en
Priority to TW101144770A priority patent/TWI502729B/en
Publication of WO2013095341A1 publication Critical patent/WO2013095341A1/en
Priority to US14/798,380 priority patent/US9666492B2/en
Priority to US15/498,280 priority patent/US10319646B2/en
Priority to US16/372,272 priority patent/US10784170B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection

Definitions

  • Embodiments of the present invention generally relate to microelectronic device architecture and fabrication, and more particularly to heterogeneous nanowire transistors for CMOS.
  • HVM high volume manufacturing
  • Figure 1 is an isometric illustration of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with an embodiment
  • Figure 2A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 2B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 3A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 3B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 4A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 4B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 5A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 5B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment
  • Figure 6 is a flow diagram illustrating a method of fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with an embodiment
  • Figure 7 is a flow diagram illustrating a method of fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with an embodiment
  • Figure 8A and 8B are a cross-sectional illustration of starting substrates for fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment of the present invention.
  • Figure 9 illustrates a illustrates a computing device in accordance with one implementation of the invention.
  • Coupled and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other.
  • Coupled my be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).
  • the terms "over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer.
  • heterogeneous materials such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon).
  • multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor.
  • individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket (i.e., full wafer) stack of alternating Ge/III-V layers.
  • vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
  • FIG. 1 is an isometric illustration of a PMOS nanowire device (transistor) 110 integrated with a NMOS group III-V nanowire device (transistor) 120 on a same substrate 101, in accordance with an embodiment.
  • the PMOS nanowire device 110 includes one or more PMOS nanowires 112A, 112B composed of a group IV semiconductor disposed over a first substrate region 102, while the NMOS nanowire device 120 includes one or more NMOS nanowires 122A, 122B composed of a group III-V semiconductor disposed over a second substrate region 103.
  • the differing nanowire materials employed for the PMOS and NMOS devices provide a transistor- level architecture conducive to CMOS with performance capabilities that beyond silicon-based CMOS devices.
  • the substrate 101 is silicon, insulating or semi-insulating and/or has an insulating or semi-insulating layer disposed there on, over which the PMOS device 110 and NMOS device 120 is disposed.
  • the substrate 105 includes a top layer of buffer structure either grown on a support substrate or transferred onto a donor substrate (support and donor substrates not depicted).
  • the substrate 101 includes a silicon support substrate, upon which a buffer layer is epitaxially grown, however, the support substrate may also be of alternate materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, carbon (SiC), and sapphire.
  • the substrate 101 includes a dielectric layer such as a buried oxide (BoX) which may be formed for example by transferring one or more layers of the semiconductor from which the nanowires formed onto the substrate 101.
  • BoX buried oxide
  • a longitudinal length of a nanowire is divided between a channel region around which gate conductors 115 and 125 wrap completely around to form a coaxial nanowire structure, extrinsic regions around which dielectric spacers 116A, 116B, 126A, and 126B are disposed, and source/drain regions 113, 123.
  • the nanowires 112A, 122A are physically separated from the substrate 101 by an intervening material.
  • the transverse cross-sectional geometry of the nanowires 112A, 122 A may vary considerably from circular to rectangular such that the thickness of the nanowires 112A, 122A (i.e., in z dimension) may be approximately equal to a width of the nanowires 112A, 122A (i.e., in x dimension) or the thickness and width of the nanowires 112A, 122 A may be significantly different from each other (i.e., physically akin to a ribbon, etc.) to form cylindrical and parallelepiped
  • the width of the nanowires 112A, 122A is between 5 and 50 nanometers (nm), and more particularly between 5 and 10 nm, but this may vary depending on implementation.
  • the nanowires 112A, 122 A are crystalline with much greater long range order than a "polycrystalline" material.
  • the channel region is substantially single crystalline and although may be referred to herein as "monocrystalline," one of ordinary skill will appreciate that a low level of crystal defects may nevertheless be present as artifacts of an imperfect epitaxial growth process.
  • At least one of the PMOS device 110 and NMOS device 120 is heterogeneous in the sense that the substrate 101 is not of the same material as at least the channel region of the nano wires 112A and/or 122 A.
  • the PMOS nanowire 112A consists essentially of germanium (Ge). Germanium is advantageous for high hole mobility and also has lattice parameters matched to some group III-V semiconductor materials sufficiently for good quality epitaxial stacks of Ge layers and group III-V semiconductor layers. Alternative embodiments where the PMOS nanowire 112A is composed of a group IV alloy (e.g., SiGe) or composed of silicon are also possible.
  • the NMOS nanowire 122A consists essentially of a group III-V semiconductor material. In the exemplary embodiment where the PMOS nanowire 112A consists essentially of germanium, the NMOS nanowire 122A consists essentially of GaAs.
  • the NMOS nanowire 122A consists essentially of: InAs, a group III-N (e.g., GaN), InP, a ternary alloy comprising GaAs, a ternary alloy comprising InAs, a ternary alloy comprising InP, or a ternary alloy comprising a group III-N, or a quaternary alloy comprising GaAs, a quaternary alloy comprising InAs, a quaternary alloy comprising InP, or a quaternary alloy comprising a group III-N.
  • the channel region in both the PMOS nanowire 112A and the NMOS nanowire 122A is substantially undoped for highest carrier mobility.
  • the nanowires 112A, 122A further include source/drain region 113, 123, respectively.
  • the source regions comprise the same semiconductor material present in the channel region for the respective PMOS and NMOS nanowires, but the source and drain regions further include a higher concentration of dopant.
  • the PMOS nanowire source/drain region 113 comprises a high p-type impurity (P+ dopant) while the NMOS nanowire source/drain region 123 comprises a high n-type impurity (i.e., N+ dopant).
  • the source and drain regions maintain the same monocrystallinity as within the channel region of the nanowires 112A and 123 A.
  • at least one of the source/drains 113, 123 are contacted with an ohmic metal (not depicted) that coaxially wraps completely around the nanowires 112 A, 122A to fill in the gaps between the nano wires and the substrate 101.
  • the source/drain contacts may further include an epitaxially grown semiconductor of different composition than the nanowires 112 A, 122 A.
  • a tunnel junction e.g., a p+ layer wrapping around the source region 123 of the nanowire 122A may provide an ultra steep turn on and off (i.e., improved sub-threshold performance).
  • in-situ doped semiconductor may be grown completely around the released source/drains 113, 123 for lower contact resistance.
  • both the PMOS nanowire device 110 and the NMOS nanowire device 120 include a vertical stack of nanowires to achieve a greater current carrying capability (e.g., larger drive currents) for a given device footprint (i.e., layout area) over the substrate 101.
  • a greater current carrying capability e.g., larger drive currents
  • Any number of nanowires may be vertically stacked, depending on fabrication limitations, with the longitudinal axis of each of the nanowire substantially parallel to a top surface of the substrate 101.
  • each of the PMOS nanowires 112A, 112B is of the same group IV semiconductor material (e.g., Ge).
  • each of the NMOS nanowires 122A, 122B is of the same group III-V semiconductor material (e.g., GaAs).
  • each of the PMOS nanowires 112A, 112B is coaxially wrapped by the gate conductor 115 (e.g., as further shown in Figures 2A, 3A, 4A, 5A).
  • the gate conductor 115 e.g., as further shown in Figures 2A, 3A, 4A, 5A.
  • source/drain regions coaxially wrap completely around source/drain regions 113, 123.
  • Figures 2A, 3A, 4A, and 5A illustrate cross-sectional views along an x-z plane (demarked in Figure 1 by the dashed line A) passing through the channel regions of the PMOS and NMOS devices 110, 120.
  • Figures 2B, 3B, 4B, and 5B illustrate cross-sectional views along an x-z plane (demarked in Figure 1 by the dashed line B) passing through an extrinsic region of the PMOS and NMOS devices 110, 120.
  • FIGS 2A and 2B illustrate an exemplary embodiment where the PMOS nanowires 112A, 112B are substantially coplanar with the NMOS nanowires 122 A, 122B.
  • a longitudinal axis 153 A of the PMOS nanowire 112A is disposed a first distance Hi above the substrate 101 while the longitudinal axis of the NMOS nanowire 122 A is disposed a second distance 3 ⁇ 4 above the substrate that is substantially equal to Hi (i.e., less than 10% difference).
  • the pitch PI between the longitudinal axis 153A, 153B is substantially equal (i.e., less than 10% different) to the pitch P2 between the longitudinal axis of the NMOS nano wires 122A and 122B.
  • Figure 2A further illustrates the gate conductors 115 and 125 to each comport with the MOS structure of a gate conductor (140, 145) that is electrically isolated from the nanowires (112, 122) by a gate dielectric material (140, 145) disposed under the gate conductor.
  • the coaxial nature of the wrap-around gate architecture is evident in Figure 2A as the gate dielectric material is disposed between the substrate layer 100 and the gate conductor.
  • the gate conductor is also disposed between the nanowires 112A, 122 A and the substrate 101.
  • the gate dielectric material 240 may include one or more of any material known in the art to be suitable for FET gate dielectrics (and/or channel passivation) and is preferably a high K dielectric (i.e., having a dielectric constant greater than that of silicon nitride (S1 3 N 4 )), such as, but not limited to, high K oxides like gadolinium oxide (Gd 2 (3 ⁇ 4), hafnium oxide ( ⁇ (3 ⁇ 4), high K silicates such as HfSiO, TaSiO, AlSiO, and high K nitrides such as HfON.
  • a high K dielectric i.e., having a dielectric constant greater than that of silicon nitride (S1 3 N 4 )
  • high K oxides like gadolinium oxide (Gd 2 (3 ⁇ 4), hafnium oxide ( ⁇ (3 ⁇ 4), high K silicates such as HfSiO, TaSiO, AlSiO, and high K nitri
  • the gate conductor may be of any material known in the art for gate electrodes suitable for the particular nanowire semiconductor composition and desired threshold voltage and operative mode (enhancement or depletion).
  • the same gate dielectric material is employed for the of the PMOS gate dielectric 140 and the NMOS gate dielectric 145.
  • the gate conductor composition includes a work function metal which may be selected to be distinct for each of the PMOS gate conductor 115 and the NMOS gate conductor 125 to obtain a desired threshold voltage (V t ) (e.g., greater than 0V, etc).
  • exemplary conductive gate materials include, tungsten (W), aluminum (Al), titanium (Ti), tantalum(Ta), nickel (Ni), molybdenum (Mo), germanium (Ge), platinum (Pt), gold (Au), ruthenium (Ru), palladium (Pd), iridium (Ir), their alloys and silicides, carbides, nitrides, phosphides, and carbonitrides thereof.
  • two vertically stacked nanowires are physically joined along at least a portion of the longitudinal nanowire length where the spacer is disposed by an intervening third crystalline
  • the PMOS nanowire 112A is joined to the substrate 101 by the intervening (third) semiconductor layer 21 OA while the PMOS nanowires 112A and 112B are joined together by the intervening semiconductor layer 210B.
  • the NMOS nanowire 122 A is joined to the substrate 101 by the intervening (forth) semiconductor layer 220A while the NMOS nanowires 122A and 122B are joined together by the intervening semiconductor layer 220B.
  • FIG. 2B While the structure depicted in Figure 2B may be in part an artifact of a particular fabrication process where the intervening layers 210, 220 are not completely removed (e.g., masked by the spacers 116A, 126A), it nonetheless illustrates the semiconductor material stack employed to release the nanowires in the channel regions depicted in Figure 2A.
  • the intervening semiconductor layers 21 OA, 210B are of any sacrificial semiconductor material which can maintain the desired crystallinity of the PMOS nanowires 112 A, 112B and are amenable to being removed selectively to the PMOS nanowires 112A, 112B.
  • the sacrificial semiconductor layers 210A, 210B comprise SiGe.
  • the intervening semiconductor layers 220A, 220B are of any sacrificial semiconductor material which can maintain the desired crystallinity of the NMOS nanowires 122 A, 122B and are amenable to being removed selectively to the PMOS nanowires 112A, 112B.
  • the sacrificial semiconductor layers 220 A, 220B comprise AlGaAs.
  • the thicknesses (z- dimension) of the sacrificial semiconductor layers 210, 220 may be selected as a matter of design based on desired nanowire pitch (e.g., PI, P2), gate stack deposition constraints, stack profile control, etc.
  • Figures 3A and 3B illustrate an exemplary embodiment where the PMOS nanowires 112A, 112B are shifted or offset along the z-dimension from the NMOS nanowires 122A, 122B.
  • the longitudinal axis of the PMOS nanowire 112A is disposed a first distance Hi above the substrate 101 while the longitudinal axis of the NMOS nanowire 122 A is disposed a second distance 3 ⁇ 4 above the substrate that is different than Hi (i.e., significantly more than 10% different).
  • second distance 3 ⁇ 4 is approximately equal to the first distance Hi added to a thickness of the first channel region (z-dimension) because the nano wires 112A and 122A are substantially equal.
  • the gap Gi between adjacent PMOS nanowires 112A, 112B is substantially equal to the thickness (diameter) of the NMOS nanowire 122A (illustrated as T 3 in Figure 3B).
  • the gap G 2 between adjacent NMOS nanowires 122 A, 122B is substantially equal to the thickness (diameter) of the PMOS nanowire 112B (illustrated as T 4 in Figure 3B).
  • the pitches PI and P2 are substantially equal.
  • the semiconductor material stack for the PMOS device 110 is the same as for the NMOS device 120.
  • the group IV material in the PMOS nanowire (e.g., 112B) serves as a sacrificial material in the NMOS device 120 while the group III-V material in the NMOS nanowire (e.g., 122A) serves as a sacrificial material in the PMOS device 110.
  • both the PMOS device 110 and the NMOS device 120 include a group IV semiconductor (e.g., Ge) layer alternating with a group III-V semiconductor (e.g., GaAs).
  • This dual function of the semiconductor layers is advantageous because it permits the PMOS/NMOS pair of stacks to be formed from a same blanket process that concurrently covers both the first and second regions of the substrate (e.g., regions 102 and 103 in Figure 1).
  • the PMOS nanowire 112 is disposed apart from the substrate 101 by way of a third sacrificial semiconductor material 210A that is also present in the NMOS device stack.
  • the third sacrificial material semiconductor 21 OA provides a standoff for the nanowire disposed closest to the substrate (e.g., PMOS nanowire 112A) to permit a wrap-around gate stack.
  • the third sacrificial semiconductor material 21 OA may be removed selectively to both the PMOS nanowire 112A and the NMOS nanowire 122A.
  • the third sacrificial semiconductor material 21 OA is group IV semiconductor (SiGe) while in another embodiment the third sacrificial semiconductor material 210A is a group III-V semiconductor material (AlGaAs).
  • the third sacrificial semiconductor material may be left as a non-functional, structural artifact in the device does not rely on the third sacrificial material as a means of nanowire release from the substrate 101 (e.g., the third sacrificial semiconductor material 210A may be left in the NMOS device 120) such that selectivity of the third sacrificial semiconductor material 210A to the group III- V material in nanowire 122 A poses no issue.
  • Figures 3A and 3B illustrate an exemplary embodiment where the PMOS nanowires 112A, 112B are again substantially offset from the NMOS nanowires 122A, 122B along the z-dimension.
  • a third sacrificial layer is disposed between adjacent layers in the alternating semiconductor material stacks as a means of decoupling the vertical spacing between nanowires in a first device (e.g., PMOS device 110) from the cross- sectional dimension (e.g., diameter or thickness in z-dimension) of a nanowire in the second device (e.g., NMOS device 120).
  • the gap Gi between adjacent PMOS nanowires 112 A, 112B is larger than the thickness of the NMOS nanowire 122 A (T 3 , Figure 4B) and the gap G 2 between adjacent NMOS nanowires 122A, 122B is larger than the thickness of the PMOS nanowire 112B (T 4 , Figure 4B).
  • the larger gaps Gl , G2 may be tailored to the demands of channel engineering and/or gate stack deposition constraints to ensure adequate fill of the gate conductors 115, 125 around the nanowires 112A, 112B, 122A, 122B.
  • a third sacrificial semiconductor material 31 OA is disposed between the nanowires 122A, 112B.
  • the third sacrificial semiconductor material 310A is again removed selectively to both the group IV material employed in the PMOS nanowire 112B and the group III-V material employed in the NMOS nanowire 122A. While many such materials exist, the preferred materials are conducive to maintaining crystallinity of the group III-V and group IV materials, for example SiGe, or AlGaAs.
  • Figures 4A and 4B further illustrate an exemplary embodiment where a recess etching the substrate 101 enables release of a nanowire (e.g., the PMOS nanowire 112A) without a third sacrificial layer disposed on the substrate 101.
  • the substrate 101 has a recess of height ⁇ sufficient to release the PMOS nanowire 112A.
  • the portion of the recess under the channel region is backfilled with gate conductor 115.
  • Such a structure may be achieved by undercutting the device stack in the first substrate region 102 with an etchant selective to the substrate material.
  • the PMOS and NMOS devices 110, 120 may be formed from a same semiconductor devices stack with minimal vertical stack height.
  • Figures 5A and 5B illustrate an exemplary embodiment where a plurality of materials is employed in a nanowire of a first device. That plurality of materials is then either sacrificial in the second device or retained.
  • the NMOS device 120 includes a nanowire 122 A with a bottom and top barrier or transition layer 132 A, 132B and a nanowire 122B with a bottom and top barrier or transition layer 142 A, 142B.
  • the barrier or transition layers 132A, 132B, 142A, 142B may be of a different bandgap (e.g., wider) than the nanowires 122A, 122B and may function as one or more of, a hybrid gate dielectric layer confining carriers in combination with the gate dielectric 145, a channel passivation layer, a sheet charge inducing layer, a strain layer, a channel bandgap (V t ) tuning layer, or the like.
  • the barrier or transition layers 132A, 132B, 142 A, 142B are present in extrinsic regions of both the PMOS and NMOS devices 110, 120, and may either be utilized as sacrificial layer or retained as a partial cladding in the channel region of the complementary device.
  • the barrier or transition layers 132A, 132B, 142A, 142B may be utilized in the PMOS device 110 in one of the functional capacities described above for the NMOS device 120.
  • the barrier or transition layers 132A, 132B, 142A, 142B are removed from the PMOS nanowires 112A, 112B as sacrificial along with the group III-V semiconductor utilized for the NMOS nanowires 122 A, 122B.
  • the larger gap 3 ⁇ 4 resulting from removing the barrier or transition layers 132A, 132B then provides more room for a separate channel transition layer 138, which like the gate dielectric 140 and gate conductor 115, may wrap around the PMOS nanowires 112 A, 112B.
  • a larger gap G2 is provided by removing barrier or transition layers 142 A, 142B.
  • Figures 6 and 7 are flow diagram illustrating methods 601 and 701 of fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with embodiments of the present invention. While methods 601 and 701 highlight certain operations, those operations may entail many more process sequences, and no order is implied by the numbering of the operations or relative positioning of the operations in Figures 6 and 7.
  • the method 601 utilizes a starting substrate having a blanket deposited semiconductor stack that is the same in two regions of the substrate 810, 820, as illustrated in Figure 8 A, while the method 701 entails a starting substrate having materially distinct stacks disposed in the two regions of the substrate 810, 820.
  • the method 601 begins at operation 610 with an alternating stack of PMOS and NMOS semiconductor material layers disposed on the first and second regions of the substrate.
  • the starting substrate 801 has a same stack of semiconductor materials 803 in which group IV semiconductor layers alternate with group III-V semiconductor layers disposed over both the regions 810 and 820.
  • the alternating stack of semiconductor materials 803 may be epitaxially grown on the substrate 101 or transferred and bonded.
  • the stack 803 is etched, for example by anisotropic plasma etch, into a first fin in the first region 810 and a second fin in the second region 820.
  • anisotropic plasma etch etch processes based on conventional techniques may be utilized.
  • NMOS material is removed from the first fin to form a gap between the group IV semiconductor layer and the substrate 101 to release the PMOS nanowires along a longitudinal channel length.
  • the group III-V layers are removed within the first region 810 selectively to the group IV layers using conventional techniques (e.g., isotropic wet and/or dry etch chemistries) to release PMOS nanowires 112 A, 112B.
  • PMOS material is removed from the second fin selectively to the group III-V semiconductor layer to form a gap between the group III-V
  • the semiconductor layer and the substrate to release the NMOS nanowires along at least their longitudinal channel lengths.
  • the group IV layers are removed selectively to the group III-V layers to release the NMOS nanowires 122 A and 122B.
  • gate stacks are then formed completely around the PMOS and NMOS nanowires (i.e., a coaxial structure) using any conventional deposition technique as a function of the materials utilized.
  • replacement gate techniques are utilized, as known in the art for non- planar silicon transistor technologies.
  • a sacrificial gate (stack) is formed, source and drain regions in the nanowires 112A, 112B are doped p-type, and source and drain regions in the nanowires 122A, 122B are doped n-type (and/or wrapped with raised source drain regions), the sacrificial gate removed, and the non- sacrificial gate stack formed.
  • Exemplary techniques for forming the non-sacrificial gate include atomic layer deposition (ALD) for high-K gate dielectric material, and ALD or physical vapor deposition (PVD) for gate conductor materials.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • Method 601 is then completed at operation 660 with conventional processing (e.g., interlayer dielectric formation, source and drain contact formation on each of the PMOS and NMOS devices, etc.).
  • the method 701 begins at operation 715 with a first stack of alternating PMOS semiconductor material layers and a first sacrificial material disposed on the first region of the substrate and a second stack of alternating NMOS semiconductor material layers and a second sacrificial material disposed on the second region of the substrate.
  • the starting material 802 includes a first stack of semiconductor materials 804, with the group IV semiconductor layers alternating with first sacrificial material layers 21 OA, 210B, disposed over a first substrate region 810.
  • the starting material 802 further includes a second stack of
  • each distinct alternating stack of semiconductor materials may be epitaxially grown on the substrate 101 (e.g., in the trenches formed in field isolation dielectric layer 850) and then sidewalls of the materials exposed (e.g., by recessing the field isolation dielectric layer 850).
  • the first sacrificial material layers 210A, 210B are removed by an etchant selective over the group IV semiconductor materials to form the PMOS nanowires 112A, 112B to release the PMOS nanowires 112A, 112B.
  • the second sacrificial material layers 220A, 220B are removed by an etchant selective over the group III-V semiconductor layers to release the NMOS nanowires 122 A, 122B.
  • gate stacks are formed completely around the released channel regions of the PMOS and NMOS nanowires (i.e., workfunction metals forming a coaxial structure with the nanowires) using any conventional deposition technique as a dependent on the workfunction and capping materials utilized.
  • replacement gate techniques are utilized, as known in the art for non-planar silicon transistor technologies.
  • a sacrificial gate (stack) is formed, source and drain regions in the nanowires 112 A, 112B are doped p-type, and source and drain regions in the nanowires 122A, 122B are doped n-type (and/or wrapped with raised source drain regions), the sacrificial gate removed, and the non-sacrificial gate stack formed.
  • Method 701 is then completed at operation 660 with conventional processing (e.g., interlayer dielectric formation, source and drain contact formation on each of the PMOS and NMOS devices, etc.).
  • the semiconductor stacks disposed on the substrate may further include one or more of the intervening semiconductor layers described elsewhere herein (e.g., by epitaxially growing a third sacrificial layer over the substrate in the first and second regions 810, 820).
  • operations 620 and 725 then further include etching the third sacrificial layer selectively to the group IV semiconductor layer to form a gap between the group IV semiconductor layer and the substrate in the first region 810 that is wider than a thickness of the group III-V semiconductor layer.
  • the third sacrificial layer is further etched selectively to the group III-V semiconductor layer to form a gap between the group III-V semiconductor layer and the substrate in the second region 820 that is wider than a thickness of the group IV
  • FIG. 9 illustrates a computing device 1000 in accordance with one implementation of the invention.
  • the computing device 1000 houses a board 1002.
  • the board 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006.
  • the processor 1004 is physically and electrically coupled to the board 1002.
  • the at least one communication chip 1006 is also physically and electrically coupled to the board 1002.
  • the communication chip 1006 is part of the processor 1004.
  • computing device 1000 may include other components that may or may not be physically and electrically coupled to the board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a
  • the communication chip 1006 enables wireless communications for the transfer of data to and from the computing device 1000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi- Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1000 may include a plurality of communication chips 1006.
  • a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004.
  • the integrated circuit die of the processor includes one or more devices, such as the PMOS device 110 and NMOS device 120 ( Figure 1) in accordance with embodiments described elsewhere herein.
  • the term "processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006.
  • the integrated circuit die of the communication chip includes one or more devices, such as the PMOS device 110 and NMOS device 120 ( Figure 1) in accordance with embodiments described elsewhere herein.
  • another component housed within the computing device 1000 may contain an integrated circuit die that includes one or more devices, such as the PMOS device 110 and NMOS device 120, as illustrated in Figure 1 and described elsewhere herein.
  • the computing device 1000 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1000 may be any other electronic device that processes data.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Description

CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBB ONS IN GATE- ALL- AROUND ARCHITECTURE
TECHNICAL FIELD
[0001] Embodiments of the present invention generally relate to microelectronic device architecture and fabrication, and more particularly to heterogeneous nanowire transistors for CMOS.
BACKGROUND
[0002] Silicon CMOS technology has been the mainstay of
microelectronics for decades past. However, Moore's Law will at some point require extension based on non-silicon device technology. While microelectronic devices have long been fabricated in materials other than silicon, such as group III- V semiconductors, MOS technologies in these medium are considered immature from a high volume manufacturing (HVM) standpoint.
[0003] Another problem with contemporary group III-V technologies stems from the lack of reasonably well matched n-type and p-type devices because although group III-V material systems have high electron mobility, hole mobility is much lower. As such, a transition from advanced silicon CMOS to group III-V devices may entail a significant disruption to circuit design which has to-date co- evolved with silicon-based devices and come to rely on the availability of complementary transistors for CMOS logic.
[0004] Device architectures and fabrication techniques capable of implementing CMOS with group III-V-based microelectronic devices offer the advantage of extending Moore's law for decades more.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Embodiments of the present invention are illustrated by way of example, and not by way of limitation, and can be more fully understood with reference to the following detailed description when considered in connection with the figures in which:
[0006] Figure 1 is an isometric illustration of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with an embodiment;
[0007] Figure 2A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0008] Figure 2B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0009] Figure 3A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0010] Figure 3B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0011] Figure 4A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0012] Figure 4B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0013] Figure 5A is an illustration of a cross-sectional plane passing through a channel region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0014] Figure 5B is an illustration of a cross-sectional plane passing through an extrinsic region of an NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment;
[0015] Figure 6 is a flow diagram illustrating a method of fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with an embodiment;
[0016] Figure 7 is a flow diagram illustrating a method of fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with an embodiment;
[0017] Figure 8A and 8B are a cross-sectional illustration of starting substrates for fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor, in accordance with an embodiment of the present invention; and
[0018] Figure 9 illustrates a illustrates a computing device in accordance with one implementation of the invention.
DETAILED DESCRIPTION
[0019] In the following description, numerous details are set forth, however, it will be apparent to one skilled in the art, that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present invention. Reference throughout this specification to "an embodiment" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the two embodiments are not mutually exclusive.
[0020] The terms "coupled" and "connected," along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other.
"Coupled" my be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). [0021] The terms "over," "under," "between," and "on" as used herein refer to a relative position of one material layer with respect to other layers. As such, for example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer.
[0022] Described herein are architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket (i.e., full wafer) stack of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
[0023] Figure 1 is an isometric illustration of a PMOS nanowire device (transistor) 110 integrated with a NMOS group III-V nanowire device (transistor) 120 on a same substrate 101, in accordance with an embodiment. The PMOS nanowire device 110 includes one or more PMOS nanowires 112A, 112B composed of a group IV semiconductor disposed over a first substrate region 102, while the NMOS nanowire device 120 includes one or more NMOS nanowires 122A, 122B composed of a group III-V semiconductor disposed over a second substrate region 103. The differing nanowire materials employed for the PMOS and NMOS devices provide a transistor- level architecture conducive to CMOS with performance capabilities that beyond silicon-based CMOS devices.
[0024] In the illustrative embodiment, the substrate 101 is silicon, insulating or semi-insulating and/or has an insulating or semi-insulating layer disposed there on, over which the PMOS device 110 and NMOS device 120 is disposed. In one such embodiment, the substrate 105 includes a top layer of buffer structure either grown on a support substrate or transferred onto a donor substrate (support and donor substrates not depicted). In a particular embodiment, the substrate 101 includes a silicon support substrate, upon which a buffer layer is epitaxially grown, however, the support substrate may also be of alternate materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, carbon (SiC), and sapphire. In another embodiment, the substrate 101 includes a dielectric layer such as a buried oxide (BoX) which may be formed for example by transferring one or more layers of the semiconductor from which the nanowires formed onto the substrate 101.
[0025] As further illustrated in Figure 1, for each of the PMOS and NMOS devices 110, 120, a longitudinal length of a nanowire is divided between a channel region around which gate conductors 115 and 125 wrap completely around to form a coaxial nanowire structure, extrinsic regions around which dielectric spacers 116A, 116B, 126A, and 126B are disposed, and source/drain regions 113, 123. Within at least the channel region, the nanowires 112A, 122A are physically separated from the substrate 101 by an intervening material. For the embodiments described herein, the transverse cross-sectional geometry of the nanowires 112A, 122 A may vary considerably from circular to rectangular such that the thickness of the nanowires 112A, 122A (i.e., in z dimension) may be approximately equal to a width of the nanowires 112A, 122A (i.e., in x dimension) or the thickness and width of the nanowires 112A, 122 A may be significantly different from each other (i.e., physically akin to a ribbon, etc.) to form cylindrical and parallelepiped
semiconductor bodies. For ribbon embodiments, advantageous embodiments have a z-dimension larger than the x dimension for the sake of reduced solid angle shadowing by the nanowire thereby improving coaxial encapsulation by the gate conductors 115, 125. For the exemplary embodiments, the width of the nanowires 112A, 122A is between 5 and 50 nanometers (nm), and more particularly between 5 and 10 nm, but this may vary depending on implementation.
[0026] Generally, the nanowires 112A, 122 A are crystalline with much greater long range order than a "polycrystalline" material. In the exemplary embodiment, the channel region is substantially single crystalline and although may be referred to herein as "monocrystalline," one of ordinary skill will appreciate that a low level of crystal defects may nevertheless be present as artifacts of an imperfect epitaxial growth process. At least one of the PMOS device 110 and NMOS device 120 is heterogeneous in the sense that the substrate 101 is not of the same material as at least the channel region of the nano wires 112A and/or 122 A.
[0027] In the exemplary embodiment, the PMOS nanowire 112A consists essentially of germanium (Ge). Germanium is advantageous for high hole mobility and also has lattice parameters matched to some group III-V semiconductor materials sufficiently for good quality epitaxial stacks of Ge layers and group III-V semiconductor layers. Alternative embodiments where the PMOS nanowire 112A is composed of a group IV alloy (e.g., SiGe) or composed of silicon are also possible. In embodiments, the NMOS nanowire 122A consists essentially of a group III-V semiconductor material. In the exemplary embodiment where the PMOS nanowire 112A consists essentially of germanium, the NMOS nanowire 122A consists essentially of GaAs. In other embodiments, the NMOS nanowire 122A consists essentially of: InAs, a group III-N (e.g., GaN), InP, a ternary alloy comprising GaAs, a ternary alloy comprising InAs, a ternary alloy comprising InP, or a ternary alloy comprising a group III-N, or a quaternary alloy comprising GaAs, a quaternary alloy comprising InAs, a quaternary alloy comprising InP, or a quaternary alloy comprising a group III-N. In further embodiments, the channel region in both the PMOS nanowire 112A and the NMOS nanowire 122A is substantially undoped for highest carrier mobility.
[0028] As further illustrated in Figure 1, the nanowires 112A, 122A further include source/drain region 113, 123, respectively. In embodiments, the source regions comprise the same semiconductor material present in the channel region for the respective PMOS and NMOS nanowires, but the source and drain regions further include a higher concentration of dopant. In the exemplary embodiment, the PMOS nanowire source/drain region 113 comprises a high p-type impurity (P+ dopant) while the NMOS nanowire source/drain region 123 comprises a high n-type impurity (i.e., N+ dopant). In certain embodiments, the source and drain regions maintain the same monocrystallinity as within the channel region of the nanowires 112A and 123 A. In embodiments, at least one of the source/drains 113, 123 are contacted with an ohmic metal (not depicted) that coaxially wraps completely around the nanowires 112 A, 122A to fill in the gaps between the nano wires and the substrate 101. The source/drain contacts may further include an epitaxially grown semiconductor of different composition than the nanowires 112 A, 122 A. For example, a tunnel junction (e.g., a p+ layer wrapping around the source region 123 of the nanowire 122A may provide an ultra steep turn on and off (i.e., improved sub-threshold performance). As another example, in-situ doped semiconductor may be grown completely around the released source/drains 113, 123 for lower contact resistance.
[0029] In embodiments, as shown in Figure 1, both the PMOS nanowire device 110 and the NMOS nanowire device 120 include a vertical stack of nanowires to achieve a greater current carrying capability (e.g., larger drive currents) for a given device footprint (i.e., layout area) over the substrate 101. Any number of nanowires may be vertically stacked, depending on fabrication limitations, with the longitudinal axis of each of the nanowire substantially parallel to a top surface of the substrate 101. In the exemplary embodiment illustrated in Figure 1, within at least the channel region, each of the PMOS nanowires 112A, 112B is of the same group IV semiconductor material (e.g., Ge). Likewise, within the channel region each of the NMOS nanowires 122A, 122B is of the same group III-V semiconductor material (e.g., GaAs). In further embodiments, each of the PMOS nanowires 112A, 112B is coaxially wrapped by the gate conductor 115 (e.g., as further shown in Figures 2A, 3A, 4A, 5A). Similarly, for each of the stacked nanowires contact metallization and/or raised (regrown) source/drain regions coaxially wrap completely around source/drain regions 113, 123.
[0030] Figures 2A, 3A, 4A, and 5A illustrate cross-sectional views along an x-z plane (demarked in Figure 1 by the dashed line A) passing through the channel regions of the PMOS and NMOS devices 110, 120. Figures 2B, 3B, 4B, and 5B illustrate cross-sectional views along an x-z plane (demarked in Figure 1 by the dashed line B) passing through an extrinsic region of the PMOS and NMOS devices 110, 120.
[0031] Figures 2A and 2B illustrate an exemplary embodiment where the PMOS nanowires 112A, 112B are substantially coplanar with the NMOS nanowires 122 A, 122B. As shown for the channel regions depicted in Figure 2A, a longitudinal axis 153 A of the PMOS nanowire 112A is disposed a first distance Hi above the substrate 101 while the longitudinal axis of the NMOS nanowire 122 A is disposed a second distance ¾ above the substrate that is substantially equal to Hi (i.e., less than 10% difference). Furthermore, the pitch PI between the longitudinal axis 153A, 153B is substantially equal (i.e., less than 10% different) to the pitch P2 between the longitudinal axis of the NMOS nano wires 122A and 122B.
[0032] Figure 2A further illustrates the gate conductors 115 and 125 to each comport with the MOS structure of a gate conductor (140, 145) that is electrically isolated from the nanowires (112, 122) by a gate dielectric material (140, 145) disposed under the gate conductor. The coaxial nature of the wrap-around gate architecture is evident in Figure 2A as the gate dielectric material is disposed between the substrate layer 100 and the gate conductor. The gate conductor is also disposed between the nanowires 112A, 122 A and the substrate 101.
Compositionally, the gate dielectric material 240 may include one or more of any material known in the art to be suitable for FET gate dielectrics (and/or channel passivation) and is preferably a high K dielectric (i.e., having a dielectric constant greater than that of silicon nitride (S13N4)), such as, but not limited to, high K oxides like gadolinium oxide (Gd2(¾), hafnium oxide (Ηί(¾), high K silicates such as HfSiO, TaSiO, AlSiO, and high K nitrides such as HfON.
[0033] Similarly, the gate conductor may be of any material known in the art for gate electrodes suitable for the particular nanowire semiconductor composition and desired threshold voltage and operative mode (enhancement or depletion). In certain embodiments the same gate dielectric material is employed for the of the PMOS gate dielectric 140 and the NMOS gate dielectric 145.
Generally, the gate conductor composition includes a work function metal which may be selected to be distinct for each of the PMOS gate conductor 115 and the NMOS gate conductor 125 to obtain a desired threshold voltage (Vt) (e.g., greater than 0V, etc). Exemplary conductive gate materials include, tungsten (W), aluminum (Al), titanium (Ti), tantalum(Ta), nickel (Ni), molybdenum (Mo), germanium (Ge), platinum (Pt), gold (Au), ruthenium (Ru), palladium (Pd), iridium (Ir), their alloys and silicides, carbides, nitrides, phosphides, and carbonitrides thereof.
[0034] Referring to Figure 2B, in embodiments two vertically stacked nanowires are physically joined along at least a portion of the longitudinal nanowire length where the spacer is disposed by an intervening third crystalline
semiconductor material layer. For example, the PMOS nanowire 112A is joined to the substrate 101 by the intervening (third) semiconductor layer 21 OA while the PMOS nanowires 112A and 112B are joined together by the intervening semiconductor layer 210B. Analogously, the NMOS nanowire 122 A is joined to the substrate 101 by the intervening (forth) semiconductor layer 220A while the NMOS nanowires 122A and 122B are joined together by the intervening semiconductor layer 220B. While the structure depicted in Figure 2B may be in part an artifact of a particular fabrication process where the intervening layers 210, 220 are not completely removed (e.g., masked by the spacers 116A, 126A), it nonetheless illustrates the semiconductor material stack employed to release the nanowires in the channel regions depicted in Figure 2A.
[0035] Generally, the intervening semiconductor layers 21 OA, 210B are of any sacrificial semiconductor material which can maintain the desired crystallinity of the PMOS nanowires 112 A, 112B and are amenable to being removed selectively to the PMOS nanowires 112A, 112B. In the exemplary embodiment where the PMOS nanowires 112A, 112B are Ge, the sacrificial semiconductor layers 210A, 210B comprise SiGe. Likewise, the intervening semiconductor layers 220A, 220B are of any sacrificial semiconductor material which can maintain the desired crystallinity of the NMOS nanowires 122 A, 122B and are amenable to being removed selectively to the PMOS nanowires 112A, 112B. In one exemplary embodiment where the NMOS nanowires 122 A, 122B are GaAs, the sacrificial semiconductor layers 220 A, 220B comprise AlGaAs. Notably, the thicknesses (z- dimension) of the sacrificial semiconductor layers 210, 220 may be selected as a matter of design based on desired nanowire pitch (e.g., PI, P2), gate stack deposition constraints, stack profile control, etc.
[0036] Figures 3A and 3B illustrate an exemplary embodiment where the PMOS nanowires 112A, 112B are shifted or offset along the z-dimension from the NMOS nanowires 122A, 122B. As shown for the channel regions depicted in Figure 3 A, the longitudinal axis of the PMOS nanowire 112A is disposed a first distance Hi above the substrate 101 while the longitudinal axis of the NMOS nanowire 122 A is disposed a second distance ¾ above the substrate that is different than Hi (i.e., significantly more than 10% different). In the illustrative embodiment, second distance ¾ is approximately equal to the first distance Hi added to a thickness of the first channel region (z-dimension) because the nano wires 112A and 122A are substantially equal. As also shown, the gap Gi between adjacent PMOS nanowires 112A, 112B is substantially equal to the thickness (diameter) of the NMOS nanowire 122A (illustrated as T3 in Figure 3B). The gap G2 between adjacent NMOS nanowires 122 A, 122B is substantially equal to the thickness (diameter) of the PMOS nanowire 112B (illustrated as T4 in Figure 3B). As such, the pitches PI and P2 are substantially equal.
[0037] As further illustrated in Figure 3B, within the extrinsic regions, the semiconductor material stack for the PMOS device 110 is the same as for the NMOS device 120. In essence, the group IV material in the PMOS nanowire (e.g., 112B) serves as a sacrificial material in the NMOS device 120 while the group III-V material in the NMOS nanowire (e.g., 122A) serves as a sacrificial material in the PMOS device 110. In the exemplary embodiment, both the PMOS device 110 and the NMOS device 120 include a group IV semiconductor (e.g., Ge) layer alternating with a group III-V semiconductor (e.g., GaAs). This dual function of the semiconductor layers is advantageous because it permits the PMOS/NMOS pair of stacks to be formed from a same blanket process that concurrently covers both the first and second regions of the substrate (e.g., regions 102 and 103 in Figure 1).
[0038] Also shown in the embodiment of Figures 2 A, 2B, the PMOS nanowire 112 is disposed apart from the substrate 101 by way of a third sacrificial semiconductor material 210A that is also present in the NMOS device stack. The third sacrificial material semiconductor 21 OA, as for Figures 2A, 2B, provides a standoff for the nanowire disposed closest to the substrate (e.g., PMOS nanowire 112A) to permit a wrap-around gate stack. Employed as depicted in Figures 2A and 2B, the third sacrificial semiconductor material 21 OA may be removed selectively to both the PMOS nanowire 112A and the NMOS nanowire 122A. For example, in one embodiment the third sacrificial semiconductor material 21 OA is group IV semiconductor (SiGe) while in another embodiment the third sacrificial semiconductor material 210A is a group III-V semiconductor material (AlGaAs). In other embodiments, the third sacrificial semiconductor material may be left as a non-functional, structural artifact in the device does not rely on the third sacrificial material as a means of nanowire release from the substrate 101 (e.g., the third sacrificial semiconductor material 210A may be left in the NMOS device 120) such that selectivity of the third sacrificial semiconductor material 210A to the group III- V material in nanowire 122 A poses no issue.
[0039] Figures 3A and 3B illustrate an exemplary embodiment where the PMOS nanowires 112A, 112B are again substantially offset from the NMOS nanowires 122A, 122B along the z-dimension. In the third exemplary embodiment, a third sacrificial layer is disposed between adjacent layers in the alternating semiconductor material stacks as a means of decoupling the vertical spacing between nanowires in a first device (e.g., PMOS device 110) from the cross- sectional dimension (e.g., diameter or thickness in z-dimension) of a nanowire in the second device (e.g., NMOS device 120).
[0040] As illustrated in Figure 4A, the gap Gi between adjacent PMOS nanowires 112 A, 112B is larger than the thickness of the NMOS nanowire 122 A (T3, Figure 4B) and the gap G2 between adjacent NMOS nanowires 122A, 122B is larger than the thickness of the PMOS nanowire 112B (T4, Figure 4B). The larger gaps Gl , G2 may be tailored to the demands of channel engineering and/or gate stack deposition constraints to ensure adequate fill of the gate conductors 115, 125 around the nanowires 112A, 112B, 122A, 122B. As further shown in Figure 4B, a third sacrificial semiconductor material 31 OA is disposed between the nanowires 122A, 112B. In this embodiment, the third sacrificial semiconductor material 310A is again removed selectively to both the group IV material employed in the PMOS nanowire 112B and the group III-V material employed in the NMOS nanowire 122A. While many such materials exist, the preferred materials are conducive to maintaining crystallinity of the group III-V and group IV materials, for example SiGe, or AlGaAs.
[0041] Figures 4A and 4B further illustrate an exemplary embodiment where a recess etching the substrate 101 enables release of a nanowire (e.g., the PMOS nanowire 112A) without a third sacrificial layer disposed on the substrate 101. As shown, the substrate 101 has a recess of height ΔΗ sufficient to release the PMOS nanowire 112A. The portion of the recess under the channel region is backfilled with gate conductor 115. Such a structure may be achieved by undercutting the device stack in the first substrate region 102 with an etchant selective to the substrate material. With the substrate 101 recessed selectively in one of the substrate regions, the PMOS and NMOS devices 110, 120 may be formed from a same semiconductor devices stack with minimal vertical stack height.
[0042] Figures 5A and 5B illustrate an exemplary embodiment where a plurality of materials is employed in a nanowire of a first device. That plurality of materials is then either sacrificial in the second device or retained. As shown in Figure 5 A, the NMOS device 120 includes a nanowire 122 A with a bottom and top barrier or transition layer 132 A, 132B and a nanowire 122B with a bottom and top barrier or transition layer 142 A, 142B. The barrier or transition layers 132A, 132B, 142A, 142B may be of a different bandgap (e.g., wider) than the nanowires 122A, 122B and may function as one or more of, a hybrid gate dielectric layer confining carriers in combination with the gate dielectric 145, a channel passivation layer, a sheet charge inducing layer, a strain layer, a channel bandgap (Vt) tuning layer, or the like.
[0043] As shown in Figure 3B, the barrier or transition layers 132A, 132B, 142 A, 142B are present in extrinsic regions of both the PMOS and NMOS devices 110, 120, and may either be utilized as sacrificial layer or retained as a partial cladding in the channel region of the complementary device. For example, the barrier or transition layers 132A, 132B, 142A, 142B may be utilized in the PMOS device 110 in one of the functional capacities described above for the NMOS device 120. However, in the embodiment illustrated by Figure 5 A, the barrier or transition layers 132A, 132B, 142A, 142B are removed from the PMOS nanowires 112A, 112B as sacrificial along with the group III-V semiconductor utilized for the NMOS nanowires 122 A, 122B. In this exemplary embodiment, the larger gap ¾ resulting from removing the barrier or transition layers 132A, 132B then provides more room for a separate channel transition layer 138, which like the gate dielectric 140 and gate conductor 115, may wrap around the PMOS nanowires 112 A, 112B. Likewise, a larger gap G2 is provided by removing barrier or transition layers 142 A, 142B.
[0044] A brief description of salient portions of fabrication process embodiments is now provided. Figures 6 and 7 are flow diagram illustrating methods 601 and 701 of fabricating a NMOS group III-V nanowire transistor integrated with a PMOS group IV nanowire transistor on a same substrate, in accordance with embodiments of the present invention. While methods 601 and 701 highlight certain operations, those operations may entail many more process sequences, and no order is implied by the numbering of the operations or relative positioning of the operations in Figures 6 and 7. Generally, the method 601 utilizes a starting substrate having a blanket deposited semiconductor stack that is the same in two regions of the substrate 810, 820, as illustrated in Figure 8 A, while the method 701 entails a starting substrate having materially distinct stacks disposed in the two regions of the substrate 810, 820.
[0045] Referring first to Figure 6, the method 601 begins at operation 610 with an alternating stack of PMOS and NMOS semiconductor material layers disposed on the first and second regions of the substrate. For example, in the illustrative embodiment depicted in Figure 8 A, the starting substrate 801 has a same stack of semiconductor materials 803 in which group IV semiconductor layers alternate with group III-V semiconductor layers disposed over both the regions 810 and 820. The alternating stack of semiconductor materials 803 may be epitaxially grown on the substrate 101 or transferred and bonded.
[0046] Subsequently, at operation 620 the stack 803 is etched, for example by anisotropic plasma etch, into a first fin in the first region 810 and a second fin in the second region 820. Depending on the group IV and group III-V materials, one or more plasma etch processes based on conventional techniques may be utilized. At operation 630, NMOS material is removed from the first fin to form a gap between the group IV semiconductor layer and the substrate 101 to release the PMOS nanowires along a longitudinal channel length. For example, in the starting material 801 (Figure 8 A) the group III-V layers are removed within the first region 810 selectively to the group IV layers using conventional techniques (e.g., isotropic wet and/or dry etch chemistries) to release PMOS nanowires 112 A, 112B. At operation 640, PMOS material is removed from the second fin selectively to the group III-V semiconductor layer to form a gap between the group III-V
semiconductor layer and the substrate to release the NMOS nanowires along at least their longitudinal channel lengths. For example, in the stack 803 (Figure 8A), within the second region 820, the group IV layers are removed selectively to the group III-V layers to release the NMOS nanowires 122 A and 122B.
[0047] At operation 650, gate stacks are then formed completely around the PMOS and NMOS nanowires (i.e., a coaxial structure) using any conventional deposition technique as a function of the materials utilized. In particular embodiments, replacement gate techniques are utilized, as known in the art for non- planar silicon transistor technologies. In one embodiment, a sacrificial gate (stack) is formed, source and drain regions in the nanowires 112A, 112B are doped p-type, and source and drain regions in the nanowires 122A, 122B are doped n-type (and/or wrapped with raised source drain regions), the sacrificial gate removed, and the non- sacrificial gate stack formed. Exemplary techniques for forming the non-sacrificial gate include atomic layer deposition (ALD) for high-K gate dielectric material, and ALD or physical vapor deposition (PVD) for gate conductor materials. Method 601 is then completed at operation 660 with conventional processing (e.g., interlayer dielectric formation, source and drain contact formation on each of the PMOS and NMOS devices, etc.).
[0048] Referring next to Figure 7, the method 701 begins at operation 715 with a first stack of alternating PMOS semiconductor material layers and a first sacrificial material disposed on the first region of the substrate and a second stack of alternating NMOS semiconductor material layers and a second sacrificial material disposed on the second region of the substrate. For example, in the illustrative embodiment depicted in Figure 8B, the starting material 802 includes a first stack of semiconductor materials 804, with the group IV semiconductor layers alternating with first sacrificial material layers 21 OA, 210B, disposed over a first substrate region 810. The starting material 802 further includes a second stack of
semiconductor materials 805, with the group III-V semiconductor layers alternating with second sacrificial semiconductor material 220A, 220B, disposed over the second substrate region 820. For this embodiment, each distinct alternating stack of semiconductor materials may be epitaxially grown on the substrate 101 (e.g., in the trenches formed in field isolation dielectric layer 850) and then sidewalls of the materials exposed (e.g., by recessing the field isolation dielectric layer 850).
[0049] At operation 725 the first sacrificial material layers 210A, 210B are removed by an etchant selective over the group IV semiconductor materials to form the PMOS nanowires 112A, 112B to release the PMOS nanowires 112A, 112B. At operation 735, the second sacrificial material layers 220A, 220B are removed by an etchant selective over the group III-V semiconductor layers to release the NMOS nanowires 122 A, 122B. At operation 745 gate stacks are formed completely around the released channel regions of the PMOS and NMOS nanowires (i.e., workfunction metals forming a coaxial structure with the nanowires) using any conventional deposition technique as a dependent on the workfunction and capping materials utilized. In particular embodiments, replacement gate techniques are utilized, as known in the art for non-planar silicon transistor technologies. In one embodiment, a sacrificial gate (stack) is formed, source and drain regions in the nanowires 112 A, 112B are doped p-type, and source and drain regions in the nanowires 122A, 122B are doped n-type (and/or wrapped with raised source drain regions), the sacrificial gate removed, and the non-sacrificial gate stack formed. Method 701 is then completed at operation 660 with conventional processing (e.g., interlayer dielectric formation, source and drain contact formation on each of the PMOS and NMOS devices, etc.).
[0050] In either method 601 or 701 it is understood that the semiconductor stacks disposed on the substrate may further include one or more of the intervening semiconductor layers described elsewhere herein (e.g., by epitaxially growing a third sacrificial layer over the substrate in the first and second regions 810, 820). For such embodiments, operations 620 and 725 then further include etching the third sacrificial layer selectively to the group IV semiconductor layer to form a gap between the group IV semiconductor layer and the substrate in the first region 810 that is wider than a thickness of the group III-V semiconductor layer. Similarly, the third sacrificial layer is further etched selectively to the group III-V semiconductor layer to form a gap between the group III-V semiconductor layer and the substrate in the second region 820 that is wider than a thickness of the group IV
semiconductor layer. [0051] Figure 9 illustrates a computing device 1000 in accordance with one implementation of the invention. The computing device 1000 houses a board 1002. The board 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the board 1002. In some implementations the at least one communication chip 1006 is also physically and electrically coupled to the board 1002. In further implementations, the communication chip 1006 is part of the processor 1004.
[0052] Depending on its applications, computing device 1000 may include other components that may or may not be physically and electrically coupled to the board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
[0053] The communication chip 1006 enables wireless communications for the transfer of data to and from the computing device 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including but not limited to Wi- Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
[0054] The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as the PMOS device 110 and NMOS device 120 (Figure 1) in accordance with embodiments described elsewhere herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
[0055] The communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as the PMOS device 110 and NMOS device 120 (Figure 1) in accordance with embodiments described elsewhere herein.
[0056] In further implementations, another component housed within the computing device 1000 may contain an integrated circuit die that includes one or more devices, such as the PMOS device 110 and NMOS device 120, as illustrated in Figure 1 and described elsewhere herein.
[0057] In various implementations, the computing device 1000 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1000 may be any other electronic device that processes data.
[0058] It is to be understood that the above description is illustrative, and not restrictive. For example, while flow diagrams in the figures show a particular order of operations performed by certain embodiments of the invention, it should be understood that such order may not be required (e.g., alternative embodiments may perform the operations in a different order, combine certain operations, overlap certain operations, etc.). Furthermore, many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Although the present invention has been described with reference to specific exemplary embodiments, it will be recognized that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

CLAIMS What is claimed is:
1. A pair of semiconductor devices, comprising:
a first nanowire disposed over a substrate, wherein a longitudinal length of the first nanowire further comprises:
a first channel region of a group IV semiconductor material;
a first source region and a first drain region electrically coupled with the first channel region;
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the first channel region; and a second nanowire disposed over the substrate, the second nanowire further comprising:
a second channel region of a group III-V semiconductor material; a second source region and second drain region electrically coupled with the second channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the second channel region.
2. The pair of semiconductor devices of claim 1 , wherein the first source region and first drain region are p-type, and wherein the second source region and second drain region are n-type to render the pair of semiconductor devices complementary.
3. The pair of semiconductor devices of claim 1, wherein the group IV semiconductor material consists essentially of germanium (Ge).
4. The pair of semiconductor devices of claim 1 , wherein the longitudinal axis of the first channel region is disposed a first distance above the substrate and wherein the longitudinal axis of the second channel region is disposed a second distance above the substrate that is different from first distance.
5. The pair of semiconductor devices of claim 1, wherein the second distance is at least equal to the first distance added to a thickness of the first channel region along a direction orthogonal to the substrate.
6. The pair of semiconductor devices of claim 1, wherein the first nanowire is disposed within a first vertical stack of nanowires, wherein each nanowire in the first vertical stack has a channel region consisting essentially of the group IV material, and wherein two adjacent nanowires in the first vertical stack are physically joined at a location along the longitudinal length by an intervening crystalline semiconductor material different than the group IV material.
7. The pair of semiconductor devices of claim 6, wherein the intervening crystalline semiconductor material is disposed within a spacer region adjacent to the first gate stack.
8. The pair of semiconductor devices of claim 6, wherein the intervening crystalline semiconductor material is the group III-V semiconductor material.
9. The pair of semiconductor devices of claim 8, wherein the second nanowire is disposed within a second vertical stack of nanowires, wherein each nanowire in the second vertical stack has a channel region consisting essentially of the group III- V semiconductor material, and wherein two adjacent nanowires in the second vertical stack are physically joined at a location along the longitudinal length by a second intervening crystalline semiconductor material different than the group III-V semiconductor.
10. The pair of semiconductor devices of claim 9, wherein the intervening crystalline semiconductor material is the group III-V semiconductor material and wherein the second intervening crystalline semiconductor material is the group IV semiconductor material.
11. The pair of semiconductor devices of claim 10, wherein the two adjacent nanowires in the first vertical stack and the two adjacent nanowires in the second vertical stack are physically joined at a location along the longitudinal length by a third intervening crystalline semiconductor material that is different than either the group IV or group III-V semiconductor material.
12. The pair of semiconductor devices of claim 11, wherein the third intervening crystalline semiconductor material is a group IV semiconductor material.
13. The pair of semiconductor devices of claim 12, wherein the third intervening crystalline semiconductor material is SiGe.
14. A pair of complementary transistors, comprising:
a p-type transistor disposed over a substrate, wherein a longitudinal length of the p-type transistor further comprises:
a first channel region of a group IV semiconductor material;
a p-type source and drain region electrically coupled with the first channel region;
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the first channel region; and an n-type transistor disposed over the substrate, wherein a longitudinal length of the n-type transistor further comprises:
a second channel region of a group III-V semiconductor material; an n-type source and drain region electrically coupled with the first channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the second channel region.
15. The pair of complementary transistors wherein the group IV semiconductor material consists essentially of germanium (Ge) and wherein the group III-V semiconductor material consists essentially of one of: GaAs, InAs, InP, and a group III-N.
16. A method of forming a pair of semiconductor devices on a substrate, the method comprising:
disposing on a first region of the substrate a first stack of semiconductor layers including a crystalline group IV semiconductor layer overlying a first sacrificial layer;
disposing on a second region of the substrate a second stack of
semiconductor layers including a crystalline group III-V semiconductor layer overlying a second sacrificial layer;
etching the first stack to define a first nanowire comprising the group IV semiconductor layer;
etching the second stack to define a second nanowire comprising the group III-V semiconductor layer;
forming a first gate stack coaxially wrapping completely around the group IV crystalline layer along a longitudinal channel length of the first nanowire; and forming a second gate stack coaxially wrapping completely around the group III-V crystalline layer along a longitudinal channel length of the second nanowire.
17. The method of claim 16, further comprising:
forming a p-type source and drain region electrically coupled with a channel of the first nanowire; and
forming an n-type source and drain region electrically coupled with a channel of the second nanowire.
18. The method of claim 16, wherein etching the first stack of semiconductor layers further comprises removing the first sacrificial layer selectively to the group IV semiconductor layer to form a gap between the group IV semiconductor layer and the substrate along the longitudinal channel length; and
wherein etching the second stack of semiconductor layers further comprises removing the second sacrificial layer selectively to the group III-V semiconductor layer to form a gap between the group III-V semiconductor layer and the substrate along the longitudinal channel length.
19. The method of claim 16, wherein epitaxially growing the group IV semiconductor layer further comprises epitaxially growing a material consisting essentially of Ge; and
wherein epitaxially growing the group III-V semiconductor layer comprises growing a material consisting essentially of GaAs.
20. The method of claim 16, wherein the first sacrificial layer is the crystalline group III-V semiconductor layer and wherein the second sacrificial layer is the crystalline group IV semiconductor layer; and
wherein disposing the first and second stacks of semiconductor layers on the substrate comprises epitaxially growing the both the crystalline group III-V semiconductor layer and the crystalline group IV semiconductor layer over both the first and second regions of the substrate.
21. The method of claim 20, wherein etching the first stack of semiconductor layers further comprises removing the group III-V semiconductor layer selectively to the group IV semiconductor layer to form a gap between the group IV semiconductor layer and the substrate in the first region; and wherein
etching the second stack of semiconductor layers further comprises removing the group IV semiconductor layer selectively to the group III-V semiconductor layer to form a gap between the group III-V semiconductor layer and the substrate in the second region.
22. The method of claim 20, wherein disposing the first and second stacks of semiconductor layers on the substrate comprises epitaxially growing a third sacrificial layer over the substrate in the first and second regions; and
wherein etching the first stack of semiconductor layers further comprises removing the group III-V semiconductor layer and the third sacrificial layer selectively to the group IV semiconductor layer to form a gap between the group IV semiconductor layer and the substrate in the first region that is wider than a thickness of the group III-V semiconductor layer; and wherein etching the second stack of semiconductor layers further comprises removing the group IV semiconductor layer and the third sacrificial layer selectively to the group III-V semiconductor layer to form a gap between the group III-V semiconductor layer and the substrate in the second region that is wider than a thickness of the group IV semiconductor layer.
23. The method of claim 20, wherein epitaxially growing the group IV semiconductor layer further comprises epitaxially growing a material consisting essentially of Ge; and
wherein epitaxially growing the group III-V semiconductor layer comprises growing a material consisting essentially of GaAs; and
wherein epitaxially growing the third sacrificial layer comprises growing a material comprising SiGe or AlGaAs.
24. The method of claim 16, further comprising epitaxially growing a crystalline semiconductor transition layer coaxially wrapping completely around at least one of the group IV crystalline layer or group III-V crystalline layer.
25. The method of claim 16, wherein forming the first and second gate stacks further comprises depositing, by atomic layer deposition, a high-K dielectric material around a released portions of the first and second nanowire, and wherein forming the first gate stack further comprises depositing a first work function metal around the released portion of the first nanowire and wherein forming the second gate stack further comprises depositing a second work function metal around the released portion of the second nanowire.
PCT/US2011/065914 2011-12-19 2011-12-19 Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture WO2013095341A1 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
CN201710001499.1A CN106847814B (en) 2011-12-19 2011-12-19 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-wound architectures
PCT/US2011/065914 WO2013095341A1 (en) 2011-12-19 2011-12-19 Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
DE112011105970.1T DE112011105970B4 (en) 2011-12-19 2011-12-19 CMOS implementation from germanium and III-V nanowires and nanobelts in gate all-round architecture
CN201180075625.9A CN103999226B (en) 2011-12-19 2011-12-19 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US13/976,411 US9123567B2 (en) 2011-12-19 2011-12-19 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
TW101144770A TWI502729B (en) 2011-12-19 2012-11-29 Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
US14/798,380 US9666492B2 (en) 2011-12-19 2015-07-13 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US15/498,280 US10319646B2 (en) 2011-12-19 2017-04-26 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US16/372,272 US10784170B2 (en) 2011-12-19 2019-04-01 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/065914 WO2013095341A1 (en) 2011-12-19 2011-12-19 Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/976,411 A-371-Of-International US9123567B2 (en) 2011-12-19 2011-12-19 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US14/798,380 Division US9666492B2 (en) 2011-12-19 2015-07-13 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Publications (1)

Publication Number Publication Date
WO2013095341A1 true WO2013095341A1 (en) 2013-06-27

Family

ID=48669008

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/065914 WO2013095341A1 (en) 2011-12-19 2011-12-19 Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture

Country Status (5)

Country Link
US (4) US9123567B2 (en)
CN (2) CN106847814B (en)
DE (1) DE112011105970B4 (en)
TW (1) TWI502729B (en)
WO (1) WO2013095341A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104425495A (en) * 2013-08-20 2015-03-18 台湾积体电路制造股份有限公司 Silicon and silicon germanium nanowire formation
FR3033081A1 (en) * 2015-02-24 2016-08-26 Commissariat Energie Atomique METHOD FOR MODIFYING THE STRAIN STATUS OF A SEMICONDUCTOR STRUCTURE WITH TRANSISTOR CHANNEL STAGES
US9472471B1 (en) 2016-03-01 2016-10-18 International Business Machines Corporation Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS
TWI562376B (en) * 2013-09-27 2016-12-11 Intel Corp Composite high-k metal gate stack for enhancement mode gan semiconductor devices and fabrication method thereof
EP3112316A1 (en) * 2015-07-02 2017-01-04 IMEC vzw Method for manufacturing a transistor devices comprising multiple nanowire channels, and cmos devices
US9698239B2 (en) 2015-08-12 2017-07-04 International Business Machines Corporation Growing groups III-V lateral nanowire channels
US10535570B1 (en) 2018-06-22 2020-01-14 International Business Machines Corporation Cointegration of III-V channels and germanium channels for vertical field effect transistors
WO2020021913A1 (en) * 2018-07-26 2020-01-30 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device
US11404325B2 (en) 2013-08-20 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation

Families Citing this family (167)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013048417A1 (en) 2011-09-29 2013-04-04 Intel Corporation Electropositive metal containing layers for semiconductor applications
CN106847805B (en) * 2011-12-23 2020-08-21 英特尔公司 Common substrate semiconductor device with nanowires or semiconductor bodies having different material orientations or compositions
US9224810B2 (en) 2011-12-23 2015-12-29 Intel Corporation CMOS nanowire structure
US9224849B2 (en) * 2012-12-28 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with wrapped-around gates and methods for forming the same
CN103985751B (en) * 2013-02-08 2016-12-28 中国科学院微电子研究所 Semiconductor arrangement and method for the production thereof
US9006842B2 (en) 2013-05-30 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning strain in semiconductor devices
US9349850B2 (en) 2013-07-17 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally tuning strain in semiconductor devices
US9171843B2 (en) 2013-08-02 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
US9136332B2 (en) 2013-12-10 2015-09-15 Taiwan Semiconductor Manufacturing Company Limited Method for forming a nanowire field effect transistor device having a replacement gate
CN103700660A (en) * 2013-12-11 2014-04-02 中国科学院上海微系统与信息技术研究所 Whole annular grid CMOS (complementary metal oxide semiconductor) field effect transistor and preparing method
KR102162675B1 (en) 2013-12-16 2020-10-07 인텔 코포레이션 Nmos and pmos strained devices without relaxed substrates
EP4177950A1 (en) * 2013-12-18 2023-05-10 INTEL Corporation Heterogeneous layer device
CN103715195B (en) * 2013-12-27 2017-02-08 中国科学院上海微系统与信息技术研究所 Full annular grating CMOS structure based on silicon-based three-dimensional nano array and preparation method thereof
US9595525B2 (en) * 2014-02-10 2017-03-14 International Business Machines Corporation Semiconductor device including nanowire transistors with hybrid channels
US9257527B2 (en) * 2014-02-14 2016-02-09 International Business Machines Corporation Nanowire transistor structures with merged source/drain regions using auxiliary pillars
US9257450B2 (en) 2014-02-18 2016-02-09 Stmicroelectronics, Inc. Semiconductor device including groups of stacked nanowires and related methods
US10134759B2 (en) 2014-02-18 2018-11-20 Stmicroelectronics, Inc. Semiconductor device including groups of nanowires of different semiconductor materials and related methods
KR102178828B1 (en) * 2014-02-21 2020-11-13 삼성전자 주식회사 Semiconductor device including multiple nanowire transistor
CN103928482A (en) * 2014-03-31 2014-07-16 上海新储集成电路有限公司 CMOS nanowire transistor structure and preparing method
US9528194B2 (en) 2014-03-31 2016-12-27 Taiwan Semiconductor Manufacturing Company Limited & National Taiwan University Systems and methods for forming nanowires using anodic oxidation
US9953989B2 (en) 2014-03-31 2018-04-24 Taiwan Semiconductor Manufacturing Company Limited and National Taiwan University Antifuse array and method of forming antifuse using anodic oxidation
US10062426B2 (en) * 2014-04-24 2018-08-28 Micron Technology, Inc. Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery
KR102158963B1 (en) 2014-05-23 2020-09-24 삼성전자 주식회사 Semiconductor device and fabricated method thereof
US9331146B2 (en) * 2014-06-11 2016-05-03 International Business Machines Corporation Silicon nanowire formation in replacement metal gate process
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
US9502518B2 (en) * 2014-06-23 2016-11-22 Stmicroelectronics, Inc. Multi-channel gate-all-around FET
US9219154B1 (en) * 2014-07-15 2015-12-22 International Business Machines Corporation Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors
US9306019B2 (en) * 2014-08-12 2016-04-05 GlobalFoundries, Inc. Integrated circuits with nanowires and methods of manufacturing the same
TWI574414B (en) * 2014-09-01 2017-03-11 財團法人國家實驗研究院 Transistor structure
US9343529B2 (en) * 2014-09-05 2016-05-17 International Business Machines Corporation Method of formation of germanium nanowires on bulk substrates
KR102255174B1 (en) * 2014-10-10 2021-05-24 삼성전자주식회사 Semiconductor device having active region and method of forming the same
US10170549B2 (en) * 2014-10-21 2019-01-01 Samsung Electronics Co., Ltd. Strained stacked nanosheet FETs and/or quantum well stacked nanosheet
US9711414B2 (en) 2014-10-21 2017-07-18 Samsung Electronics Co., Ltd. Strained stacked nanosheet FETS and/or quantum well stacked nanosheet
US9406506B2 (en) 2014-11-05 2016-08-02 International Business Machines Corporation Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
US9287362B1 (en) 2014-11-21 2016-03-15 International Business Machines Corporation Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts
US9461114B2 (en) * 2014-12-05 2016-10-04 Samsung Electronics Co., Ltd. Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same
CN105762190B (en) * 2014-12-19 2019-04-19 中国科学院微电子研究所 Semiconductor device and method for manufacturing the same
US9287360B1 (en) * 2015-01-07 2016-03-15 International Business Machines Corporation III-V nanowire FET with compositionally-graded channel and wide-bandgap core
CN104695020B (en) * 2015-03-05 2017-03-01 湖南大学 A kind of strip InAs nano belt and its preparation and application
US9780166B2 (en) 2015-03-30 2017-10-03 International Business Machines Corporation Forming multi-stack nanowires using a common release material
CN106158859B (en) * 2015-04-09 2019-07-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof
US9793403B2 (en) 2015-04-14 2017-10-17 Samsung Electronics Co., Ltd. Multi-layer fin field effect transistor devices and methods of forming the same
US9437502B1 (en) * 2015-06-12 2016-09-06 International Business Machines Corporation Method to form stacked germanium nanowires and stacked III-V nanowires
US9647071B2 (en) * 2015-06-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. FINFET structures and methods of forming the same
KR102377909B1 (en) * 2015-06-27 2022-03-23 인텔 코포레이션 GE Nanowire Transistors with GAAS as Sacrificial Layer
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
EP3125273B1 (en) 2015-07-31 2024-08-28 IMEC vzw Strained group iv channels
US9647139B2 (en) 2015-09-04 2017-05-09 International Business Machines Corporation Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
CN108028274B (en) * 2015-09-10 2021-09-03 英特尔公司 Semiconductor nanowire device and method for manufacturing the same
US10411090B2 (en) * 2015-09-24 2019-09-10 Intel Corporation Hybrid trigate and nanowire CMOS device architecture
EP3353812A4 (en) * 2015-09-25 2019-05-08 Intel Corporation Nanowire transistor device architectures
US9484405B1 (en) * 2015-09-29 2016-11-01 International Business Machines Corporation Stacked nanowire devices formed using lateral aspect ratio trapping
US9853101B2 (en) 2015-10-07 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained nanowire CMOS device and method of forming
CN106601738B (en) * 2015-10-15 2018-08-24 上海新昇半导体科技有限公司 Complementary field-effect transist and preparation method thereof
US10032678B2 (en) 2015-10-15 2018-07-24 Qualcomm Incorporated Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices
US9685564B2 (en) 2015-10-16 2017-06-20 Samsung Electronics Co., Ltd. Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US20200258740A1 (en) * 2015-11-16 2020-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Forming Stacked Nanowire Transistors
US9754840B2 (en) * 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
US10032627B2 (en) 2015-11-16 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming stacked nanowire transistors
US10204985B2 (en) * 2015-11-16 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9887269B2 (en) * 2015-11-30 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
KR102434993B1 (en) * 2015-12-09 2022-08-24 삼성전자주식회사 Semiconductor device
US9425291B1 (en) 2015-12-09 2016-08-23 International Business Machines Corporation Stacked nanosheets by aspect ratio trapping
US9431301B1 (en) 2015-12-10 2016-08-30 International Business Machines Corporation Nanowire field effect transistor (FET) and method for fabricating the same
US9412849B1 (en) 2015-12-11 2016-08-09 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
CN106887409B (en) * 2015-12-15 2020-02-21 上海新昇半导体科技有限公司 Complementary nanowire semiconductor device and manufacturing method thereof
CN106910716B (en) * 2015-12-22 2021-10-15 Imec 非营利协会 Method of fabricating Si-based high mobility CMOS devices and resulting devices
KR102366953B1 (en) 2016-01-06 2022-02-23 삼성전자주식회사 Semiconductor device and method of fabricating the same
CN106960870B (en) 2016-01-11 2021-09-10 三星电子株式会社 Semiconductor device and method for manufacturing the same
US9484267B1 (en) 2016-02-04 2016-11-01 International Business Machines Corporation Stacked nanowire devices
US10062693B2 (en) * 2016-02-24 2018-08-28 International Business Machines Corporation Patterned gate dielectrics for III-V-based CMOS circuits
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108701653B (en) * 2016-02-25 2022-07-29 株式会社索思未来 Semiconductor integrated circuit device having a plurality of semiconductor chips
KR102461174B1 (en) * 2016-02-26 2022-11-01 삼성전자주식회사 Semiconductor device
KR102476143B1 (en) 2016-02-26 2022-12-12 삼성전자주식회사 Semiconductor device
US9748404B1 (en) * 2016-02-29 2017-08-29 International Business Machines Corporation Method for fabricating a semiconductor device including gate-to-bulk substrate isolation
US9755017B1 (en) * 2016-03-01 2017-09-05 International Business Machines Corporation Co-integration of silicon and silicon-germanium channels for nanosheet devices
DE112016006574T5 (en) * 2016-03-11 2018-11-29 Intel Corporation TECHNIQUES FOR TRAINING TRANSISTORS THAT HAVE GROUP III V MATERIAL NANODRICKS USING GROUP IV MATERIAL PHOTO STENCILS
US10439039B2 (en) * 2016-03-25 2019-10-08 Qualcomm Incorporated Integrated circuits including a FinFET and a nanostructure FET
KR102506426B1 (en) * 2016-06-07 2023-03-08 삼성전자주식회사 Semiconductor device
WO2018004607A1 (en) * 2016-06-30 2018-01-04 Intel Corporation Co-integration of gan and self-aligned thin body group iv transistors
US10134905B2 (en) 2016-06-30 2018-11-20 International Business Machines Corporation Semiconductor device including wrap around contact, and method of forming the semiconductor device
TWI744358B (en) 2016-07-19 2021-11-01 日商東京威力科創股份有限公司 Three-dimensional semiconductor device and method of fabrication
TWI731138B (en) * 2016-08-08 2021-06-21 日商東京威力科創股份有限公司 Three-dimensional semiconductor device and method of fabrication
US9842914B1 (en) * 2016-08-19 2017-12-12 International Business Machines Corporation Nanosheet FET with wrap-around inner spacer
US10332986B2 (en) 2016-08-22 2019-06-25 International Business Machines Corporation Formation of inner spacer on nanosheet MOSFET
US9905643B1 (en) 2016-08-26 2018-02-27 International Business Machines Corporation Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
JP7164289B2 (en) 2016-09-05 2022-11-01 東京エレクトロン株式会社 Position-Specific Tuning of Bow-Controlling Stress to Control Overlay During Semiconductor Processing
US9704863B1 (en) 2016-09-09 2017-07-11 International Business Machines Corporation Forming a hybrid channel nanosheet semiconductor structure
US9876088B1 (en) * 2016-09-19 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. III-V semiconductor layers, III-V semiconductor devices and methods of manufacturing thereof
US9853114B1 (en) 2016-10-24 2017-12-26 Samsung Electronics Co., Ltd. Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
US10312152B2 (en) 2016-10-24 2019-06-04 Samsung Electronics Co., Ltd. Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
US10177226B2 (en) 2016-11-03 2019-01-08 International Business Machines Corporation Preventing threshold voltage variability in stacked nanosheets
US10170378B2 (en) * 2016-11-29 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gate all-around semiconductor device and manufacturing method thereof
CN108231589B (en) * 2016-12-09 2020-06-05 Imec 非营利协会 Formation of internal spacers in nanowire semiconductor devices
US10002922B1 (en) * 2016-12-14 2018-06-19 Taiwan Semiconductor Manufacturing Company Process to etch semiconductor materials
KR102574454B1 (en) 2016-12-16 2023-09-04 삼성전자 주식회사 Semiconductor devices and method of manufacturing the same
US9972542B1 (en) 2017-01-04 2018-05-15 International Business Machines Corporation Hybrid-channel nano-sheet FETs
KR102564325B1 (en) * 2017-01-04 2023-08-07 삼성전자주식회사 Semiconductor devices having channel regions
US9825143B1 (en) * 2017-01-09 2017-11-21 International Business Machines Corporation Single spacer tunnel on stack nanowire
CN108305897A (en) * 2017-01-11 2018-07-20 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacturing method
KR102363250B1 (en) 2017-03-23 2022-02-16 삼성전자주식회사 Semiconductor device
KR102318560B1 (en) * 2017-04-12 2021-11-01 삼성전자주식회사 Semiconductor device
US10930793B2 (en) 2017-04-21 2021-02-23 International Business Machines Corporation Bottom channel isolation in nanosheet transistors
US10573564B2 (en) 2017-04-27 2020-02-25 Tokyo Electron Limited Method for fabricating NFET and PFET nanowire devices
KR102293127B1 (en) * 2017-06-23 2021-08-26 삼성전자주식회사 Semiconductor device and method for manufacturing the same
US10276728B2 (en) 2017-07-07 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including non-volatile memory cells
DE102017126225A1 (en) * 2017-08-31 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
US10297508B2 (en) * 2017-08-31 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
WO2019059894A1 (en) * 2017-09-19 2019-03-28 Intel Corporation Multi-channel vertical transistor for embedded non-volatile memory
US10497624B2 (en) * 2017-09-29 2019-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
DE102018108821A1 (en) * 2017-09-29 2019-04-04 Taiwan Semiconductor Manufacturing Co. Ltd. METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
US10170304B1 (en) 2017-10-25 2019-01-01 Globalfoundries Inc. Self-aligned nanotube structures
US10340363B2 (en) * 2017-11-06 2019-07-02 International Business Machines Corporation Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers
JP6877319B2 (en) * 2017-11-15 2021-05-26 ルネサスエレクトロニクス株式会社 Semiconductor devices and their manufacturing methods
US10700066B2 (en) * 2017-11-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10685887B2 (en) * 2017-12-04 2020-06-16 Tokyo Electron Limited Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device
US10833078B2 (en) * 2017-12-04 2020-11-10 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
US10566330B2 (en) 2017-12-11 2020-02-18 Samsung Electronics Co., Ltd. Dielectric separation of partial GAA FETs
CN108172546B (en) * 2017-12-22 2020-06-23 中国科学院微电子研究所 CMOS nanowire and manufacturing method thereof
WO2019132865A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Heterogeneous ge/iii-v cmos transistor structures
US20190221483A1 (en) * 2018-01-12 2019-07-18 Globalfoundries Inc. Single work function enablement for silicon nanowire device
US11387238B2 (en) * 2018-03-02 2022-07-12 Intel Corporation Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices
US11081567B2 (en) 2018-03-12 2021-08-03 International Business Machines Corporation Replacement-channel fabrication of III-V nanosheet devices
TWI800626B (en) * 2018-03-19 2023-05-01 日商東京威力科創股份有限公司 Three-dimensional device and method of forming the same
US10424639B1 (en) 2018-04-19 2019-09-24 International Business Machines Corporation Nanosheet transistor with high-mobility channel
US10388755B1 (en) 2018-06-04 2019-08-20 International Business Machines Corporation Stacked nanosheets with self-aligned inner spacers and metallic source/drain
US10461154B1 (en) * 2018-06-21 2019-10-29 International Business Machines Corporation Bottom isolation for nanosheet transistors on bulk substrate
US10332809B1 (en) * 2018-06-21 2019-06-25 International Business Machines Corporation Method and structure to introduce strain in stack nanosheet field effect transistor
US11043556B2 (en) 2018-06-26 2021-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Local epitaxy nanofilms for nanowire stack GAA device
KR102515393B1 (en) 2018-06-29 2023-03-30 삼성전자주식회사 Semiconductor devices and methods of manufacturing the same
KR102513084B1 (en) 2018-08-27 2023-03-24 삼성전자주식회사 Semiconductor devices
WO2020055642A2 (en) * 2018-09-05 2020-03-19 Tokyo Electron Limited Power distribution network for 3d logic and memory
WO2020051144A1 (en) 2018-09-05 2020-03-12 Tokyo Electron Limited Architecture design and processes for manufacturing monolithically integrated 3d cmos logic and memory
US11069818B2 (en) * 2018-09-14 2021-07-20 Samsung Electronics Co., Ltd. Semiconductor device
CN110970369B (en) * 2018-09-30 2022-08-02 中芯国际集成电路制造(上海)有限公司 CMOS inverter structure and forming method thereof
US11043493B2 (en) * 2018-10-12 2021-06-22 International Business Machines Corporation Stacked nanosheet complementary metal oxide semiconductor field effect transistor devices
KR20200057125A (en) * 2018-11-15 2020-05-26 삼성전자주식회사 Semiconductor device
US10607847B1 (en) * 2018-12-03 2020-03-31 Applied Materials, Inc. Gate all around device and method of formation using angled ions
US11532619B2 (en) * 2019-03-27 2022-12-20 Intel Corporation Transistor structures including a non-planar body having variable and complementary semiconductor and insulator portions
US11088255B2 (en) 2019-05-17 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices
US11088034B2 (en) 2019-05-22 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structures for semiconductor devices
KR20210000780A (en) * 2019-06-25 2021-01-06 삼성전자주식회사 Semiconductor devices
US20210005604A1 (en) * 2019-07-03 2021-01-07 Qualcomm Incorporated Nanosheet Transistor Stack
US11887988B2 (en) 2019-08-01 2024-01-30 Intel Corporation Thin film transistor structures with regrown source and drain
US11574845B2 (en) * 2019-08-07 2023-02-07 Tokyo Electron Limited Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices
TWI819068B (en) 2019-08-16 2023-10-21 聯華電子股份有限公司 Semiconductor device and manufacturing method thereof
WO2021048995A1 (en) * 2019-09-13 2021-03-18 株式会社日立ハイテク Semiconductor device manufacturing method and plasma processing device
US11177259B2 (en) 2019-09-27 2021-11-16 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-threshold gate structure with doped gate dielectric layer
US11404416B2 (en) 2019-12-17 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Low resistance fill metal layer material as stressor in metal gates
US11257933B2 (en) * 2019-12-19 2022-02-22 Institute of Microelectronics, Chinese Academy Semiconductor device and method for manufacturing the same
US11164785B2 (en) * 2019-12-27 2021-11-02 Intel Corporation Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material
US11328988B2 (en) 2019-12-27 2022-05-10 Intel Corporation Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication
US11244943B2 (en) 2019-12-27 2022-02-08 Intel Corporation Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
US11251182B2 (en) 2020-03-17 2022-02-15 International Business Machines Corporation Staggered stacked vertical crystalline semiconducting channels
US11798851B2 (en) 2020-04-14 2023-10-24 International Business Machines Corporation Work function metal patterning for nanosheet CFETs
US12015066B2 (en) * 2020-06-17 2024-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Triple layer high-k gate dielectric stack for workfunction engineering
US11335683B2 (en) * 2020-06-30 2022-05-17 Qualcomm Incorporated Device channel profile structure
KR20220005746A (en) * 2020-07-07 2022-01-14 삼성전자주식회사 Semiconductor device
KR20220010662A (en) 2020-07-17 2022-01-26 삼성전자주식회사 Semiconductor devices
KR20220016332A (en) 2020-07-30 2022-02-09 삼성전자주식회사 Semiconductor device
US11916070B2 (en) * 2020-10-22 2024-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure with nanosheets
CN112768514B (en) * 2021-01-19 2022-11-25 泉芯集成电路制造(济南)有限公司 Full-surrounding gate vertical penetration transistor and preparation method thereof
CN113257920B (en) * 2021-04-29 2024-03-08 中国科学院微电子研究所 Nanowire/sheet device with support portion, method of manufacturing the same, and electronic apparatus
CN114628523B (en) * 2022-01-25 2023-03-21 深圳大学 Gallium nitride-based CMOS field effect transistor and preparation method thereof
WO2024183056A1 (en) * 2023-03-09 2024-09-12 西安电子科技大学 Nano-channel gan-based device and manufacturing method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060240622A1 (en) * 2005-04-21 2006-10-26 Samsung Electronics Co., Ltd. Multi-channel semiconductor device and method of manufacturing the same
US20100059807A1 (en) * 2008-09-05 2010-03-11 Samsung Electronics Co., Ltd. Semiconductor device having bar type active pattern
US7892945B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000150535A (en) * 1998-11-09 2000-05-30 Fujitsu Quantum Device Kk Field effect transistor and manufacture thereof
US7101761B2 (en) * 2003-12-23 2006-09-05 Intel Corporation Method of fabricating semiconductor devices with replacement, coaxial gate structure
KR100594327B1 (en) * 2005-03-24 2006-06-30 삼성전자주식회사 Semiconductor device comprising nanowire having rounded section and method for manufacturing the same
FR2884648B1 (en) * 2005-04-13 2007-09-07 Commissariat Energie Atomique STRUCTURE AND METHOD FOR PRODUCING A MICROELECTRONIC DEVICE HAVING ONE OR MORE QUANTUM THREADS FOR FORMING A CHANNEL OR MORE CHANNELS OF TRANSISTORS
US20070090416A1 (en) * 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
JP4310399B2 (en) * 2006-12-08 2009-08-05 株式会社東芝 Semiconductor device and manufacturing method thereof
CN101556922B (en) * 2008-04-10 2010-07-28 北京大学 Nano surrounding-gate MOSFET transistor and preparation method thereof
JP4724231B2 (en) * 2009-01-29 2011-07-13 株式会社東芝 Semiconductor device and manufacturing method thereof
FR2950481B1 (en) * 2009-09-18 2011-10-28 Commissariat Energie Atomique IMPLEMENTATION OF A MICROELECTRONIC DEVICE COMPRISING SILICON AND GERMANIUM NANO-WIRES INTEGRATED ON THE SAME SUBSTRATE
CN102034863B (en) * 2009-09-28 2012-10-31 中芯国际集成电路制造(上海)有限公司 Semiconductor device, transistor having gate of around cylindrical channel and manufacturing method
CN101719498B (en) * 2009-12-01 2011-09-07 中国科学院上海微系统与信息技术研究所 Composite material inversion mode all-around-gate CMOS field effect cylindrical transistor
US8455334B2 (en) 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US8183104B2 (en) * 2010-07-07 2012-05-22 Hobbs Christopher C Method for dual-channel nanowire FET device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060240622A1 (en) * 2005-04-21 2006-10-26 Samsung Electronics Co., Ltd. Multi-channel semiconductor device and method of manufacturing the same
US20100059807A1 (en) * 2008-09-05 2010-03-11 Samsung Electronics Co., Ltd. Semiconductor device having bar type active pattern
US7892945B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170194215A1 (en) * 2013-08-20 2017-07-06 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US20160056236A1 (en) * 2013-08-20 2016-02-25 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US11854905B2 (en) 2013-08-20 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation
US11404325B2 (en) 2013-08-20 2022-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon and silicon germanium nanowire formation
US10943833B2 (en) 2013-08-20 2021-03-09 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US10699964B2 (en) 2013-08-20 2020-06-30 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US9634091B2 (en) 2013-08-20 2017-04-25 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US9935016B2 (en) * 2013-08-20 2018-04-03 Taiwan Semiconductor Manufacturing Company Ltd. Silicon and silicon germanium nanowire formation
CN104425495A (en) * 2013-08-20 2015-03-18 台湾积体电路制造股份有限公司 Silicon and silicon germanium nanowire formation
TWI562376B (en) * 2013-09-27 2016-12-11 Intel Corp Composite high-k metal gate stack for enhancement mode gan semiconductor devices and fabrication method thereof
US9853130B2 (en) 2015-02-24 2017-12-26 Commissariat á l'énergie atomique et aux énergies alternatives Method of modifying the strain state of a semiconducting structure with stacked transistor channels
FR3033081A1 (en) * 2015-02-24 2016-08-26 Commissariat Energie Atomique METHOD FOR MODIFYING THE STRAIN STATUS OF A SEMICONDUCTOR STRUCTURE WITH TRANSISTOR CHANNEL STAGES
EP3062350A1 (en) * 2015-02-24 2016-08-31 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for modifying the state of stress of a semiconductor structure with transistor channel stages
US9842777B2 (en) 2015-07-02 2017-12-12 Imec Vzw Semiconductor devices comprising multiple channels and method of making same
EP3112316A1 (en) * 2015-07-02 2017-01-04 IMEC vzw Method for manufacturing a transistor devices comprising multiple nanowire channels, and cmos devices
US10763340B2 (en) 2015-08-12 2020-09-01 International Business Machines Corporation Growing Groups III-V lateral nanowire channels
US9698239B2 (en) 2015-08-12 2017-07-04 International Business Machines Corporation Growing groups III-V lateral nanowire channels
US9859397B2 (en) 2015-08-12 2018-01-02 International Business Machines Corporation Growing groups III-V lateral nanowire channels
US10103242B2 (en) 2015-08-12 2018-10-16 International Business Machines Corporation Growing groups III-V lateral nanowire channels
US9472471B1 (en) 2016-03-01 2016-10-18 International Business Machines Corporation Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS
US9659829B1 (en) 2016-03-01 2017-05-23 International Business Machines Corporation Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS
US10535570B1 (en) 2018-06-22 2020-01-14 International Business Machines Corporation Cointegration of III-V channels and germanium channels for vertical field effect transistors
WO2020021913A1 (en) * 2018-07-26 2020-01-30 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device
US11476329B2 (en) 2018-07-26 2022-10-18 Sony Semiconductor Solutions Corporation Semiconductor device
US11961885B2 (en) 2018-07-26 2024-04-16 Sony Semiconductor Solutions Corporation Semiconductor device

Also Published As

Publication number Publication date
US10319646B2 (en) 2019-06-11
US10784170B2 (en) 2020-09-22
US20190229022A1 (en) 2019-07-25
TWI502729B (en) 2015-10-01
US20130270512A1 (en) 2013-10-17
US20150325481A1 (en) 2015-11-12
US9666492B2 (en) 2017-05-30
US20170229354A1 (en) 2017-08-10
TW201403792A (en) 2014-01-16
DE112011105970T5 (en) 2014-09-25
CN106847814A (en) 2017-06-13
CN106847814B (en) 2020-12-08
CN103999226A (en) 2014-08-20
CN103999226B (en) 2017-02-15
DE112011105970B4 (en) 2020-12-03
US9123567B2 (en) 2015-09-01

Similar Documents

Publication Publication Date Title
US10784170B2 (en) CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
US11616015B2 (en) Integrated circuit device with back-side interconnection to deep source/drain semiconductor
US11380684B2 (en) Stacked transistor architecture including nanowire or nanoribbon thin film transistors
US9935205B2 (en) Internal spacers for nanowire transistors and method of fabrication thereof
US10840352B2 (en) Nanowire transistors with embedded dielectric spacers
KR101950120B1 (en) Non-planar semiconductor device having channel region with low band-gap cladding layer
CN110660797A (en) Isolation scheme for full-ring gate transistor devices
US20230207700A1 (en) Integrated circuit structures having partitioned source or drain contact structures
US11329162B2 (en) Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures
WO2017171845A1 (en) Beaded fin transistor
US11387238B2 (en) Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices
TWI781952B (en) Integrated circuit and method of forming the same, and complementary metal-oxide-semiconductor device
TWI805555B (en) Semiconductor circuit structure
US20240332302A1 (en) Integrated circuit structures with backside conductive source or drain contact having enhanced contact area

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13976411

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11877834

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 112011105970

Country of ref document: DE

Ref document number: 1120111059701

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11877834

Country of ref document: EP

Kind code of ref document: A1