WO2007119265A1

WO2007119265A1 - Stress-applied semiconductor device and method for manufacturing same

Info

Publication number: WO2007119265A1
Application number: PCT/JP2006/305608
Authority: WO
Inventors: Akira Katakami; Hiroshi Morioka
Original assignee: Fujitsu Limited
Priority date: 2006-03-20
Filing date: 2006-03-20
Publication date: 2007-10-25
Also published as: JPWO2007119265A1; JP5168140B2

Abstract

Disclosed is a stress-applied semiconductor device comprising a gate electrode formed on a silicon substrate via a gate insulating film, a first and a second groove formed apart from each other in the silicon substrate respectively on a first and a second side of the gate electrode, and epitaxial layers respectively having a first and a second conductivity type which are composed of a mixed crystal of Si and another group IV element and respectively filled into the first and second grooves. In this stress-applied semiconductor device, the gate electrode is made of a polycrystalline substance composed of a mixed crystal of Si and another element.

Description

Specification

Stress applying semiconductor device and manufacturing method thereof

Technical field

TECHNICAL FIELD [0001] The present invention generally relates to a semiconductor device, and more particularly, to a stress-applying semiconductor device in which an operation speed is improved by applying strain and a manufacturing method thereof. Background art

[0002] With the advancement of miniaturization technology, ultra-miniaturized 'ultra-high-speed semiconductor devices having a gate length of 30 nm or less are now possible.

[0003] In such ultra-miniaturized / high-speed transistors, the area of the channel region directly below the gate electrode is very small compared to conventional semiconductor devices. Therefore, the electrons or holes traveling in the channel region are small. Mobility is greatly affected by the stress applied to such channel regions. Therefore, many attempts have been made to improve the operation speed of the semiconductor device by optimizing the stress applied to the channel region.

Disclosure of the invention

Problems to be solved by the invention

[0004] In particular, p-channel MOS transistors are known to improve carrier mobility by applying uniaxial compressive stress to the channel region. As a means for applying compressive stress to the channel region, The schematic configuration shown in Fig. 1 has been proposed.

Referring to FIG. 1, a gate electrode 3 is formed on a silicon substrate 1 corresponding to a channel region via a gate insulating film 2, and the gate electrode 3 is formed in the silicon substrate 1. The p-type diffusion regions la and lb are formed so as to define channel regions on both sides of the substrate. Further, side wall insulating films 3A and 3B are formed on the side wall of the gate electrode 3 so as to cover a part of the surface of the silicon substrate 1.

[0006] The diffusion regions la and lb act as source and drain etching regions of the MOS transistor, respectively, and holes transported through the channel region directly below the gate electrode 3 from the diffusion region la to lb. The flow is controlled by the gate voltage applied to the gate electrode 3. In the configuration of FIG. 1, SiGe mixed crystal layers 1 A and 1 B are further formed on the silicon substrate 1 on the outer side of the sidewall insulating films 3 A and 3 B, respectively, with respect to the silicon substrate 1. In the SiGe mixed crystal layers 1A and 1B, P-type source and drain regions continuous with the diffusion regions la and lb are formed, respectively.

In the MOS transistor having the configuration of FIG. 1, since the SiGe mixed crystal layers 1A and 1B have a larger lattice constant than the silicon substrate 1, the SiGe mixed crystal layers 1A and IB are indicated by arrows a. As a result, compressive stress is formed, and as a result, the SiGe mixed crystal layers 1A and IB are distorted in a direction substantially perpendicular to the surface of the silicon substrate 1 indicated by an arrow b.

[0009] Since the SiGe mixed crystal layers 1A and IB are formed epitaxially with respect to the silicon substrate 1, the strain in the SiGe mixed crystal layers 1A and 1B indicated by the arrow b is a corresponding strain. The channel region in the silicon substrate is induced as indicated by an arrow c. Along with this strain, a uniaxial compressive stress is induced in the channel region as indicated by an arrow d.

In the MOS transistor of FIG. 1, as a result of such uniaxial compressive stress being applied to the channel region, the symmetry of the Si crystal constituting the channel region is locally modulated, and this symmetry is further applied. As the characteristics change, the degeneration of the valence band of heavy holes and the valence band of light holes can be solved, so that the hole mobility in the channel region increases and the operation speed of the transistor improves. The increase in hole mobility and the accompanying increase in transistor operation speed due to the locally induced stress in the channel region are particularly noticeable in ultra-miniaturized semiconductor devices having a gate length of lOOnm or less.

On the other hand, in an n-channel MOS transistor, on the contrary, it is known that applying an in-plane tensile stress to the channel region is effective in improving the operation speed. For example, as shown in FIG. A configuration has been proposed in which a stress film in which tensile stress is accumulated is provided on the gate electrode, and the gate electrode is pressed against the channel region in the silicon substrate.

Referring to FIG. 2, an n ⁺ -type polysilicon gate electrode 13 is formed on a silicon substrate 11 via a gate insulating film 12, and the polysilicon gate electrode 13 in the silicon substrate 11 is formed. On each side, an n-type source extension region 11a and a drain extension region 1 lb are formed. In addition, a sidewall insulating film 14N made of a SiN film is formed on both side wall surfaces of the gate electrode 13 via a sidewall oxide film 140x, and the sidewall insulating film 14N in the silicon substrate 11 is formed. An n ⁺ -type source region 1 lc and a drain region 1 Id are formed in the outer portion.

[0014] Silicide films 15S, 15D, and 15G are formed on the source region 11c, the drain region lld, and the gate electrode 13, respectively, and the silicide film is further formed on the silicon substrate 11. A SiN film 16 in which tensile stress is accumulated is formed so as to continuously cover the films 15S, 15D, 15G and the sidewall insulating film 14N.

The gate electrode 13 is urged in a direction perpendicular to the substrate surface toward the silicon substrate 11 by the action of tensile force of the SiN film 16 due to force, and as a result, the gate electrode 13 is directly below the gate electrode 13. The same strain as that when tensile stress is applied in the gate length direction is induced in the channel region.

[0016] Due to such tensile stress strain, the mobility of electrons increases in the channel region, and the operating speed of the n-channel MOS transistor is improved.

[0017] On the other hand, if the stress value in the channel region can be further increased in such a conventional p-channel or n-channel MOS transistor, it is considered that the operation speed can be further improved.

Means for solving the problem

[0018] In one aspect, the present invention provides a silicon substrate, a gate electrode formed on the silicon substrate via a gate insulating film, and on the first and second sides of the gate electrode in the silicon substrate. The first and second groove portions formed separately from each other, and the first and second groove portions made of a mixed crystal of Si and another group IV element and filling the first and second groove portions, respectively. A stress-applying semiconductor device, wherein the gate electrode is a polycrystal made of a mixed crystal of Si and another element.

In another aspect, the present invention provides a step of forming a first polycrystalline film made of a mixed crystal of Si and another element on a silicon substrate via a first insulating film; Forming a second polycrystalline film having a concentration of the other element higher than that of the first polycrystalline film on the polycrystalline film through a second insulating film; and the first and second A polycrystalline film of the same material as the second insulating film. The first polycrystalline pattern having the first width and the second polycrystalline pattern having the first width are formed on the silicon substrate by the insulating film pattern having the first width. A step of forming a laminated structure laminated via a turn, and isotropic etching is performed on the laminated structure, and the width of the second polycrystalline pattern is changed from the first width to the second width. A step of selectively reducing the first polycrystalline pattern, and anisotropic etching is performed on the silicon substrate using the first polycrystalline pattern as a mask. Forming the first and second grooves on the first and second sides of the laminated structure, respectively, and using the second polycrystalline pattern as a mask, the insulating film pattern and the first polycrystalline pattern Anisotropic etching and the first step And filling the second groove with first and second semiconductor layers made of a mixed crystal of Si and another group IV element in an epitaxial manner. Provide a method. The invention's effect

According to the present invention, the silicon substrate is anisotropically etched in the direction perpendicular to the substrate surface using the first polycrystalline pattern having the first width as a mask, and the second polycrystalline pattern having the second width is used. The first polycrystalline pattern is anisotropically etched in the direction perpendicular to the substrate surface using the first and second masks as masks, so that the first polycrystalline pattern is formed on both sides of the region where the first polycrystalline pattern is formed in the silicon substrate. And the second groove portion is formed, and the gate electrode is formed in the center portion of the region in a self-aligned manner with a desired gate length by the first polycrystalline pattern. At this time, the second polycrystalline pattern is obtained by selectively laterally etching the second polycrystalline film pattern on the first polycrystalline film pattern with respect to the first polycrystalline pattern, It should be noted that it is formed in a self-aligned manner in the central portion of the region. Therefore, the first polycrystalline pattern is anisotropically etched in the direction perpendicular to the substrate using the second polycrystalline pattern formed in this manner as a mask, so that the desired gate electrode is formed into the first polycrystalline pattern. The pattern makes it possible to reliably form the central portion of the region. Thus, the first or second epitaxial semiconductor layer acting as a source of compressive or tensile stress to the first or second groove, and thus to the channel region of the semiconductor device, is 20 nm from the side wall surface of the gate electrode. It is possible to form the following close distances, increasing the stress applied to the channel region of the stress application semiconductor device. It is possible to force S. That is, according to the present invention, the operation speed of the semiconductor device can be improved with a simple configuration and process.

In the present invention, the Ge concentration in the first polycrystalline pattern serving as the gate electrode is stepped in the film thickness direction by utilizing the fact that the etching rate of the SiGe mixed crystal layer varies with the Ge concentration. Alternatively, by continuously changing, the opposing side wall surfaces of the first and second groove portions can be formed in a shape inclined toward opposite directions. At this time, the shape of the side wall surface becomes a stepped surface or a continuous surface depending on whether the Ge concentration change in the first polycrystalline pattern is stepped or continuous. As a result, in the vicinity of the interface between the gate insulating film and the silicon substrate where the effect of applying stress to the channel region is large, the first and second semiconductor layer regions serving as stress sources are formed closest to each other. Is easily obtained.

Brief Description of Drawings

FIG. 1 is a diagram showing a configuration of a stress applying semiconductor device according to a related technique of the present invention.

FIG. 2 is a diagram showing a configuration of a stress applying semiconductor device according to another related technique of the present invention.

FIG. 3A is a view (No. 1) showing a step of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3B is a diagram (part 2) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3C is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 3D is a diagram (part 4) illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 3E is a view (No. 5) showing a step of manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 3F is a view (No. 6) showing a step of manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3G is a view (No. 7) showing a step of manufacturing a semiconductor device according to the first embodiment of the present invention; FIG. 3H is a view (No. 8) showing a step of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a graph showing the relationship between the etching rate of the SiGe mixed crystal layer and the Ge concentration.

FIG. 5A is a view (No. 1) showing a step of manufacturing a semiconductor device according to the second embodiment of the invention.

FIG. 5B is a diagram (part 2) illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 5C is a view (No. 3) illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 5D is a view (No. 4) showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 5E is a view (No. 5) showing a step of manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 5F is a view (No. 6) showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 5G is a view (No. 7) showing a step of manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 6A is a view (No. 1) showing a step of manufacturing a semiconductor device according to a third embodiment of the invention.

FIG. 6B is a diagram (part 2) illustrating the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 6C is a view (No. 3) illustrating the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

FIG. 6D is a view (No. 4) showing a step of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 6E is a view (No. 5) showing a step of manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 6F is a view (No. 6) showing a manufacturing step of the semiconductor device according to the third embodiment of the invention. The

FIG. 6G is a view (No. 7) showing a step of manufacturing a semiconductor device according to the third embodiment of the present invention;

Explanation of symbols

[0023] 20, 40, 60 Semiconductor device

21 Board

21 A element area

211 Element isolation region

21TA, 21TB, 41TA, 41TB, 61TA, 61TB Groove

21a, 21b Source / drain extension region

21c, 2 Id Source / drain region

21ta, 21tb, 41ta, 41tb, 61ta, 61tb groove side wall

22, 22A Gate insulation film

23, 23a-23d, 25, 43, 63 SiGe mixed crystal layer

23 A, 25 A, 25 B, 43 A, 43 B, 63 A, 63 B SiGe mixed crystal layer. Turn

23B, 43C, 63C SiGe mixed crystal gate electrode

24 Insulating film

24A, 24B, 24C Insulating film pattern

25A, 25B regrown SiGe mixed crystal layer

26A ~ 26C Si cap film

27A ~ 27C Silicide layer

26 Anti-reflective coating

R1 resist pattern

BEST MODE FOR CARRYING OUT THE INVENTION

[0024] [First embodiment]

3A to 3H are diagrams showing a manufacturing process of the p-channel MOS transistor 20 according to the first embodiment of the present invention.

Referring to FIG. 3A, element region 21A is formed on silicon substrate 21 by element isolation region 211. A silicon oxide film or silicon oxynitride film 22 having a thickness of 0.8 to 1.2 nm is formed on the element region 21A.

[0026] Furthermore, the composition of the silicon substrate 21 is Si so as to cover the silicon oxynitride film 22.

A polycrystalline SiGe mixed crystal layer 23 containing Ge at an atomic concentration of 1 to 30%, represented by Ge, is formed with a film thickness of 50 to 150 nm. In the case of forming a p-channel transistor, the SiGe mixed crystal layer 23 is doped p + type at this stage. When forming an n-type MOS transistor, the SiGe mixed crystal layer 23 is doped n + type.

[0027] On the polycrystalline SiGe mixed crystal layer 23, the composition is represented by Si Ge through a silicon oxide film 24 having a thickness of 10 to 20 nm, and Ge has an atomic concentration of 1 to 30%. However, the polycrystalline SiGe mixed crystal layer 25 containing (Ge) more than the Ge concentration in the SiGe mixed crystal layer 23 is formed with a film thickness of 70 to 120 nm.

Further, a resist pattern R1 force is formed on the polycrystalline SiGe mixed crystal layer 25 via an antireflection film (BARC) 26 with a width W1 larger than Onm and smaller than 40 nm with respect to a desired gate length Lg. ing.

Next, in the step of FIG. 3B, using the resist pattern R1 as a mask, the underlying layers 23 to 26 are patterned, and a SiGe mixed crystal layer pattern 23A corresponding to the SiGe mixed crystal layer 23 is formed. A silicon oxide film pattern 24A corresponding to the silicon oxide film 24 is formed corresponding to the SiGe mixed crystal layer 25 with a SiGe mixed crystal layer pattern 25A force having the width W1.

Further, in the step of FIG. 3B, B + or In + is ion-implanted in the silicon substrate 21 to a depth of, for example, 10 to 30 nm using the stacked pattern including the SiGe mixed crystal layer patterns 23A and 25A as a mask. In the element region, a p + type source region 21c and a p + type drain region 21d are formed in the silicon substrate 21 on the first and second sides of the SiGe pattern 23A, respectively.

Incidentally, the SiGe mixed crystal exhibits the etching rate shown in FIG. 4 with respect to dry etching using HBr as an etching gas.

[0032] Referring to FIG. 4, when x = 0 and the SiGe mixed crystal does not contain Ge, the etching rate is about 120 nmZ, whereas the etching rate increases when the Ge concentration in the film increases even under the same etching conditions. The rate also increases, for example when the Ge concentration is 50% (x = 0.5), the etching rate It can be seen that increases almost twice. Depending on the plasma source used for etching and other conditions, there is a slight difference in force.

Therefore, in the present invention, in the process of FIG. 3C, the structure of FIG. 3B is introduced into a normal dry etching apparatus, and is dry-etched under isotropic etching conditions. The SiGe pattern with a width of W2 (W2 and W1) corresponding to the desired gate length (Lg) is slimmed as shown by the arrow in the figure by selective etching for the low SiGe pattern 23A. A mixed crystal layer pattern 25B is formed. In this embodiment, the p-channel MOS transistor 30 has a gate length Lg of 30 nm or less. In this example, a force using a mixed gas mainly composed of HBr is used, using other gases containing C1 and F, such as CI and CF.

twenty four

However, etching depending on the Ge concentration of the SiGe mixed crystal layer is possible.

In the state of FIG. 3C, after the slimming process, the resist pattern R1 and the antireflection film pattern 26A are removed. In the isotropic etching of FIG. 3C, since the Si Ge mixed crystal layer pattern 25B is formed by lateral etching from both sides, it is surely formed at the center of the SiGe mixed crystal layer pattern 23A below it.

Next, in the step of FIG. 3D, dry etching acting mainly in a direction perpendicular to the substrate 21 with respect to the structure of FIG. 3C masks the SiGe mixed crystal layer pattern 23A and the insulating film pattern 24A. In addition, a gas in which 〇 is added to HBr is used as an etching gas.

2

Are applied under etching conditions that act selectively, and in the silicon substrate 21, on the first and second sides of the Si Ge mixed crystal layer pattern 23A, the trenches 21TA and 21TB force, respectively, the source region 21c and the drain region, respectively. It is formed with a depth not exceeding 21d. The groove portions 21TA and 21TB are respectively defined by side wall surfaces 21ta and 21tb facing each other.

In the step of FIG. 3D, after the formation of the groove portions 21TA and 21TB, the SiGe mixed crystal layer pattern 23A force used as a mask when forming the groove portions 21TA and 21TB, together with the insulating film pattern 24A thereon, Further, the SiGe mixed crystal layer pattern 25B is patterned using the upper SiGe mixed crystal layer pattern 25B as a mask. The gate electrode is formed so as to be covered with the insulating film pattern 24B having a width of W2. In this case, the SiON film 22A is not gate-insulated. Constructs an edge membrane.

Next, in the process of FIG. 3E, the structure of FIG. 3D is introduced into a reduced pressure CVD apparatus, and the partial pressure of an inert gas atmosphere such as hydrogen, nitrogen, He or Ar is changed at a substrate temperature of 400 to 550 ° C. Set to 5 to 1330 Pa, and silane (SiH) gas as Si gas phase raw material, l to 10 Pa partial pressure

Four

Then, using germane (GeH) gas as the gas phase raw material of Ge, with a partial pressure of 0.:! To lOPa,

Four

Run the (BH) gas as a dopant gas, at ^{^{1 X 10- 5 ~1 X 10- 3}} , or even hydrogen chloride (

2 6

HC1) Gas etching gas is supplied at 1 to:! OPa partial pressure for 1 to 40 minutes. Thus, p-type SiGe mixed crystal layer regions 25A and 25B force S are grown epitaxially in the trenches 21TA and 21TB, respectively.

In the step of FIG. 3E, the p-type SiGe mixed crystal layers 25A and 25B are grown beyond the interface between the silicon substrate and the gate insulating film 22A.

[0039] As described above with reference to FIG. 1, the SiGe epitaxial layer 25A thus formed is formed as described above.

25B acts so as to extend the channel region directly below the gate electrode 23B in the direction perpendicular to the substrate surface. As a result, the channel region is equivalent to the case where uniaxial compressive stress is applied in the gate length direction. Distortion is induced.

In the step of FIG. 3E, since the gate electrode 23B is covered with the insulating film pattern 24B, no SiGe mixed crystal layer grows on the gate electrode 23B.

Next, in the process of FIG. 3F, a p-type impurity element, for example, B or In is ion-implanted into the structure of FIG. 3E, and the sidewalls 21 ta and 21tb of the silicon substrate 21 are defined. In the formed region, a p-type source extension region 21a and a drain extension region 21b are formed on both sides of the gate electrode 23B.

Further, in the step of FIG. 3G, a pair of side wall insulating films 23W are formed on the gate electrode 23B.

In addition, a silicon oxide film or silicon nitride film is formed by CVD deposition and etchback, and a p-type Si cap layer is formed on each of the SiGe mixed crystal layers 25A and 25B.

26A and 26B are formed epitaxially, and a polysilicon cap film 26C is formed on the SiGe gate electrode 23B.

[0043] These Si cap layers 26A to 26C are used as an underlayer for silicide formation.

On the Si cap layers 26A to 26C by the salicide method in the 3H process, NiSi or Silicide layers made of CoSi or the like 27A to 27C are formed respectively. Especially the Salisa

2

By forming a Si cap layer that does not contain Ge as a base for the id process, the salicide process can be stably performed and a desired low-resistance silicide layer can be formed.

[0044] As described above, in the p-channel MOS transistor 20 formed in this way, the SiGe mixed crystal layers 25A and 25B serve as stress sources, and the channel transistors directly under the gate electrode 23B are used. Uniaxial compressive stress acting in the gate length direction is applied to the region, hole mobility is improved, and transistor operation speed is improved.

At this time, in this embodiment, since the distance between the side wall surfaces 21a, 21b and the gate electrode 23B is controlled by the lateral etching of FIG. 3C, the SiGe mixed crystal layers 25A, 25B are replaced with the groove portions 21TA. Compared to the conventional technique in which 21 TB is formed using the side wall insulating film 23W as a mask, the distance from the side wall surface 21ta or 21tb to the corresponding side wall surface of the gate electrode 23B is close to the gate electrode 23B, for example. As shown in FIG. 3F, it is possible to form the wings (see FIG. 3F) at an arbitrary distance that is 20 nm or less larger than Onm, thereby increasing the magnitude of the uniaxial compressive stress.

Further, the gate electrode 23B is formed on the side wall surface by the lateral etching process of FIG. 3C.

Since it is reliably formed in the center of the silicon substrate region between 21ta and 21tb, variations in device characteristics are also suppressed.

3A to 3H, the SiGe mixed crystal layers 25A and 25B are replaced with a SiC mixed crystal layer containing C (carbon) at an atomic concentration of 0.1 to 10%, and the source By introducing an n-type impurity element into the region 21c and the drain region 21d instead of the p-type impurity element, and then introducing the n-type impurity element into the source extension region 21a and the drain extension region 21b, an n-channel MS It is also possible to constitute a transistor. In this case, since the SiC mixed crystal has a lattice constant smaller than that of the silicon substrate 21, the stress source regions 25A and 25B contract downward, and accordingly, the channel region immediately below the gate electrode 23B does not enter the channel region. A uniaxial tensile stress acting in the gate length direction is generated.

[0048] As described above, when an n-channel MOS transistor is formed using the configuration of FIG. 3H, the gate electrode 23B and the hard mask film 25 thereabove are formed with S as described above. It is possible to use an iGe mixed crystal layer. [Second Embodiment]

Next, a manufacturing process of the semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. However, in the figure, the parts described above are denoted by corresponding reference numerals, and the description thereof is omitted.

Referring to FIG. 5A, in this embodiment, instead of the SiGe mixed crystal layer 23, a SiGe mixed crystal layer 43 configured by stacking SiGe mixed crystal layers 23a to 23d having different Ge compositions is used. In the SiGe mixed crystal layer 43, the Ge composition increases stepwise in the atomic concentration range of:! -30% from the SiGe mixed crystal layer 23a to 23d. The SiGe mixed crystal layer 25 has a Ge concentration higher than the maximum Ge concentration in the SiGe mixed crystal layer 43.

[0050] Also in the present embodiment, the laminated structure of the layers 23 to 26 is patterned using the resist pattern R1 having a width W1 in the step of FIG. 5B, and accordingly, from the SiGe mixed crystal layer 43. A SiGe mixed crystal layer pattern 43A is formed. Further, by ion implantation of a p-type impurity element, a p + -type source region 21c and a drain region 2 Id are formed in the silicon substrate 21 corresponding to the element region 21A.

Next, in the process of FIG. 5C, similarly to the process of FIG. 3C, by performing dry etching under isotropic etching conditions, slimming is performed on the SiGe mixed crystal layer pattern 25A. Form a W2 width pattern 25B corresponding to the gate length design value of the p-channel MOS transistor.

In the process of FIG. 5C, during the isotropic dry etching process, the SiGe mixed crystal layers 23a to 23d are also subjected to slimming by an amount corresponding to the Ge concentration in the film, respectively. A SiGe mixed crystal layer pattern 43B having a stepped shape is formed from the SiGe mixed crystal layer pattern 43A.

Therefore, in the step of FIG. 5D, by applying anisotropic etching acting mainly in the direction perpendicular to the substrate surface to the silicon substrate 21 using the SiGe mixed crystal layer pattern 43B as a mask, the element In the region 21A, grooves 41TA and 41TB corresponding to the grooves 21TA and 21TB are formed on both sides of the SiGe mixed crystal layer pattern 43B in the silicon substrate 21. Here, the groove portions 41TA and 41TB correspond to the side wall surfaces 21ta and 21tb, and are respectively defined by a pair of opposing side wall surfaces 41ta and 41tb. lta and 41tb have a step shape corresponding to the step shape of the SiGe mixed crystal layer pattern 43B, and as a whole, they are inclined in opposite directions. That is, the distance between the side wall surfaces 41ta and 41tb increases stepwise from the interface between the silicon substrate 21 and the gate insulating film 22 downward.

Also in the present embodiment, the groove portions 41TA and 41TB are formed so as not to exceed the source region 21c and the drain region 2 Id.

In the step of FIG. 5D, the Si Ge mixed crystal constituting the SiGe mixed crystal layer pattern 43B is formed along with the formation of the groove portions 41TA and 41TB by dry etching acting in the direction perpendicular to the substrate surface. The layers 23a to 23b are also sequentially etched using the pattern immediately above as a mask, and a stacked pattern 43C having a width W2 corresponding to a desired gate length design value is formed. Here, the width W2 of the stacked layer pattern 43C is determined by the insulating film pattern 24C obtained by patterning the insulating film pattern 24B in the step of FIG. 5C using the SiGe mixed crystal layer pattern 25B as a mask.

[0056] The stacked pattern 43C constitutes the gate electrode of the p-channel MOS transistor 40.

Next, in the step of FIG. 5E, the insulating film pattern 24C is used as a mask, and the trenches 41TA and 41TB are SiGe mixed crystal layers 25A and 25B. In the step of FIG. 5F, the source extension region 21a and the drain extension region 21b are provided in the region between the SiGe mixed crystal layers 25A and 25B in the silicon substrate 21 in the step of FIG. 5F. It is formed by ion implantation of a p-type impurity element using as a mask.

Further, in the step of FIG. 5G, a sidewall insulating film 23W is formed on the side wall surface of the gate electrode 43C in the same manner as in the previous step of FIG. 3G. Further, although not shown, FIG. 3G and FIG. The p-channel MOS transistor 40 is completed through the same process as in FIG.

[0059] In the present embodiment, the sidewall surfaces of the SiGe mixed crystal layers 25A and 25B can be inclined surfaces opposite to each other, and the surface portion of the silicon substrate 21 where the channel is formed has a stress source. SiGe mixed crystal layers 25A and 25B are placed close to each other to maximize the stress applied to the channel, and at the same time, the SiGe mixed crystal layers 25A and 25B are spaced apart from each other in the silicon substrate 21. Thus, these can be surely included in the source region 21c and the drain region 21d. As a result, it is possible to suppress the occurrence of leakage current due to the p-type SiGe layer having a small band gap being in direct contact with the n-type silicon substrate 21 having a large band gap.

[0060] In the configurations shown in FIGS. 5A to 5G, the SiGe mixed crystal layers 25A and 25B are set to C (carbon) of 0.

1 to: Replaced by a SiC mixed crystal layer containing an atomic concentration of 10%, and introduced an n-type impurity element in place of the p-type impurity element in the source region 21c and drain region 21d, and then the source extension region 21 It is also possible to configure an n-channel MOS transistor by introducing an n-type impurity element into a and the drain extension region 21 b. In this case, since the SiC mixed crystal has a lattice constant smaller than that of the silicon substrate 21, the stress source regions 25A and 25B contract downward, and accordingly, the channel region immediately below the gate electrode 23B does not enter the channel region. A uniaxial tensile stress acting in the gate length direction is generated.

As described above, when an n-channel MOS transistor is formed using the configuration shown in FIG. 5G, the gate electrode 43B and the hard mask film 25 thereon are provided with S as described above. It is possible to use an iGe mixed crystal layer.

[Third embodiment]

Next, a manufacturing process of the p-channel MOS transistor 60 according to the third embodiment of the present invention will be described with reference to FIGS. However, in the figure, the same reference numerals are assigned to the portions corresponding to the portions described above, and the description thereof is omitted.

[0062] Referring to FIG. 6A, in the present embodiment, instead of the SiGe mixed crystal layer 43, a SiGe mixed crystal layer 63 in which the Ge composition is continuously increased from the lower end to the upper end is used. In the layer 63, the Ge composition is in the range of! ~ 30% in atomic concentration. The SiGe mixed crystal layer 25 has a Ge concentration higher than the maximum Ge concentration in the SiGe mixed crystal layer 63.

[0063] Also in the present embodiment, the laminated structure of the layers 23 to 26 is patterned using the resist pattern R1 having a width W1 in the step of FIG. 6B, and accordingly, from the SiGe mixed crystal layer 63. A SiGe mixed crystal layer pattern 63A is formed. Further, by ion implantation of a p-type impurity element, a p + -type source region 21c and a drain region 2 Id are formed in the silicon substrate 21 corresponding to the element region 21A.

[0064] Next, in the process of FIG. 6C, as in the process of FIG. By performing dry etching, slimming is performed on the SiGe mixed crystal layer pattern 25A, and a pattern 25B having a width of W2 corresponding to the gate length design value of the p-channel MOS transistor is formed.

In the process of FIG. 6C, during this isotropic dry etching process, the SiGe mixed crystal pattern 63A is also received in an amount corresponding to the Ge concentration in the film, and as a result, the SiGe mixed crystal SiGe mixed crystal layer pattern 63B defined by continuous slope is formed from layer pattern 63A

Therefore, in the step of FIG. 6D, by applying anisotropic etching mainly acting in the direction perpendicular to the substrate surface to the silicon substrate 21 using the SiGe mixed crystal layer pattern 63B as a mask, In the element region 21A, grooves 61TA and 61TB corresponding to the grooves 41TA and 41TB are formed in the silicon substrate 21 on both sides of the SiGe mixed crystal layer pattern 43B. Here, the groove portions 61TA and 61TB are defined by a pair of opposite side wall surfaces 61ta and 61tb corresponding to the side wall surfaces 41ta and 41tb, respectively. However, the side wall surfaces 61ta and 61tb are formed by the SiGe mixture. The crystal layer pattern 63B has an inclined shape corresponding to the inclined side wall surface, and is inclined in opposite directions as a whole. That is, the distance between the side wall surfaces 61ta and 61tb continuously increases from the interface between the silicon substrate 21 and the gate insulating film 22 downward.

Also in the present embodiment, the groove portions 61TA and 61TB are formed so as not to exceed the source region 21c and the drain region 2 Id.

In the step of FIG. 6D, along with the formation of the groove portions 61TA and 61TB by dry etching acting in the direction perpendicular to the substrate surface, the SiGe mixed crystal layer pattern 63B is also sequentially etched to obtain a desired A SiGe mixed crystal layer pattern 63C with a width W2 corresponding to the gate length design value is formed. Here, the width W2 of the SiGe mixed crystal layer pattern 63C is determined by the insulating film pattern 24C obtained by patterning the insulating film pattern 24B in the process of FIG. 6C using the SiGe mixed crystal layer pattern 25B as a mask. Has been.

[0069] The SiGe mixed crystal layer pattern 63C constitutes the gate electrode of the p-channel MOS transistor 60.

Next, in the step of FIG. 6E, using the insulating film pattern 24C as a mask, the groove 61TA , 61TB are filled with SiGe mixed crystal layers 25A and 25B by a regrowth process similarly to the process of FIG. 5E, and in the process of FIG. In the region between the mixed crystal layers 65A and 65B, the source extension region 21a and the drain extension region 21b are formed by ion implantation of a p-type impurity element using the gate electrode 63C as a mask.

Further, in the step of FIG. 6G, a side wall insulating film 23W is formed on the side wall surface of the gate electrode 63C in the same manner as in the previous step of FIG. 5G. Further, although not shown, FIG. 3G and FIG. The p-channel MOS transistor 60 is completed through the same process as in FIG.

[0072] In the present embodiment, the sidewall surfaces of the SiGe mixed crystal layers 25A and 25B can be inclined surfaces that are opposite to each other, and the surface portion of the silicon substrate 21 where the channel is formed has a stress source. The SiGe mixed crystal layers 25A and 25B are made close to each other to maximize the stress applied to the channel, and at the same time, the SiGe mixed crystal layers 25A and 25B are spaced apart from each other in the silicon substrate 21, and these are separated into the source region 21c, The drain region 21d can be surely included. As a result, it is possible to suppress the occurrence of leakage current due to the p-type SiGe layer having a small band gap being in direct contact with the n-type silicon substrate 21 having a large band gap.

[0073] In the configurations of Figs. 6A to 6G, the SiGe mixed crystal layers 25A and 25B are replaced with C (carbon) of 0.

1 to: Replaced by SiC mixed crystal layer containing atomic concentration of 10%, introduced n-type impurity element instead of p-type impurity element into the source region 21c and drain region 21d, and further source extension region 21a and drain An n-channel MOS transistor can be configured by introducing an n-type impurity element into the extension region 21b. In this case, since the SiC mixed crystal has a lattice constant smaller than that of the silicon substrate 21, the stress source regions 25A and 25B contract downward, and accordingly, the channel region immediately below the gate electrode 23B does not enter the channel region. A uniaxial tensile stress acting in the gate length direction is generated.

[0074] Thus, when an n-channel MOS transistor is formed using the configuration shown in FIG. It is possible to use an iGe mixed crystal layer. It is also possible to replace this with SiC mixed crystals. In this case, the C concentration in the gate electrode 63B is continuously increased from the lower end to the upper end in the atomic concentration range of 0.1 to 10%. [0075] In the above description, the gate electrodes 23B, 43C, and 63C have been described as SiGe mixed crystal patterns or SiC mixed crystal patterns. However, the gate electrodes are used in the dry etching process of the silicon substrate of FIG. If it can be used as a mask, it may contain other elements. Similarly, the SiGe mixed crystal layer 25 may contain other elements as long as it can serve as a mask in the dry etching of the underlying layer 23.

While the present invention has been described with reference to the preferred embodiments, various modifications and changes can be made to the present invention within the spirit and scope of the appended claims.

Industrial applicability

According to the present invention, the silicon substrate is anisotropically etched in the direction perpendicular to the substrate surface using the first polycrystalline pattern of the first width as a mask, and the second polycrystal of the second width is used. Using the crystal pattern as a mask, the first polycrystalline pattern is anisotropically etched in a direction perpendicular to the substrate surface, so that both sides of the region where the first polycrystalline pattern is formed in the silicon substrate. First and second trenches are formed, and a gate electrode is formed in the center of the region in a self-aligned manner with a desired gate length by the first polycrystalline pattern. In this case, the second polycrystalline pattern is obtained by selectively laterally etching the second polycrystalline film pattern on the first polycrystalline film pattern with respect to the first polycrystalline pattern, It should be noted that it is formed in a self-aligned manner in the central portion of the region. Therefore, the first polycrystalline pattern is anisotropically etched in the direction perpendicular to the substrate using the second polycrystalline pattern formed in this manner as a mask, so that the desired gate electrode is formed into the first polycrystalline pattern. The pattern makes it possible to reliably form the central portion of the region. Thus, the first or second epitaxial semiconductor layer acting as a source of compressive or tensile stress to the first or second groove, and thus to the channel region of the semiconductor device, is 20 nm from the side wall surface of the gate electrode. It can be formed at the following close distance, and the force S can be increased to increase the stress applied to the channel region of the stress application semiconductor device. That is, according to the present invention, the operation speed of the semiconductor device can be improved with a simple configuration and process.

In the present invention, the Ge concentration in the first polycrystalline pattern serving as the gate electrode is stepped in the film thickness direction by utilizing the fact that the etching rate of the SiGe mixed crystal layer varies with the Ge concentration. By changing the shape or continuously, the opposing side wall surfaces of the first and second groove portions can be formed in a shape inclined in opposite directions. At this time, the shape of the side wall surface becomes a stepped surface or a continuous surface depending on whether the Ge concentration change in the first polycrystalline pattern is stepped or continuous. As a result, in the vicinity of the interface between the gate insulating film and the silicon substrate where the effect of applying stress to the channel region is large, the first and second semiconductor layer regions serving as stress sources are formed closest to each other. Is easily obtained.

Claims

The scope of the claims

[1] a silicon substrate;

A gate electrode formed on the silicon substrate via a gate insulating film; and first and second groove portions formed on the first and second sides of the gate electrode in the silicon substrate so as to be spaced apart from each other. When,

First and second epitaxial layers made of a mixed crystal of Si and another group IV element and filling the first and second grooves, respectively,

With

The stress application semiconductor device, wherein the gate electrode is a polycrystalline body made of a mixed crystal of Si and another element.

2. The stress-applying semiconductor device according to claim 1, wherein the other element constituting the gate electrode and the other group IV element constituting the first and second epitaxial layers are the same element. .

[3] The stress application semiconductor according to [1], wherein the other elements constituting the gate electrode and the other group IV elements constituting the first and second epitaxial layers are different elements. Body equipment.

[4] The first groove portion and the second groove portion are the side wall surface on the first side and the side on the second side of the gate electrode, respectively, at the interface between the silicon substrate and the gate insulating film. 2. The stress applying semiconductor device according to claim 1, wherein the stress applying semiconductor device is formed apart from the wall surface by a distance exceeding Onm and not more than 20 nm.

5. The stress applying semiconductor device according to claim 1, wherein the mixed crystal constituting the gate electrode increases the concentration of the other element stepwise from the lower end in contact with the gate insulating film toward the upper end.

[6] The first and second groove portions are defined by first and second side wall surfaces facing each other, and the first and second side wall surfaces are formed on the first and second side wall surfaces. 6. The stress applying semiconductor device according to claim 5, wherein the interval is formed so as to increase stepwise with the depth from the interface between the silicon substrate and the gate insulating film.

[7] The mixed crystal constituting the gate electrode extends from the lower end in contact with the gate insulating film to the upper end. 2. The stress applying semiconductor device according to claim 1, wherein the concentration of the other element is continuously increased.

[8] The first and second groove portions are defined by first and second side wall surfaces facing each other, and the first and second side wall surfaces are formed on the first and second side wall surfaces. 8. The stress applying semiconductor device according to claim 7, wherein the interval is formed so as to continuously increase with the depth from the interface between the silicon substrate and the gate insulating film.

[9] The stress applying semiconductor device is a p-channel MOS transistor, and the first and second transistors

2. The stress applying semiconductor device according to claim 1, wherein the second epitaxial layer is made of a p-type doped SiGe mixed crystal.

[10] The stress applying semiconductor device is an n-channel MOS transistor, and the first and the second

The epitaxial layer according to claim 2, wherein the epitaxial layer is made of an n-type doped SiC mixed crystal.

The stress applying semiconductor device according to 1.

[11] The first and second groove portions are respectively included in source and drain regions formed in the silicon substrate, and the source and drain regions are formed in the first and second regions. 2. The stress applying semiconductor device according to claim 1, wherein the stress applying semiconductor device has the same conductivity type as that of the epitaxial layer.

[12] forming a first polycrystalline film made of a mixed crystal of Si and another element on the silicon substrate via the first insulating film;

Forming a second polycrystalline film having a concentration of the other element higher than that of the first polycrystalline film on the first polycrystalline film via a second insulating film;

The first and second polycrystalline films are patterned together with the second insulating film, and a first polycrystalline pattern having a first width and the first width are formed on the silicon substrate. Forming a laminated structure in which a second polycrystalline pattern is laminated via an insulating film pattern having the first width;

Isotropic etching is performed on the stacked structure, and the width of the second polycrystalline pattern is selectively reduced with respect to the first polycrystalline pattern from the first width to the second width. A process of reducing,

Using the first polycrystalline pattern as a mask, anisotropic etching is performed on the silicon substrate. Forming a first groove and a second groove on the first and second sides of the stacked structure in the silicon substrate, respectively;

Anisotropically etching the insulating film pattern and the first polycrystalline pattern using the second polycrystalline pattern as a mask;

Filling the first and second grooves with first and second semiconductor layers made of a mixed crystal of Si and another group IV element, and

A method for manufacturing a stress-applying semiconductor device, comprising:

[13] The stress-applied semiconductor device according to [12], wherein the concentration of the other element in the first polycrystalline film is increased stepwise toward the upper end. Manufacturing method.

[14] The first and second grooves are defined by first and second side wall surfaces facing each other, and the first and second side wall surfaces are the first and second side wall surfaces. 14. The method of manufacturing a stress-applying semiconductor device according to claim 13, wherein the distance is increased stepwise with the depth from the interface between the silicon substrate and the gate insulating film.

15. The stress applying semiconductor device according to claim 12, wherein the concentration of the other element in the first polycrystalline film continuously increases from the lower end to the upper end. Manufacturing method.

[16] The first and second grooves are defined by first and second side wall surfaces facing each other, and the first and second side wall surfaces are defined by the first and second side wall surfaces. 16. The method of manufacturing a stress-applying semiconductor device according to claim 15, wherein the gap is continuously increased with the depth from the interface between the silicon substrate and the gate insulating film.

17. The method for manufacturing a p-channel MOS transistor according to claim 10, wherein the step of forming the first and second semiconductor layers is performed by a regrowth step using the insulating film pattern as a mask.

[18] Prior to the step of forming the first and second groove portions, ion implantation of an impurity element is performed in the silicon substrate using the stacked structure as a mask, and the first and second trench structures are respectively formed. Including a step of forming source and drain diffusion regions on the second side, wherein the first and second groove portions are formed so as not to exceed the source and drain diffusion regions, respectively. 13. The method for manufacturing a stress applying semiconductor device according to claim 12, wherein:

Further, after the step of forming the first and second semiconductor layers, an impurity element is introduced into the silicon substrate by ion implantation, and a source extension region and a gate extension electrode are respectively formed on the first and second sides of the gate electrode. 13. The method for manufacturing a stress applying semiconductor device according to claim 12, further comprising a step of forming a drain extension region.