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WO2005029853A1 - データ変換システム - Google Patents

データ変換システム Download PDF

Info

Publication number
WO2005029853A1
WO2005029853A1 PCT/JP2003/011949 JP0311949W WO2005029853A1 WO 2005029853 A1 WO2005029853 A1 WO 2005029853A1 JP 0311949 W JP0311949 W JP 0311949W WO 2005029853 A1 WO2005029853 A1 WO 2005029853A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
data
conversion system
reference signal
cycle
Prior art date
Application number
PCT/JP2003/011949
Other languages
English (en)
French (fr)
Inventor
Atsushi Tabuchi
Original Assignee
Canopus Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canopus Co., Ltd. filed Critical Canopus Co., Ltd.
Priority to CNB038270781A priority Critical patent/CN100466710C/zh
Priority to AU2003264500A priority patent/AU2003264500A1/en
Priority to PCT/JP2003/011949 priority patent/WO2005029853A1/ja
Priority to EP03818716A priority patent/EP1667447B1/en
Priority to CN2009100016329A priority patent/CN101472171B/zh
Priority to US10/595,168 priority patent/US8285896B2/en
Priority to JP2005509049A priority patent/JP4228081B2/ja
Publication of WO2005029853A1 publication Critical patent/WO2005029853A1/ja

Links

Classifications

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    • G11B27/031—Electronic editing of digitised analogue information signals, e.g. audio or video signals
    • G11B27/034—Electronic editing of digitised analogue information signals, e.g. audio or video signals on discs
    • G—PHYSICS
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    • G01S1/00—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith
    • G01S1/02—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith using radio waves
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    • G01S1/026—Means for monitoring or calibrating of associated receivers
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    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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Definitions

  • the present invention relates to a data conversion system for converting data output from an information processing device into data of a different format in real time, and in particular, one of a first node and a second node on an IEEE1394 bus.
  • the cycle master As the cycle master, the first data is transferred from the first node to the second node in synchronization with the cycle start packet output by the cycle master, and the second node is converted from the first data by the second node.
  • the present invention relates to a data conversion system that outputs data in synchronization with a reference signal input from the outside.
  • nonlinear editing in which video editing is performed on a personal computer (PC) has become widespread due to the remarkable improvements in the data recording capacity and processing speed of personal computers (PCs).
  • PCs personal computers
  • special hardware such as a video capture port and a video editing port to the PC's expansion slot.
  • dedicated hardware is required to handle analog video and high-end professional signals, but it is widely used in consumer equipment and low-end business. If only DV (Digital Video) format data is handled, general-purpose, inexpensive 1394OHCI-compliant IEEE 1394 interface standard hardware is becoming practical.
  • the 1394OHCI-compliant IEEE1394 interface is often installed not only on desktop PCs but also on notebook PCs as standard, and it is possible to perform all operations from video input / output in DV format to editing on a single laptop PC. It is possible.
  • the system described above can be used to complete the process.However, there are many cases where analog video images and professional SDI format materials need to be handled. In such a case, it is necessary to perform mutual conversion of formats.
  • To convert data between DV format video material and analog video image or SDI format video material the input analog video signal or SDI video signal is converted to DV format in real time.
  • an external unit type DV converter that outputs a DV signal while converting it as a DV signal or vice versa while converting a DV format video signal into an analog video signal or an SDI video signal is also used.
  • DV converters There are various types of DV converters, from consumer use to business use.
  • a function called external synchronization (genlock) may be required.
  • a DV converter without this external synchronization function converts a DV signal output from a PC via a 13940HCI compliant IEEE 1394 interface to an analog video signal or an SDI video signal
  • the frame of the DV signal output from the PC is used.
  • a reference signal that serves as the output timing reference is input via the reference input terminal.
  • the conversion result signal is buffered and synchronized with the reference signal. Output.
  • Asynchronous transfer asynchronous transfer
  • Isochronous transfer asynchronous transfer
  • PC and DV converter and power ⁇ When present as a node on the IEEE1394 bus and outputting a DV video signal to the DV converter via a 13940 HCI compliant IEEE1394 interface on the PC, either the PC or the DV converter transfers It becomes a node called a cycle master that manages the cycle, and outputs a cycle start bucket on the IEEE1394 bus at a fixed cycle (125 ⁇ sec).
  • the IEEE1394 interface conforming to 1394OHCI of the PC transmits a DV format video signal in the form of a bucket for isochronous transfer defined by IEEE1394 every time a cycle start packet output by the cycle master is detected.
  • the frame frequency of the DV video signal output from the 1394OHCI-compliant IEEE1394 interface of the PC is synchronized with the frequency of the cycle start packet output by the cycle master.
  • the cycle start bucket output interval of 125 sec generated by the cycle master is generated at a fixed ratio from the clock source 24.576 MHz of the node that has become the cycle master, but the individual clock sources included in each hardware are generated. Fluctuates, frequency fluctuations occur.
  • the frame frequency of the DV video signal output from the PC's 13940HCI compliant IEEE1394 interface differs depending on the device used, it must not be equal to the frame frequency of the reference signal input from the outside to the DV converter on average. Even if buffering is performed on the DV converter side, if the transfer speed from the PC side is high, the output analog video signal or SDI video signal may have dropped frames, and the transfer speed from the PC side is low. In such a case, there is a problem that frame repetition occurs in the output analog video signal or SDI video signal.
  • the present invention synchronizes the transfer of data and the output of the converted data when converting the data output from the information processing device into data of a different format in real time.
  • a data conversion system that prevents image defects such as repetition from occurring.
  • one of the first node and the second node on the IEEE1394 bus becomes a cycle master, and is synchronized with a cycle start packet output by the cycle master.
  • Data conversion that transfers the first data from one node to the second node and outputs the second data converted from the first data at the second node in synchronization with an externally input reference signal
  • An external synchronization signal receiving unit provided at at least one of the first node and the second node, for receiving a reference signal input from the outside, and externally synchronizing a frequency of a cycle start bucket output by the cycle master.
  • a synchronization adjustment unit that synchronizes with a reference signal received by the signal reception unit.
  • the transfer rate of the data output from the first node and the output rate of the second data output from the second node must be matched by synchronizing the frequency of the cycle start bucket with the reference signal. It is possible to prevent data from being lost or repeated in the output second data. In particular, when converting a video signal such as a DV format into a video signal of a different format, it is possible to prevent image defects such as dropped frames and repeated frames.
  • a data conversion system is the data conversion system according to claim 1, wherein the first node is a 13940HCI-compliant IEEE1394 interface that outputs a DV format video signal as first data.
  • the second node is data conversion hardware that outputs an analog video signal or an SDI video signal as the second data.
  • a data conversion system according to claim 3 of the present invention is the data conversion system according to claim 1 or 2, wherein the second node includes an external synchronization signal reception unit and a synchronization adjustment unit, and includes a cycle during data transfer. It is characterized by becoming a master.
  • the transfer rate of data output from the first node can be synchronized with the reference signal received at the second node.
  • a data conversion system is the data conversion system according to claim 1 or 2, wherein the first node includes a synchronization adjustment unit, and the second node includes an external synchronization signal reception unit and a synchronization signal.
  • An adjustment unit is provided, and the synchronization adjustment unit of the node that has become the cycle master synchronizes the frequency of the cycle start bucket with the reference signal received by the external synchronization signal receiving unit and outputs it.
  • the data conversion system according to claim 5 of the present invention is the data conversion system according to claim 4, wherein when the first node becomes a cycle master, the data is received by the external synchronization signal receiving unit of the second node. A synchronization adjustment signal generated based on the reference signal thus transmitted is transmitted from the second node to the first node by asynchronous transfer of the IEEE1394 interface.
  • the synchronization adjustment signal generated based on the reference signal received by the external synchronization signal receiving unit is transmitted using the IEEE1394 bus, even if the first node becomes the cycle master, In particular, it is possible to transmit a synchronization adjustment signal without increasing the number of wirings.
  • the data conversion system according to claim 6 of the present invention is the data conversion system according to claim 4, wherein when the first node becomes a cycle master, the data is received by the external synchronization signal receiving unit of the second node.
  • Dedicated synchronization signal line for transmitting a synchronization adjustment signal generated based on the reference signal from the second node to the first node In this case, even if a reference signal for external synchronization is input to the second node and the first node becomes the cycle master, the data transfer rate from the first node is used as the reference signal. Synchronization can be performed reliably.
  • a data conversion system is the data conversion system according to claim 1 or 2, wherein the first node includes an external synchronization signal reception unit and a synchronization adjustment unit, and includes a cycle in data transfer. It is characterized by becoming a master.
  • the second node since the frame frequency of the data output from the first node is already completely externally synchronized, the second node simply needs to perform the conversion process, and the second node does not have the external synchronization function. Even with a converter, external synchronization without frame dropout or frame repetition can be realized for the entire system.
  • FIG. 1 is a simplified block diagram of the first embodiment.
  • FIG. 2 is a simplified block diagram of the second embodiment.
  • FIG. 3 is a simplified block diagram of the third embodiment.
  • a hardware equipped with a 13940HCI-compliant IEEE1394 interface, and a DV video signal output from the PC converted to an analog video signal or an SDI video signal for output
  • a DV converter conversion hardware
  • the isochronous eggplant transfer mode is managed by a node called a cycle master on the IEEE1394 bus, and based on the cycle start bucket output by the cycle master every 125jsec, the PC uses a 13940HCI-compliant IEEE1394 interface. Output a DV format video signal.
  • the interval of the cycle start bucket is divided at a fixed ratio from the cycle master clock source of 24 576 MHz, and the interval from the reference signal input to the external synchronous circuit occurs. Even if buffering is performed when an analog video signal or SDI video signal is output, defects such as dropped frames or repeated frames may occur. For this reason, in the present invention, the frequency of the cycle master's peak source is subjected to feedback control using a reference signal, so that the interval between cycle start buckets output by the cycle master is made longer or shorter than 125 sec. As a result, the IEEE 1394 transfer rate is dynamically changed, and as a result, the average of the frame frequency of the DV format video signal output from the IEEE 1394 interface conforming to 13940HCI is used for external synchronization. It is made to match the frequency of the reference signal.
  • a PC 10 which is IEEE 1394 hardware conforming to 13940HCI and a DV converter 20 for converting a video signal of a DV format into an analog video signal or an SDI video signal are connected by an IEEE 1394 cable 30.
  • the PC 10 includes a DV data processing unit 11 including a recording medium such as a hard disk for storing moving image data in a DV format, an IEEE1394 circuit 12 for inputting and outputting data in a packet format defined by IEEE1394 12, a crystal oscillator, etc. And a clock source 13 composed of Note that the PC 10, a CPU, a ROM, a RAM, and other interfaces are built in, and these functional units are omitted in the drawing. In addition, the PC 10 has an environment in which at least video editing software for editing data in the DV format can be executed, and can be output through the DV data processing unit 11 and the IEEE1394 circuit 12. I have.
  • the DV converter 20 includes an IEEE1394 circuit 21 for receiving a DV format video signal transferred via the IEEE1394 cable 30, and an analog video signal or an SDI signal for transferring the transferred DV format video signal. Convert to video signal A data conversion circuit 23, a frame buffer 24 that temporarily buffers the converted video signal, an external synchronization circuit 25 that receives an external reference signal, and a clock oscillation circuit VCXO that receives voltage feedback control by the external synchronization circuit 25 ( Voltage Controlled Crystal Oscillator) 22.
  • the DV converter 20 also has a built-in CPU, ROM, RAM, various interfaces, and the like, and these functional parts are omitted in the drawing.
  • the IEEE1394 node on the DV converter 20 side becomes a cycle master.
  • the IEEE1394 circuit 21 of the DV converter 20, which has become the cycle master, outputs a cycle start bucket to the IEEE1394 bus every 125 seconds.
  • the clock oscillation circuit that determines the interval of the cycle start bucket is provided by the external synchronization circuit 25. Is controlled by
  • the external synchronization circuit 25 controls the oscillation frequency of VCX022 by feedback-controlling the voltage of VCXO22 so that the timing difference between the input reference signal and the output analog video signal or SDI video signal is kept constant. .
  • the output interval of the cycle start bucket generated by dividing the clock of the VCXO22 at a fixed ratio changes, and the transfer rate from the 1394OHCI-compliant IEEE1394 side of the PC 10 determined by the cycle start bucket interval is also determined. Can be synchronized with the reference signal.
  • the DV converter 20 receives the transfer of the DV video signal from the 13940HCI-compliant IEEE1394 interface of the PC10 and converts the analog video signal or SDI video signal after data conversion into dropped frames or repeated frames. It is possible to output the signal completely in synchronization with the reference signal without any defect such as the above.
  • the IEEE 1394 hardware of the PC 10 can be configured as a standard product.
  • a PC 10 which is IEEE1394 hardware conforming to 1394OHCI and a DV converter 20 for converting a video signal of a DV format into an analog video signal or an SDI video signal are connected by an IEEE1394 cable 30.
  • the PC 10 includes a DV data processing unit 11 including a recording medium such as a hard disk for storing moving image data in a DV format, an IEEE 1394 circuit for inputting / outputting data in a bucket format defined by IEEE 1394, and voltage feedback.
  • the VCX014 is equipped with a controllable oscillation frequency. As described above, the CPU 10, ROM, RAM. And other interfaces are built in the PC 10, and these functional units are omitted in the drawing.
  • the PC 10 has an environment in which at least video editing software for editing DV format data can be executed, and the PC 10 can output the data via the DV data processing unit 11 and the IEEE1394 circuit 12. O
  • the DV converter 20 includes an IEEE1394 circuit 21 for receiving a DV format video signal transferred via the IEEE1394 cable 30, and an analog format video signal for the transferred DV format video signal.
  • a data conversion circuit 23 that converts video signals or SDI format video signals, a frame buffer 24 that temporarily buffers the converted video signals, an external synchronization circuit 25 that receives an external reference signal, and an external synchronization circuit 25 It is equipped with a clock oscillation circuit VCXO (Voltage Controlled Crystal Oscillator) 22 that receives voltage feedback control by the VCO.
  • the DV converter 20 also has a built-in CPU, ROM. RAM, various interfaces, and the like, and these functional parts are omitted in the drawing.
  • the input reference signal and the analog video signal or the SDI video signal are output in the same manner as in the first embodiment.
  • the oscillation frequency of VCXO22 is controlled by feedback-controlling the voltage of VCXO22 so as to keep the signal timing difference constant. This allows the VCX022 clock to be divided at a fixed ratio and generated. lo J
  • the output interval of the start bucket varies and is determined by the interval of this cycle start bucket: The transfer rate from the IEEE1394 side of the PC10 that conforms to 13940HCI can also be synchronized with the reference signal.
  • the reference signal received by the external synchronization circuit 25 of the DV converter 20 is transmitted to the PC 10 side via the IEEE 1394 cable 30, and the reference signal and the cycle start packet are transmitted.
  • the feedback control of the VCXO 14 on the PC 10 side is performed so that the timing difference of the PC 10 is kept constant.
  • the signal can be transmitted in an asynchronous (Asynchronous) transfer mode.
  • the PC 10 can interpret the command transmitted by the AV / C protocol. It is necessary to have an algorithm.
  • the output interval of the cycle start bucket generated by dividing the frequency of the VCX014 clock by a fixed ratio changes, and the transfer from the 13940HCI compliant IEEE1394 side of PC10 is determined by the cycle start bucket interval.
  • the rate can also be synchronized with the reference signal.
  • the analog video signal or the SDI video signal after the data conversion can be used to reduce frame loss or repeat frames. It is possible to output completely synchronously with the reference signal without any defect.
  • a dedicated control signal line 31 for transmitting to the PC 10 a synchronization adjustment signal generated based on a reference signal input to the external synchronization circuit 25 of the DV converter 20 can be separately provided.
  • the synchronization adjustment signal generated based on the reference signal is reliably transmitted via the dedicated control signal line 31, and the feedback control of the VCX014 on the PC 10 side can be performed.
  • a reference signal for external synchronization can be input to the PC, and the transfer frequency to the PC or the DV converter can be controlled so as to synchronize with the reference signal.
  • a PC 10 which is IEEE1394 hardware conforming to 1394OHCI and a DV converter 20 which converts a video signal of a DV format into an analog video signal or an SDI video signal are connected by an IEEE1394 cable 30. I have.
  • PC10 (This is a DV data processing unit 11 including a recording medium such as a hard disk that stores moving image data in DV format 11, an IEEE1394 circuit 12 that inputs and outputs data in the form of packets defined by IEEE1394, and voltage feedback. It has a VCX014 that can control the oscillation frequency and an external synchronization circuit 15 that receives an external reference signal.
  • the PC 10 a CPU, a ROM, a RAM, and other interfaces are built in, and these functional units are omitted in the drawing. Also, the PC 10 has an environment in which video editing software for editing at least DV format data can be executed, and can be output via the DV data processing unit 11 and the IEEE 1394 circuit 12. It has become.
  • the DV converter 20 includes an IEEE1394 circuit 21 for receiving a DV format video signal transferred via the IEEE1394 cable 30, and an analog video signal or an SDI signal for transferring the transferred DV format video signal. It has a data conversion circuit 23 for converting to a video signal, a clock source 26 composed of a crystal oscillator and the like.
  • the DV converter 20 also has a built-in CPU, ROM, RAM, various interfaces, and the like, and these functional parts are omitted in the drawing.
  • the VCX014 of the PC 10 is fed back based on the reference signal received by the external synchronization circuit 15 of the PC 10 so that the timing difference between the reference signal and the cycle start packet is kept constant. Control.
  • the output interval of the cycle start bucket generated by dividing the VCX014 clock at a fixed ratio changes, and the transfer rate from the 13940HCI-compliant IEEE1394 side of PC10 determined by the cycle start bucket interval.
  • Each part can be synchronized with the reference signal.
  • the IEEE1394 node of the PC 10 needs to be the cycle master.
  • the analog video signal or the SDI video signal after the data conversion is output completely in synchronization with the reference signal without any defect such as repeated frames.
  • the hardware on the DV converter 20 side can be configured using a general-purpose product as it is.
  • the frame frequency of the data output in synchronization with the external synchronization reference signal and the frame frequency of the data output through the 13940HCI-compliant IEEE1394 interface can be synchronized. It is possible to prevent data defects such as dropped frames or repeated frames due to a shift in frame frequency.
  • the transfer rate by IEEE1394 and the output frame rate are synchronized, so that dropped frames and frames are eliminated.
  • the occurrence of image defects such as repetition can be prevented.
  • the data format to be converted is not limited to the one described in the embodiment, but may be an analog video signal, an SDI video signal, a DV video signal, MPEG1, MPEG2, MPEG4. It can be applied to mutual conversion. Also, the present invention is not limited to moving image data, but can be applied to audio data.

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Abstract

本発明は、情報処理装置から出力されるデータを異なるフォーマットのデータにリアルタイムで変換する際に、データの転送と変換されたデータの出力を同期させることにより、動画像データにおけるフレーム落ちやフレーム繰り返しなどの画像の欠陥が生じることを防止するデータ変換システムを提供する。このデータ変換システムは、IEEE1394バス上の第１ノードと第２ノードとのうちいずれか一方がサイクルマスタとなり、サイクルマスタが出力するサイクルスタートパケットに同期して、第１ノードから第２ノードへの第１データの転送を行うとともに、第２ノードにおいて第１データから変換された第２データを外部から入力されるリファレンス信号に同期して出力するデータ変換システムであって、第１ノードおよび第２ノードの少なくとも一方に設けられ、外部から入力されるリファレンス信号を受信する外部同期信号受信部と、サイクルマスタが出力するサイクルスタートパケットの周波数を外部同期信号受信部で受信したリファレンス信号に同期させる同期調整部とを備える。

Description

明 細 書 データ変換システム
(技術分野）
本発明は、 情報処理装置から出力されるデータを異なるフォーマツ卜のデータ にリアルタイムで変換するためのデータ変換システムに関し、 特に、 IEEE1394 バス上の第 1ノードと第 2ノードとのうちいずれか一方がサイクルマスタとなリ 、 サイクルマスタが出力するサイクルスタートパケットに同期して、 第 1ノード から第 2ノードへの第 1データの転送を行うとともに、 第 2ノードにおいて第 1 データから変換された第 2データを外部から入力されるリファレンス信号に同期 して出力するデータ変換システムに関する。
(背景技術）
パーソナルコンピュータ （PC) のデータ記録容量および処理速度の著しい向上 によりビデオ編集を PC上で行う、 いわゆるノンリニア編集が普及してきている。 ビデオ素材を PCに取り込んだり、 編集した後のビデオ画像を出力する際には、 ビ デォキヤプチャポードゃビデオ編集ポードなどの専用のハードウエアを PCの拡 スロッ卜に追加挿入し、 このハードウエアを介してデータの入出力を行っている 現在でも、 アナログビデオやハイエンド業務用の信号を扱うためには、 専用の ハードウエアが必要となるが、 民生機器やローェンド業務用で広く用いられてい る DV (Digital Video) というフォーマツ卜のデータを扱うだけであれば、 汎用 の安価な 1394OHCI準拠の IEEE1394ィンタ一フェイス規格のハードウエアであ つても実用に耐えるようになってきている。
これは、 PCの CPU能力が向上したことにより、 専用のハードウェアを用いるこ となくビデオ編集などの処理を実用的に実行できるようになったことに加えて、 代表的なビデオ編集ソフトウ；!:ァが DVフォーマツ卜でデータの入出力を行うイン ターフェイスとして、 13940HCI準拠の IEEE1394インタ一フェイスをサポート するようになったことが、要因となっている。
1394OHCI準拠の IEEE1394インタ一フェイスは、 デスクトップ型 PCだけでは なく、 ノートブック型 PCにも標準搭載される場合も多く、 DVフォーマットでの ビデオ入出力から編集までをノート型 PC 1台で行うことも可能となっている。
DVフォーマツ卜のビデオ素材のみを扱う場合には、 前述したようなシステムで 完結することができるものの、 アナログビデオ画像や業務用の SDIフォーマツト の素材を扱う必要があるケースも少なくなく、 そのような場合には、 フォーマツ 卜の相互変換を行う必要がある。 DVフォーマットのビデオ素材と、 アナログビデ ォ画像や SDIフォーマツ卜のビデオ素材との間でデータの相互変換をするために は、 入力されたアナログビデオ信号または SDIビデオ信号をリアルタイムで DVフ ォーマツ卜に変換しながら DV信号として出力したり、 その逆に DVフォーマツト のビデオ信号をアナログビデオ信号や SDIビデオ信号に変換しながら出力する外 付けュニッ卜型の DVコンバータが併用される場合が多い。
民生用から業務用にいたるまでさまざまな DVコンバータが存在しているが、 業 務用途では外部同期 （ゲンロック） と呼ばれる機能が必要とされる場合がある。 この外部同期機能を持たない DVコンパータでは、 PCから 13940HCI準拠の IEEE 1394インターフェイスを介して出力される DV信号からアナログビデオ信号また は SDIビデオ信号に変換する際、 PCから出力される DV信号のフレーム周波数の タイミングで、 変換結果のアナログビデオ信号または SDIビデオ信号を出力する 外部同期機能を有する DVコンバータの場合、 リファレンス入力端子を介して出 力タイミングの基準となるレファレンス信号が入力される。 PCの 1394OHCI準拠 の IEEE 1394ィンターフェイスから出力された DVビデオ信号をアナ口グビデオ信 号や SDIビデオ信号に変換する場合には、 変換結果の信号をバッファリングしな がらリファレンス信号に同期させて出力する。
IEEE1394バス上に接続されたノード間のデータ転送には、 Asynchronous転送 (非同期転送） モードと Isochronous転送 （ァイソクロナス転送） モードがあり、 映像■音声の転送にはアイソク口ナス転送モ一ドが用いられる。 PCの 13940HCI 準拠の IEEE 1394ィンタ一フェイスを介して DVビデオ信号を出力する場合もこの ァイソクロナス転送モードを用いる。
PCと DVコンバータと力《IEEE1394バス上のノードとして存在し、 PCの 13940 HCI準拠の IEEE1394ィンタ一フェイスを介して DVコンバータに DVビデオ信号 を出力する場合、 PCまたは DVコンバータのいずれか一方が転送サイクルを管理 するサイクルマスタと呼ばれるノードとなり、 一定周期 （125 u sec) でサイクル スタートバケツ卜を IEEE1394バス上に出力する。
PCの 1394OHCI準拠の IEEE1394ィンターフェイスは、 サイクルマスタが出力 するサイクルスタートパケットを検出する度に、 IEEE1394で定義されているァ イソクロナス転送用のバケツ卜の形式で DVフォーマツ卜のビデオ信号を送信する このように、 PCの 1394OHCI準拠の IEEE1394ィンターフェイスから出力され る DVビデオ信号のフレーム周波数は、 サイクルマスタの出力するサイクルスター トパケットの周波数と同期することとなる。 サイクルマスタの出力するサイクル スタートバケツ卜の 125 secという間隔は、 サイクルマスタとなったノードのク ロックソース 24.576MHzから一定比で分茼されて生成されるが、 各ハードウエア に備わる個々のクロックソースのばらつきから、 周波数のゆらぎが生じることと なる。 したがって、 PCの 13940HCI準拠の IEEE1394インターフェイスから出力 される DVビデオ信号のフレーム周波数が使用する機器により異なることから、 外 部から DVコンバータに入力されるリファレンス信号のフレーム周波数と平均的に —致しないこととなり、 DVコンバータ側でバッファリングを行っても、 PC側カヽ らの転送速度が速い場合には出力されるアナログビデオ信号または SDIビデオ信 号にフレーム落ちが生じ、 PC側からの転送速度が遅い場合には出力されるアナ口 グビデオ信号または SDIビデオ信号にフレームの繰リ返しが発生するという問題 がある。
このようなフレーム落ちやフレームの繰り返しが発生するタイミングは予測す ることが困難であり、 PC側に搭載されたビデオ編集ソフトウェアにょリフレーム 単位で正確に編集が行われたにも拘らず、 最終的に出力される画像にはフレーム 落ちやフレームの繰り返しなどの欠陥が不定期的に発生するおそれがある。
本発明は、 情報処理装置から出力されるデータを異なるフォーマツ卜のデータ にリアルタイムで変換する際に、 データの転送と変換されたデータの出力を同期 させることにより、 動画像データにおけるフレーム落ちやフレーム繰り返しなど の画像の欠陥が生じることを防止するデータ変換システムを提供する。
(発明の開示）
本発明の請求項 1に係るデータ変換システムは、 IEEE1394バス上の第 1ノー ドと第 2ノードとのうちいずれか一方がサイクルマスタとなり、 サイクルマスタ が出力するサイクルスタートパケットに同期して、 第 1ノードから第 2ノードへ の第 1データの転送を行うとともに、 第 2ノードにおいて第 1データから変換さ れた第 2データを外部から入力されるリファレンス信号に同期して出力するデ一 タ変換システムであって、 第 1 ノードおよび第 2ノードの少なくとも一方に設け られ、 外部から入力されるリファレンス信号を受信する外部同期信号受信部と、 サイクルマスタが出力するサイクルスタートバケツ卜の周波数を外部同期信号受 信部で受信したリファレンス信号に同期させる同期調整部とを備える。
この場合、 サイクルスタートバケツ卜の周波数がリファレンス信号と同期する ことにより、 第 1ノードから出力されるデータの転送レー卜と、 第 2ノードから 出力される第 2データの出力レートとを一致させることができ、 出力される第 2 データ中にデータの欠落や繰り返しが発生することを防止できる。 特に、 DVフォ 一マツトなどのビデオ信号を異なるフォーマツ卜のビデオ信号に変換する際には 、 フレーム落ちやフレームの繰り返しなどの画像欠陥の発生を防止することが可 能となる。
本発明の請求項 2に係るデータ変換システムは請求項 1に記載のデータ変換シ ステムであって、 第 1ノードは第 1データとして DVフォーマットのビデオ信号を 出力する 13940HCI準拠の IEEE1394ィンタ一フェイスを備えるハードウェアで あり、 第 2ノードは第 2データとしてアナログビデオ信号または SDIビデオ信号 を出力するデータ変換ハードウエアである。
この場合、 DVフォーマツ卜のビデオ信号の出力をリファレンス信号に同期した 周波数で出力することにより、 アナログビデオ信号または SDIビデオ信号にフレ ー厶落ちやフレームの繰り返しなどの画像欠陥が発生することを防止できる。 本発明の請求項 3に係るデータ変換システムは請求項 1または 2に記載のデー タ変換システムであって、 第 2ノードは、 外部同期信号受信部および同期調整部 を備え、 データ転送時におけるサイクルマスタとなることを特徴とする。
この場合、 第 1ノード側から出力されるデータの転送レートを、 第 2ノードに おいて受信したリファレンス信号に同期させることができる。
本発明の請求項 4に係るデータ変換システムは請求項 1または 2に記載のデー タ変換システムであって、 第 1 ノードは同期調整部を備え、 第 2ノードは外部同 期信号受信部および同期調整部を備え、 サイクルマスタとなったノードの同期調 整部がサイクルスタートバケツ卜の周波数を外部同期信号受信部で受信したリフ ァレンス信号に同期させて出力する。
この場合、 第 1ノードおよび第 2ノードのいずれがサイクルマスタとなった場 合であっても、 外部同期信号受信部で受信したリファレンス信号に同期したデ一 タ転送を行うことが可能であり、 第 2ノードから出力されるデータ中に欠陥が発 生することを防止できる。
本発明の請求項 5に係るデータ変換システムは請求項 4に記載のデータ変換シ ステムであって、 第 1ノードがサイクルマスタとなった場合に、 第 2ノードの外 部同期信号受信部で受信したリファレンス信号に基づいて生成される同期調整用 信号を IEEE1394インターフェイスのァシンクロナス転送により第 2ノードから 第 1ノードに送信する。
この場合、 外部同期信号受信部で受信したリファレンス信号に基づいて生成さ れる同期調整用信号を IEEE1394バスを用いて送信しているので、 第 1 ノードが サイクルマスタとなった場合であっても、 特に配線を増加することなく同期調整 用信号を送信することが可能となる。
本発明の請求項 6に係るデータ変換システムは請求項 4に記載のデータ変換シ ステムであって、 第 1ノードがサイクルマスタとなった場合に、 第 2ノードの外 部同期信号受信部で受信したリファレンス信号に基づいて生成される同期調整用 信号を第 2ノードから第 1 ノードに送信するための専用同期信号線を備えている この場合、 第 2ノード側に外部同期用のリファレンス信号が入力され、 第 1ノ 一ドがサイクルマスタとなる場合であっても、 第 1ノードからのデータの転送レ ートを、 リファレンス信号に確実に同期させることが可能となる。
本発明の請求項 7に係るデータ変換システムは請求項 1または 2に記載のデー タ変換システムであって、 第 1ノードは、 外部同期信号受信部および同期調整部 を備え、 データ転送時におけるサイクルマスタとなることを特徴とする。
この場合、 第 1ノードから出力されるデータのフレーム周波数がすでに完全に 外部同期しているため、 第 2ノードでは単純に変換処理を行うだけでよく、 第 2 ノードが外部同期機能を持たない DVコンバータであってもシステム全体としてフ レーム落ちやフレーム繰り返しのない外部同期を実現することが可能となる。
(図面の簡単な説明）
図 1は、 第 1実施例の簡略ブロック図である。
図 2は、 第 2実施例の簡略ブロック図である。
図 3は、 第 3実施例の簡略ブロック図である。
(発明を実施するための最良の形態）
本発明では、 IEEE1394バス上のノードとして、 13940HCI準拠の IEEE1394ィ ンターフェイスを備えたハードウェア （PC) と、 PCから出力される DVビデオ信 号をアナログビデオ信号または SDIビデオ信号に変換して出力する変換ハードウ エア （以下、 DVコンバータと称す） とが接続されている場合を考察する。 PCの 1 394OHCI準拠の IEEE1394ィンターフェイスから出力される DVフォ一マツ 卜の ビデオ信号は、 ァイソクロナス転送モードで第 2ノードである DVコンバータに転 送される。
アイソク口ナス転送モードは、 IEEE1394バス上のサイクルマスタと呼ばれる ノードによって管理され、 サイクルマスタが 125j« sec毎に出力するサイクルスタ 一トバケツ卜に基づいて、 PCの 13940HCI準拠の IEEE1394インターフェイスか ら DVフォーマツ卜のビデオ信号が出力される。
このサイクルスタートバケツ卜の間隔は、 サイクルマスタのクロックソース 24· 576MHzから一定比で分周されており、 外部同期回路に入力されるリファレンス 信号とのずれが生じることから、 DVコンバー夕で変換されたアナ口グビデオ信号 や SDIビデオ信号を出力する際にバッファリングを行ったとしてもフレーム落ち やフレームの繰り返しなどの欠陥が生じることとなる。 このため、 本発明では、 サイクルマスタのク口ックソースの周波数をリファレンス信号によリフィ一ドバ ック制御して、 サイクルマスタが出力するサイクルスタートバケツ卜の間隔を 12 5 secよリ長くしたり短くしたりして、 その結果として IEEE1394の転送レ一卜 を動的に変化させ、 それにより、 13940HCI準拠の IEEE1394インターフェイス から出力される DVフォ一マットのビデオ信号のフレーム周波数の平均を外部同期 用のリファレンス信号の周波数に一致させるようにしている。
以下に、 具体的な実施例に基づいて詳細に説明する。
〈実施例 1〉
本発明の第 1実施例について図 1に基づいて説明する。
図 1では、 13940HCI準拠の IEEE1394ハードウェアである PC10と、 DVフォ 一マツ卜のビデオ信号をアナログビデオ信号または SDIビデオ信号に変換する DV コンバータ 20とが IEEE1394ケーブル 30によリ接続されている。
PC10には、 DVフォーマツ卜の動画像データを格納するハードディスクなどの 記録媒体を含む DVデータ処理部 11、 IEEE1394で定義されているパケットの形式 でデータを入出力する IEEE1394回路 12、 水晶発振子などで構成されるクロック ソース 13とを備えている。 なお、 PC10内には、 CPU、 ROM, RAM, その他の インターフェイス類が内蔵されており、 図面ではこれらの機能部は省略している 。 また、 PC10では、 少なくとも DVフォーマットのデータを編集するためのビデ ォ編集ソフトウェアが実行可能な環境となっており、 DVデータ処理部 11および I EEE1394回路 12を介して出力することが可能となっている。
DVコンバータ 20には、 IEEE1394ケーブル 30を介して転送されてくる DVフォ 一マツ卜のビデオ信号を受信するための IEEE1394回路 21、 転送されてくる DVフ ォーマツ卜のビデオ信号をアナログビデオ信号または SDIビデオ信号に変換する データ変換回路 23、 変換されたビデオ信号を一旦バッファリングするフレームバ ッファ 24、 外部からのリファレンス信号を受信する外部同期回路 25、 外部同期回 路 25による電圧のフィードバック制御を受けるクロック発振回路 VCXO (Voltage Controlled Crystal Oscillator) 22を備えている。 この DVコンバータ 20につい ても、 CPU、 ROM, RAM, 各種インターフェイスなどを内蔵しており、 図面で はこれらの機能部を省略している。
このようにした第 1実施例では、 DVコンバータ 20側の IEEE1394ノ一ドがサイ クルマスタになる。 サイクルマスタとなった DVコンバータ 20の IEEE1394回路 21 は、 125 sec毎にサイクルスタートバケツトを IEEE1394バス上に出力するが、 このサイクルスタートバケツ卜の間隔を決定するクロック発振回路が外部同期回 路 25によって制御されている。
外部同期回路 25は、 入力されるリファレンス信号と、 出力されるアナログビデ ォ信号または SDIビデオ信号のタイミング差を一定に保つように、 VCXO22の電 圧をフィードバック制御して VCX022の発振周波数を制御する。 このことにより 、 VCXO22のクロックを一定比で分周して生成されるサイクルスタートバケツト の出力間隔が変化し、 このサイクルスタートバケツ卜の間隔により決まる PC10の 1394OHCI準拠の IEEE1394側からの転送レートも、 リファレンス信号と同期さ せることができる。
このようにして、 DVコンバータ 20では、 PC10の 13940HCI準拠 IEEE1394ィ ンターフェイスからの DVビデオ信号の転送を受けて、 データ変換後のアナ口グビ デォ信号また SDIビデオ信号をフレーム落ちやフレームの繰り返しなどの欠陥の ない状態でリファレンス信号に完全に同期して出力することが可能となる。
この第 1実施例の場合、 PC10側の IEEE1394ハードウエアは標準品のままで構 成することができる。
〈実施例 2〉
IEEE1394/くスに接続された PCおよぴ DVコンバータの IEEE1394回路のうちい ずれがサイクルマスタになるか特定できない場合がある。 DVコンノ 一タ側がサイ クルマスタになれなかった場合には、 PC側の IEEE1394ノードがサイクルマスタ となることとなり、 PC側のクロック発振周波数をリファレンス信号に同期するよ うに制御する必要がある。 このような場合を、 本発明の第 2実施例として、 図 2 に基づいて説明する。
図 2では、 1394OHCI準拠の IEEE1394ハードウェアである PC10と、 DVフォ 一マツ卜のビデオ信号をアナログビデオ信号または SDIビデオ信号に変換する DV コンバータ 20とが IEEE1394ケーブル 30により接続されている。
PC10には、 DVフォーマツ卜の動画像データを格納するハードディスクなどの 記録媒体を含む DVデータ処理部 11、 IEEE1394で定義されているバケツ卜の形式 でデータを入出力する IEEE1394回路 12、 電圧のフィードバックにより発振周波 数の制御が可能な VCX014を備えている。 前述と同様に、 PC10内には、 CPU、 R OM、 RAM. その他のインタ一フェイス類が内蔵されており、 図面ではこれらの 機能部は省略している。 また、 PC10では、 少なくとも DVフォーマットのデータ を編集するためのビデオ編集ソフトウエアが実行可能な環境となっており、 DVデ ータ処理部 11および IEEE1394回路 12を介して出力することが可能となっている o
DVコンバータ 20には、 IEEE1394ケーブル 30を介して転送されてくる DVフォ 一マツ卜のビデオ信号を受信するための IEEE1394回路 21、 転送されてくる DVフ ォーマツ卜のビデオ信号をアナログフォーマツ卜のビデオ信号または SDIフォー マツ卜のビデオ信号に変換するデータ変換回路 23、 変換されたビデオ信号を一旦 バッファリングするフレームバッファ 24、 外部からのリファレンス信号を受信す る外部同期回路 25、 外部同期回路 25による電圧のフィードバック制御を受けるク ロック発振回路 VCXO (Voltage Controlled Crystal Oscillator) 22を備えてい る。 この DVコンバータ 20についても、 CPU、 ROM. RAM、 各種インタ一フエ イスなどを内蔵しており、 図面ではこれらの機能部を省略している。
このようにした第 2実施例では、 DVコンバータ 20側の IEEE1394ノ一ドがサイ クルマスタになった場合は、 第 1実施例と同様にして、 入力されるリファレンス 信号と、 アナログビデオ信号または SDIビデオ信号のタイミング差を一定に保つ ように、 VCXO22の電圧をフィードバック制御して VCXO22の発振周波数を制御 する。 このことにより、 VCX022のクロックを一定比で分周して生成されるサイ lo J クルスター卜バケツ卜の出力間隔が変化し、 このサイクルスタートバケツ卜の間 隔によリ決まる: PC10の 13940HCI準拠の IEEE1394側からの転送レートも、 リフ アレンス信号と同期させることができる。
また、 PC10側の IEEE1394ノードがサイクルマスタになった場合には、 DVコ ンバータ 20の外部同期回路 25で受信したリファレンス信号を IEEE1394ケーブル 3 0により PC10側に送信し、 リファレンス信号とサイクルスタートパケットとのタ ィミング差を一定に保つように、 PC10側の VCXO14をフィードバック制御する。 リファレンス信号を DVコンバータ 20から PC10に送信するには、 非同期 （Asynch ronous) 転送モードで転送することができ、 この場合、 PC10側に AV/Cプロトコ ルにより送信されてくるコマンドを解釈するためのアルゴリズムなどを備える必 要がある。 このことにより、 VCX014のクロックを一定比で分周して生成される サイクルスタートバケツ卜の出力間隔が変化し、 このサイクルスター卜バケツト の間隔によリ決まる PC10の 13940HCI準拠の IEEE1394側からの転送レートも、 リファレンス信号と同期させることができる。
このようにして、 第 2実施例では、 PC10と DVコンバータ 20のうちいずれがサ ィクルマスタとなった場合でも、 データ変換後のアナログビデオ信号また SDIビ デォ信号をフレーム落ちやフレームの繰り返しなどの欠陥のない状態でリファレ ンス信号に完全に同期して出力することが可能である。
〈変形例〉
DVコンバータ 20の外部同期回路 25に入力されるリファレンス信号に基づいて 生成される同期調整用信号を PC10側に送信するための専用制御信号線 31を別途 設けることが可能である。 この場合、 リファレンス信号に基づいて生成される同 期調整用信号を専用制御信号線 31により確実に送信し、 PC10側の VCX014のフ イードバック制御を行うことが可能となる。
〈実施例 3〉
PC側に外部同期用のリファレンス信号を入力し、 このリファレンス信号に同期 するように PC側か DVコンバータへの転送周波数を制御するように構成するこ とが可能である。 このような場合を第 3実施例として図 3に基づいて説明する。 図 3では、 1394OHCI準拠の IEEE1394ハードウェアである PC10と、 DVフォ 一マツ卜のビデオ信号をアナログビデオ信号または SDIビデオ信号に変換する DV コンバ一タ 20とが IEEE1394ケーブル 30によリ接続されている。
PC10【こは、 DVフォーマツ卜の動画像データを格納するハードディスクなどの 記録媒体を含む DVデータ処理部 11、 IEEE1394で定義されているパケットの形式 でデータを入出力する IEEE1394回路 12、 電圧のフィードバックによリ発振周波 数の制御が可能な VCX014および外部からのリファレンス信号を受信する外部同 期回路 15を備えている。 前述と同様に、 PC10内には、 CPU、 ROM, RAM. そ の他のインターフェイス類が内蔵されており、 図面ではこれらの機能部は省略し ている。 また、 PC10では、 少なくとも DVフォーマツ卜のデータを編集するため のビデオ編集ソフトウエアが実行可能な環境となっており、 DVデータ処理部 11お よぴ IEEE 1394回路 12を介して出力することが可能となっている。
DVコンバータ 20には、 IEEE1394ケーブル 30を介して転送されてくる DVフォ 一マツ卜のビデオ信号を受信するための IEEE1394回路 21、 転送されてくる DVフ ォーマツ卜のビデオ信号をアナログビデオ信号または SDIビデオ信号に変換する データ変換回路 23、 水晶発振子などで構成されるクロックソース 26などを備えて いる。 この DVコンバータ 20についても、 CPU、 ROM, RAM, 各種インターフ ェイスなどを内蔵しており、 図面ではこれらの機能部を省略している。
このようにした第 3実施例では、 PC10の外部同期回路 15で受信したリファレ ンス信号に基づいて、 リファレンス信号とサイクルスタートパケットとのタイミ ング差を一定に保つように、 PC10側の VCX014をフィードバック制御する。 この ことにより、 VCX014のクロックを一定比で分周して生成されるサイクルスター トバケツ卜の出力間隔が変化し、 このサイクルスタートバケツ卜の間隔により決 まる PC10の 13940HCI準拠の IEEE1394側からの転送レ一卜も、 リファレンス信 号と同期させることができる。 なお、 この場合、 PC10の IEEE1394ノードがサイ クルマスタになる必要がある。
このようにして、 第 3実施例では、 データ変換後のアナログビデオ信号また SD Iビデオ信号をフレーム落ちゃフレームの繰リ返しなどの欠陥のない状態でリファ レンス信号に完全に同期して出力することが可能である。 この第 3実施例の場合、 DVコンバータ 20側のハードウエアは汎用品をそのま ま用いて構成することが可能となる。 このようにして、 本発明によれば、 外部同期用のリファレンス信号に同期して 出力されるデータと、 13940HCI準拠の IEEE1394インターフェイスを介して出 力されるデータのフレーム周波数を同期させることができ、 フレーム周波数のず れに基づくフレーム落ちやフレームの繰り返しなどのデータの欠陥を防止するこ とが可能となる。
(産業上の利用可能性）
本発明では、 DVフォーマットでのビデオ信号を PCから出力し、 これをアナ口 グビデオ信号や SDIビデオ信号に変換する際に、 IEEE1394による転送レートと 出力フレームレートを同期させて、 フレーム落ちやフレームの繰り返しなどの画 像欠陥の発生を防止できる。 変換を行うデータフォーマットは、 実施例に説明し たものに限定されるものではなく、 アナログビデオ信号、 SDIビデオ信号、 DVビ デォ信号、 MPEG1、 MPEG2、 MPEG4. その他のフォーマットのビデオ信号間 の相互変換などに適用することが可能である。 また、 動画像データに限定される ものではなく、 音声データに適用することも可能である。

Claims

請 求 の 範 囲
1 .
IEEE1394バス上の第 1ノードと第 2ノードとのうちいずれか一方がサイクル マスタとなり、 前記サイクルマスタが出力するサイクルスタートパケットに同期 して、 前記第 1ノードから第 2ノードへの第 1データの転送を行うとともに、 第 2ノードにおいて第 1データから変換された第 2データを外部から入力されるリ ファレンス信号に同期して出力するデータ変換システムであって、
前記第 1ノ一ドおよび第 2ノ一ドの少なくとも一方に設けられ、 外部から入力 されるリファレンス信号を受信する外部同期信号受信部と、
前記サイクルマスタが出力するサイクルスター卜バケツ卜の周波数を前記外部 同期信号受信部で受信したリファレンス信号に同期させる同期調整部と、 を備えるデータ変換システム。
2 .
前記第 1ノードは第 1データとして DVフォーマツ卜のビデオ信号を出力する 1 394OHCI準拠の IEEE1394インタ一フェイスを備えるハ一ドウエアであり、 前記 第 2ノードは第 2データとしてアナログビデオ信号または SDIビデオ信号を出力 するデータ変換ハードウェアである、 請求項 1に記載のデータ変換システム。
3 .
前記第 2ノードは、 前記外部同期信号受信部および同期調整部を備え、 データ 転送時におけるサイクルマスタとなる、 請求項 1または 2に記載のデータ変換シ ステム。
4.
前記第 1ノードは前記同期調整部を備え、 前記第 2ノードは前記外部同期信号 受信部および同期調整部を備え、 サイクルマスタとなったノードの同期調整部が サイクルスター卜バケツ卜の周波数を前記外部同期信号受信部で受信したリファ レンス信号に同期させて出力する、 請求項 1または 2に記載のデータ変換システ ム。
5 . 前記第 1ノードがサイクルマスタとなった場合に、 第 2ノードの外部同期信号 受信部で受信したリファレンス信号を IEEE1394インターフェイスのァシンク口 ナス転送により第 2ノードから第 1 ノードに送信する、 請求項 4に記載のデータ 変換システム。
6.
前記第 1ノードがサイクルマスタとなった場合に、 第 2ノードの外部同期信号 受信部で受信したリファレンス信号を第 2ノードから第 1ノードに送信するため の専用同期信号線を備える、 請求項 4に記載のデータ変換システム。
7 .
前記第 1ノードは、 前記外部同期信号受信部および同期調整部を備え、 データ 転送時におけるサイクルマスタとなる、 請求項 1または 2に記載のデータ変換シ ステム。
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US20070046512A1 (en) 2007-03-01
EP1667447B1 (en) 2011-11-23
CN1839624A (zh) 2006-09-27
CN101472171B (zh) 2012-11-21
JP4228081B2 (ja) 2009-02-25
CN101472171A (zh) 2009-07-01
US8285896B2 (en) 2012-10-09
AU2003264500A1 (en) 2005-04-11
CN100466710C (zh) 2009-03-04
EP1667447A1 (en) 2006-06-07
EP1667447A4 (en) 2009-03-04
JPWO2005029853A1 (ja) 2006-11-30

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