WO2000028664A2 - Fully integrated tuner architecture - Google Patents
Fully integrated tuner architecture Download PDFInfo
- Publication number
- WO2000028664A2 WO2000028664A2 PCT/US1999/026700 US9926700W WO0028664A2 WO 2000028664 A2 WO2000028664 A2 WO 2000028664A2 US 9926700 W US9926700 W US 9926700W WO 0028664 A2 WO0028664 A2 WO 0028664A2
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- filter
- frequency
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- 239000013078 crystal Substances 0.000 claims abstract description 115
- 238000000034 method Methods 0.000 claims abstract description 92
- 239000000758 substrate Substances 0.000 claims abstract description 64
- 238000006243 chemical reaction Methods 0.000 claims abstract description 61
- 238000001914 filtration Methods 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 22
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 22
- 230000008054 signal transmission Effects 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims description 100
- 230000004044 response Effects 0.000 claims description 59
- 239000000872 buffer Substances 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 38
- 238000001228 spectrum Methods 0.000 claims description 23
- 238000012545 processing Methods 0.000 claims description 21
- 239000010453 quartz Substances 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 230000003321 amplification Effects 0.000 claims description 11
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 238000002156 mixing Methods 0.000 claims description 8
- 230000003993 interaction Effects 0.000 claims description 7
- 230000002238 attenuated effect Effects 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 6
- 230000005236 sound signal Effects 0.000 claims description 4
- 230000001276 controlling effect Effects 0.000 claims 7
- 230000005669 field effect Effects 0.000 claims 4
- 230000001105 regulatory effect Effects 0.000 claims 2
- 230000003362 replicative effect Effects 0.000 claims 2
- 238000010079 rubber tapping Methods 0.000 claims 1
- 230000000007 visual effect Effects 0.000 claims 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 abstract description 12
- 230000010355 oscillation Effects 0.000 abstract description 3
- 229920000729 poly(L-lysine) polymer Polymers 0.000 abstract 2
- 238000013461 design Methods 0.000 description 81
- 238000010586 diagram Methods 0.000 description 64
- 230000006870 function Effects 0.000 description 34
- 230000001965 increasing effect Effects 0.000 description 32
- 239000000047 product Substances 0.000 description 32
- 230000000737 periodic effect Effects 0.000 description 28
- 230000005540 biological transmission Effects 0.000 description 21
- 230000008901 benefit Effects 0.000 description 17
- 230000000694 effects Effects 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 101100082028 Arabidopsis thaliana PLL2 gene Proteins 0.000 description 9
- 230000010363 phase shift Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 8
- 230000001419 dependent effect Effects 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000002829 reductive effect Effects 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
- 238000010276 construction Methods 0.000 description 7
- 238000006731 degradation reaction Methods 0.000 description 7
- 230000006872 improvement Effects 0.000 description 7
- 238000003780 insertion Methods 0.000 description 7
- 230000037431 insertion Effects 0.000 description 7
- 230000010354 integration Effects 0.000 description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 238000013459 approach Methods 0.000 description 6
- 238000004422 calculation algorithm Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
- 230000002452 interceptive effect Effects 0.000 description 5
- 230000035945 sensitivity Effects 0.000 description 5
- 230000001629 suppression Effects 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 4
- 230000000593 degrading effect Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000007493 shaping process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000001747 exhibiting effect Effects 0.000 description 3
- 230000036039 immunity Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000011144 upstream manufacturing Methods 0.000 description 3
- 101100350613 Arabidopsis thaliana PLL1 gene Proteins 0.000 description 2
- 101100013145 Drosophila melanogaster Flo2 gene Proteins 0.000 description 2
- 230000018199 S phase Effects 0.000 description 2
- 101100066910 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FLO1 gene Proteins 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005094 computer simulation Methods 0.000 description 2
- 238000006880 cross-coupling reaction Methods 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000000638 solvent extraction Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000009466 transformation Effects 0.000 description 2
- 238000013519 translation Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 101100120289 Drosophila melanogaster Flo1 gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004870 electrical engineering Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000008713 feedback mechanism Effects 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000009022 nonlinear effect Effects 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/18—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by means of synchronous gating arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
- H03B5/36—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
- H03B5/364—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device the amplifier comprising field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/161—Multiple-frequency-changing all the frequency changers being connected in cascade
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/18—Modifications of frequency-changers for eliminating image frequencies
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
- H03F3/45188—Non-folded cascode stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/12—Frequency selective two-port networks using amplifiers with feedback
- H03H11/1291—Current or voltage controlled filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/46—One-port networks
- H03H11/53—One-port networks simulating resistances; simulating resistance multipliers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/54—Modifications of networks to reduce influence of variations of temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/004—Switched capacitor networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/24—Frequency- independent attenuators
- H03H7/25—Frequency- independent attenuators comprising an element controlled by an electric or magnetic variable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
- H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
- H03J1/0058—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor provided with channel identification means
- H03J1/0066—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor provided with channel identification means with means for analysing the received signal strength
- H03J1/0075—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor provided with channel identification means with means for analysing the received signal strength where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/02—Details
- H03J3/04—Arrangements for compensating for variations of physical values, e.g. temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/02—Details
- H03J3/06—Arrangements for obtaining constant bandwidth or gain throughout tuning range or ranges
- H03J3/08—Arrangements for obtaining constant bandwidth or gain throughout tuning range or ranges by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/02—Details
- H03J3/16—Tuning without displacement of reactive element, e.g. by varying permeability
- H03J3/18—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance
- H03J3/185—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance with varactors, i.e. voltage variable reactive diodes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
- H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
- H03L7/103—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator the additional signal being a digital signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0053—Printed inductances with means to reduce eddy currents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F21/00—Variable inductances or transformers of the signal type
- H01F21/12—Variable inductances or transformers of the signal type discontinuously variable, e.g. tapped
- H01F2021/125—Printed variable inductor with taps, e.g. for VCO
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- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/40—Structural association with built-in electric component, e.g. fuse
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/42—Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
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- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
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- H—ELECTRICITY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/447—Indexing scheme relating to amplifiers the amplifier being protected to temperature influence
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/63—Indexing scheme relating to amplifiers the amplifier being suitable for CATV applications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45264—Indexing scheme relating to differential amplifiers the dif amp comprising frequency or phase stabilisation means
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- H—ELECTRICITY
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- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45286—Indexing scheme relating to differential amplifiers the temperature dependence of a differential amplifier being controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/10—Tuning of a resonator by means of digitally controlled capacitor bank
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
Definitions
- This application relates generally to receiver circuits and, in particular to a CATV tuner with a frequency plan and architecture that allows the entire receiver, including the filters, to be integrated onto a single integrated circuit.
- Radio receivers are widely used in applications requiring the reception of electromagnetic energy.
- Applications can include broadcast receivers such as radio and television, set top boxes for cable television, receivers in local area networks, test and measurement equipment, radar receivers, air traffic control receivers, and microwave communication links among others.
- Transmission ofthe electromagnetic energy may be over a transmission line or by electromagnetic radio waves.
- the design of a receiver is one ofthe most complex design tasks in electrical engineering.
- a fully integrated tuner architecture having all channel selectivity and image rejection integrated onto a single silicon substrate.
- An embodiment of a fully integrated tuner architecture comprises a substrate upon which a receiver circuit that utilizes differential signal transmission.
- a mixer creates a first intermediate frequency that is higher than the received signal.
- the first up conversion has been performed to provide image frequency rejection for the second mixing stage.
- a first intermediate frequency filter attenuates the image frequencies and provides channel selectivity.
- This filter is preferably an LC filter that has inductors disposed upon the substrate. The Q ofthe inductors is adjusted with an inductor tuning algorithm, and the center frequency ofthe filter is adjusted by a filter tuning algorithm.
- An image reject mixer is next used to reduce the image rejection requirements ofthe first filter by further attenuating the amplitude ofthe image frequencies.
- the second intermediate frequency created by this mixer is lower than the first intermediate frequency.
- the second intermediate frequency undergoes filtering by a filter that is constructed on the substrate.
- This filter contains integrated inductors on the substrate with their Q adjusted by an inductor tuning algorithm.
- the frequency response ofthe filter is centered using a filter tuning algorithm.
- a third image reject mixer converts the second intermediate frequency to the third intermediate frequency. This mixer reduces the image rejection requirements of the previous filter and converts the second intermediate frequency to the third intermediate frequency.
- a third intermediate frequency filter further reduces the distortion present with the signal.
- This filter utilizes tuning algorithms to adjust the quality factor ofthe integrated inductors and to center the frequency response ofthe filter.
- the frequency synthesizer implemented on the substrate uses a differential crystal oscillator for a reference signal is an on chip synthesizer.
- the first and second local oscillator signals are produced by indirect synthesis.
- the third local oscillator signal is produced by direct synthesis, to reduce distortion of this in band local oscillator signal.
- the fully integrated tuner architecture advantageously uses differential signal transmission to minimize the introduction of external distortion and noise into the circuit. Differential signal transmission increases noise rejection of noise that has been generated on the semiconductor substrate, and is injected into the receiver signal path.
- FIG. 1 is an illustration of a portion ofthe over-the-air broadcast spectrum allocations in the United States
- FIG. 2 is an illustration ofthe frequency spectrum of harmonic distortion products
- FIG. 3 is an illustration of a spectrum of even and odd order intermodulation distortion products
- FIG. 4 is an illustration of interference caused at the IF frequency by a signal present at the image frequency
- FIG. 5 is an illustration of a typical dual conversion receiver utilizing an up conversion and a subsequent down conversion
- FIG. 6 is a semi-schematic simplified timing diagram of differential signals, including a common mode component, as might be developed by a differential crystal oscillator in accordance with the invention
- FIG. 7 is a semi-schematic block diagram of a differential crystal oscillator, including a quartz crystal resonator and oscillator circuit differentially coupled to a linear buffer amplifier in accordance with the invention
- FIG. 8 is a simplified schematic illustration of differential signals present at the output of a crystal resonator
- FIG. 9 is a simplified schematic diagram of a quartz crystal resonator equivalent circuit
- FIG. 10 is a simplified graphical representation of a plot of impedance vs. frequency for a crystal resonator operating near resonance
- FIG. 11 is a simplified graphical representation of a plot of phase vs. frequency for a crystal resonator operating near resonance
- FIG. 12 is a simplified schematic diagram ofthe differential oscillator circuit of FIG. 7;
- FIG. 13 is a simplified, semi-schematic block diagram of a periodic signal generation circuit including a crystal oscillator having balanced differential outputs driving cascaded linear and non-linear buffer stages;
- FIG. 14 is a simplified schematic diagram of a differential folded cascade linear amplifier suitable for use in connection with the present invention.
- FIG. 15 is a simplified, semi-schematic diagram of a differential nonlinear buffer amplifier suitable for use as a clock buffer in accordance with the invention.
- FIG. 16 is a semi-schematic illustration of an alternative embodiment ofthe differential oscillator driver circuit
- FIG. 17 is an block diagram of a differential crystal oscillator as a reference signal generator in a phase-lock-loop
- FIG. 18 is a simplified block diagram of an illustrative frequency synthesizer that might incorporate the differential periodic signal generation circuit ofthe invention.
- FIG. 19 is a block diagram illustrating the exemplary frequency conversions for receiver tuning utilized in the embodiments ofthe invention.
- FIG. 20 is a block diagram of an exemplary tuner designed to receive a 50 to 860 MHz bandwidth containing a multiplicity of channels;
- FIG.21 is an exemplary table of frequencies utilizing coarse and fine PLL tuning to derive a 44 MHz IF;
- FIG. 22 is an illustration of an alternative embodiment ofthe coarse and fine PLL tuning method to produce an exemplary final IF of 36 MHz;
- FIG.23 is a block diagram of a dummy component used to model an operative component on an integrated circuit chip;
- FIG. 24a is a block diagram of a tuning process
- FIG. 24b is a flow diagram ofthe tuning process
- FIG. 24c is an exemplary illustration ofthe tuning process
- FIG. 25 is a block diagram of an exemplary tuning circuit
- FIG. 26 illustrates the amplitude and phase relationship in an LC filter at resonance
- FIG. 27 is a schematic diagram showing the configuration of switchable capacitors in a differential signal transmission embodiment
- FIG. 28 is an illustration of a typical spiral inductor suitable for integrated circuit applications
- FIG. 29 is an illustration of the effect of decreasing "Q" on the selectivity of a tuned circuit
- FIG. 30 is an illustration of a typical filter bank utilized in embodiments of the invention for filtering I and Q IF signals
- FIG. 31 is a diagram of a transconductance stage with an LC load
- FIG. 32 shows a transconductance stage with an LC load and Q enhancement
- FIG. 33 shows a method of tuning inductor Q over temperature
- FIG. 34 is a block diagram of a communications network utilizing a receiver according to any one ofthe exemplary embodiments ofthe invention.
- FIG. 35 is an is an illustration ofthe input and output signals ofthe integrated switchless programmable attenuator and low noise amplifier
- FIG. 36 is a functional block diagram of the integrated switchless programmable attenuator and low noise amplifier circuit
- FIG. 37 is a simplified diagram showing the connection of multiple attenuator sections to the output ofthe integrated switchless programmable attenuator and low noise amplifier;
- FIG. 38 is an illustration of an exemplary embodiment showing how the attenuator can be removed from the circuit so that only the LNAs are connected;
- FIG. 39 is an attenuator circuit used to achieve one dB per step attenuation
- FIG. 40 is an exemplary embodiment of an attenuator for achieving a finer resolution in attenuation then shown in FIG. 5;
- FIG. 41 is an illustration of the construction of series and parallel resistors used in the attenuator circuit ofthe integrated switchless programmable attenuator and low noise amplifier;
- FIG. 42 is an illustration of a preferred embodiment utilized to turn on current tails ofthe differential amplifiers
- FIG. 43 is an illustration of an embodiment showing how the individual control signals used to turn on individual differential pair amplifiers are generated from a single control signal
- FIG. 44 is an illustration of an embodiment of comparator circuitry used to activate individual LNA amplifier stages
- FIG. 45 is a block diagram illustrating the exemplary generation of the local oscillator signals utilized in the embodiments ofthe invention.
- FIG. 46 is a schematic of a PLL having its VCO controlled by an embodiment of a VCO tuning control circuit
- FIG. 47 is a process flow diagram illustrating the process of tuning the VCO with an embodiment of a VCO control circuit
- FIG. 48 is a block diagram of the first exemplary embodiment ofthe invention
- FIG.49 is an illustration ofthe frequency planning utilized in the exemplary embodiments ofthe invention
- FIG. 50 is a block diagram showing how image frequency cancellation is achieved in an I/Q mixer
- FIG. 51 is a block diagram ofthe second exemplary embodiment ofthe present invention
- FIG. 52 is a block diagram of the third exemplary embodiment ofthe present invention
- FIG. 53 is a block diagram of a CATV tuner that incorporates the fully integrated tuner architecture
- FIG. 54 is a block diagram of a low power embodiment of the receiver that has been configured to receive cable telephony signals.
- FIG. 55 is a block diagram of a set top box that incorporates the receiver embodiments
- FIG. 56 is a block diagram of a television that incorporates the receiver embodiments
- FIG. 57 is a block diagram of a VCR that incorporates the receiver embodiments.
- FIG. 58 is a block diagram of a cable modem that incorporates the integrated switchless programmable attenuator and low noise amplifier.
- FIG. 1 is an illustration of a portion of the radio frequency spectrum allocations by the FCC.
- Transmission over a given media occurs at any one of a given range of frequencies that are suitable for transmission through a medium.
- a set of frequencies available for transmission over a medium are divided into frequency bands 102.
- Frequency bands are typically allocations of frequencies for certain types of transmission.
- FM radio broadcasts FM being a type of modulation
- AM Amplitude modulation
- AM is allocated the frequency band of 540 kHz to 1 ,600 kHz 106.
- the frequency band for a type of transmission is typically subdivided into a number of channels.
- a channel 112 is a convenient way to refer to a range of frequencies allocated to a single broadcast station.
- a station broadcasting on a given channel may transmit one or more radio frequency (RF) signals within this band to convey the information of a broadcast.
- RF radio frequency
- several frequencies transmitting within a given band may be used to convey information from a transmitter to a broadcast receiver.
- a television broadcast channel broadcasts its audio signal(s) 108 on a frequency modulated (FM) carrier signal within the given channel.
- a TV picture (P) 110 is a separate signal broadcast using a type of amplitude modulation (AM) called vestigial side band modulation (VSB), and is transmitted within this channel.
- AM amplitude modulation
- VSB vestigial side band modulation
- FIG. 1 channel allocations for a television broadcast band showing the locations of a picture and a sound carrier frequencies within a channel are shown.
- Each channel 112 for television has an allocated fixed bandwidth of 6 MHz.
- the picture 110 and sound 108 carriers are assigned a fixed position relative to each other within the 6 MHz band. This positioning is not a random selection.
- the picture and sound carriers each require a predetermined range of frequencies, or a bandwidth (BW) to sufficiently transmit the desired information.
- BW bandwidth
- a channel width is a fixed 6 MHz, with the picture and sound carrier position fixed within that 6 MHz band, and each carrier is allocated a certain bandwidth to transmit its signal.
- FIG. 1 it is seen that there are gaps between channels 114, and also between carrier signals 116. It is necessary to leave gaps of unused frequencies between the carriers and between the channels to prevent interference between channels and between carriers within a given channel. This interference primarily arises in the receiver circuit that is used to receive these radio frequency signals, convert them to a usable frequency, and subsequently demodulate them.
- Selectivity is a principal measure of receiver performance. Designing for sufficient selectivity not only involves rejecting other channels, but the rejection of distortion products that are created in the receiver or are part of the received signal. Design for minimization or elimination of spurious responses is a maj or obj ecti ve in state of the art receiver design.
- FIG.2 is an illustration of harmonic distortion products.
- Transmitted spurious signals, and spurious signals generated in a receiver most commonly consist of harmonics created by one frequency and intermodulation distortion, created by the interaction of multiple frequencies.
- Spurious signals at other than the desired frequency arise from the inherent nonlinear properties in the circuit components used. These nonlinearities can not be eliminated, but by careful engineering the circuitry can be designed to operate in a substantially linear fashion.
- spurious signals 204 are always generated with this fundamental.
- the spurious signals produced as a result of generating a single frequency (f) 202 are called harmonics 204 and occur at integer multiples of the fundamental frequency (2f, 3f, 7)
- the signal strength or amplitude of these harmonics decrease with increasing harmonic frequency. Fortunately these distortion products fall one or more octaves away from the desired signal, and can usually be satisfactorily filtered out with a low pass filter that blocks all frequencies above a pre-selected cut-off frequency.
- Radio signals do not exist in isolation.
- the radio frequency spectrum is populated by many channels within a given band transmitting at various frequencies.
- these frequencies interact, or intermodulate, to create distortion products that occur at known frequency locations.
- FIG. 3 is an illustration of intermodulation distortion products. Whenever two or more frequencies are present they interact to produce additional spurious signals that are undesired.
- FIG. 3 illustrates a spurious response produced from the interaction of two signals, f j 302 and f 2 304. This particular type of distortion is called intermodulation distortion (IMD).
- IMD intermodulation distortion
- These intermodulation distortion products 306 are assigned orders, as illustrated. In classifying the distortion the IM products are grouped into two families, even and odd order IM products. Odd order products are shown in FIG. 3.
- IM distortion performance specifications are important because they are a measure ofthe receiver's immunity to strong out of band signal interference.
- These unwanted signals may be generated in a transmitter and transmitted along with desired signal or are created in a receiver. Circuitry in the receiver is required to block these signals. These unwanted spurious responses arise from nonlinearities in the circuitry that makes up the receiver.
- the circuits that make up the receiver though nonlinear are capable of operating linearly if the signals presented to the receiver circuits are confined to signal levels within a range that does not call for operation of the circuitry in the nonlinear region. This can be achieved by careful design ofthe receiver.
- Frequency planning is the selection of local oscillator signals that create the intermediate frequency (IF) signals of the down conversion process. It is an analytical assessment of the frequencies being used and the distortion products associated with these frequencies that have been selected. By evaluating the distortion and its strength, an engineer can select local oscillator and IF frequencies that will yield the best overall receiver performance, such as selectivity and image response. In designing a radio receiver, the primary problems encountered are designing for sufficient sensitivity, selectivity and image response.
- Selectivity is a measure of a radio receiver's ability to reject signals outside ofthe band being tuned by a radio receiver.
- a way to increase selectivity is to provide a resonant circuit after an antenna and before the receiver's frequency conversion circuitry in a "front end.” For example, a parallel resonant circuit after an antenna and before a first mixer that can be tuned to the band desired will produce a high impedance to ground at the center ofthe band. The high impedance will allow the antenna signal to develop a voltage across this impedance. Signals out of band will not develop the high voltage and are thus attenuated.
- the out of band signal rejection is determined by a quality factor or "Q" of components used in the resonant circuit.
- Q quality factor
- a voltage developed across the resonant circuit at a tuned frequency band will be closer in value to the voltage developed across the resonant circuit out of band.
- an out of band signals would be closer in amplitude to an in band signals than if a high Q circuit were constructed.
- This type of resonant circuit used as a preselector will increase frequency selectivity of a receiver that has been designed with this stage at its input. If an active preselector circuit is used between an antenna and frequency conversion stages, the sensitivity ofthe receiver will be increased as well as improving selectivity. If a signal is weak its level will be close to a background noise level that is present on an antenna in addition to a signal. If this signal cannot be separated from the noise, the radio signal will not be able to be converted to a signal usable by the receiver. Within the receiver's signal processing chain, the signal's amplitude is decreased by losses at every stage ofthe processing. To make up for this loss the signal can be amplified initially before it is processed. Thus, it can be seen why it is desirable to provide a circuit in the receiver that provides frequency selectivity and gain early in the signal processing chain.
- Radio frequency tuners are increasingly being designed with major portions of their circuitry implemented as an integrated circuit.
- exotic materials such as gallium arsenide (GaAs) are used.
- GaAs gallium arsenide
- a receiver implemented on this type of material will typically have lower distortion and noise present than in a similarly constructed receiver constructed on silicon.
- Silicon is an attractive material due to its low cost.
- a CMOS circuit implemented on silicon has the additional benefit of having known processing characteristics that allow a high degree of repeatability from lot to lot of wafers.
- the state of the art has not achieved a completely integrated receiver in CMOS circuitry. A reason for this is the difficulty of eliminating receiver distortion and noise.
- the distortion products discussed above that are created in the receiver can, in the maj ority of cases, also be reduced by setting an appropriate drive level in the receiver, and by allowing a sufficient spacing between carriers and channels.
- These receiver design parameters are dependent upon many other factors as well, such as noise present in the system, frequency, type of modulation, and signal strength among others. Noise is one of the most important of these other parameters that determines the sensitivity ofthe receiver, or how well a weak signal may be satisfactorily received.
- Noise is present with the transmitted signal, and also generated within a receiver. If excessive noise is created in a receiver a weak signal may be lost in a "noise floor". This means that the strength ofthe received signal is comparable to the strength ofthe noise present, and the receiver is incapable of satisfactorily separating a signal out of this background noise, or floor. To obtain satisfactory performance a "noise floor" is best reduced early in a receiver's chain of circuit components.
- noise is generated inside the radio receiver.
- this internal noise predominates over the noise received with the signal of interest.
- the weakest signal that can be detected is determined by the noise level in the receiver.
- a "pre-amplifier" is often used after an antenna as a receiver front end to boost the signal level that goes into the receiver. This kind of pre-amplification at the front end ofthe amplifier will add noise to the receiver due to the noise that is generated inside of this amplifier circuit.
- the noise contribution of this amplifier can be minimized by using an amplifier that is designed to produce minimal noise when it amplifies a signal, such as an
- the overall gain is simply the sum ofthe gains ofthe individual amplifiers in decibels. For example, the total gain in a series of two amplifiers each having a gain of 10 dB is 20 dB for a overall amplifier.
- Noise floor is commonly indicated by the noise figure (NF). The larger the NF the higher the noise floor ofthe circuit.
- NF noise figure
- a Cascaded noise figure is not as easily calculated as amplifier gain; its calculation is non- intuitive.
- gain does not depend upon the positioning of the amplifiers in the chain. However, in achieving a given noise figure for a receiver, the placement ofthe amplifiers is critical with respect to establishing a receiver' s noise floor.
- Friis' equation is used to calculate the noise figure ofthe entire system. Friis' equation is NF. - 1 NF, - 1 - 1 NF l lal -NF. + 2 + 3 + .. + (1) ,otal ' G, G,G 2 G ⁇ G ⁇ . . G n
- NE total system noise figure
- NF X noise figure of stage- 1
- NE 2 noise figure of stage-2
- G 2 gain of stage-2
- G ⁇ gain of rath stage
- the noise figure of a first stage is the predominant contributor to a total noise figure.
- the noise figure of a system is only increased a small amount when a second amplifier is used.
- the noise figure ofthe first amplifier in a chain of amplifiers or system components is critical in maintaining a low noise floor for an entire system or receiver.
- a lowNF amplifier typically requires a low noise material for transistors, such as gallium arsenide. Later amplifiers that do not contribute significantly to the noise, are constructed of a cheaper and noisier material such as silicon.
- the initial low noise amplifiers are typically constructed from expensive materials such as gallium arsenide to achieve sufficient performance.
- Gallium arsenide requires special processing, further adding to its expense.
- GaAs circuits are not easily integrated with silicon circuits that make up the bulk of the receivers in use. It would be desirable to achieve identical performance with a less costly material, such as silicon. Silicon requires less costly processing. Further it is advantageous if a standard process, such as CMOS, could be used to achieve the required low noise design. Given the trend towards miniaturization and high volume production, it is highly desirable to be able to produce an integrated receiver with a low noise floor on silicon.
- the layout and spacing of circuitry is critical to avoid the injection of noise generated in other portions ofthe circuit onto a received signal. If a tuner is placed on a semiconductor substrate noise generated in the substrate itself will interfere with, and degrade the received signal, this has been a problem preventing complete integration of a receiver on silicon.
- CMOS advantageously is a known process that may be implemented economically for volume production.
- CMOS complementary metal-oxide-semiconductor
- the signal After preselection and low noise amplification that is performed in a front end of a receiver, the signal next enters the receiver's frequency conversion circuitry.
- This circuitry takes channels that have been passed through the front end and converts one ofthe selected channel's frequencies down to one or more known frequencies (f IF or IFs).
- This frequency conversion is accomplished through the use of a circuit called a mixer that utilizes a local oscillator signal (f 0 ), usually generated in the receiver, to tune a received channel to an IF frequency while blocking the other channels.
- Spurious signals previously described, are produced in this receiver circuitry, and an additional problem known as "image response" is encountered that must be considered in the receiver's design.
- a mixer has three ports: f ⁇ receives a low level radio frequency signal that contains the desired modulation, f L0 is a high level signal from a local oscillator, and f IF is the resultant mixer product or intermediate frequency produced. These frequencies are related:
- One or more mixers are advantageously used in radio receivers to convert a high frequency radio signal which is received into a lower frequency signal that can be easily processed by subsequent circuitry.
- Mixers are also used to tune multiple channels, so that different tuned circuits are not required for each channel.
- circuit components used to process the intermediate frequency may be fixed in value, with no tuning of capacitors or coils required.
- circuits in an IF strip are all fixed-tuned at an IF frequency.
- a receiver constructed in this manner, using one or more frequency conversions, is called a superheterodyne radio receiver.
- a disadvantage of a superheterodyne radio receiver is that any ofthe one or more local oscillators within the receiver also acts as a miniature transmitter.
- a receiver "front end" alleviates this problem by isolating an antenna from the remaining receiver circuitry.
- a radio frequency amplifier By positioning a radio frequency amplifier between the antenna and the frequency converting stages of a receiver, additional isolation between the receiver circuitry and the antenna is achieved.
- the presence of an amplifier stage provides attenuation for any ofthe one or more local oscillator signals from the frequency conversion stages that are radiated back towards the antenna or a cable distribution network.
- This increased isolation has the benefit of preventing radiation of a local oscillator signal out the antenna which could cause radio frequency interference from a local oscillator. If radiated these and other signals present could create interference in another receiver present at another location.
- FIG. 4 is an illustration that shows an image frequency's 402 relation to other signals present 404, 406, 408 at a mixer.
- Image frequency suppression is an important parameter in a receivers design.
- two frequencies input to a radio receiver 404, 406 will yield a signal at the IF frequency 408.
- a receiver will simultaneously detect signals at the desired frequency 404 and also any signals present at an undesired frequency known as the image frequency 402. If there is a signal present at the image frequency, it will translate down to the IF frequency 408 and cause interference with the reception ofthe desired channel. Both of these signals will be converted to the IF frequency unless the receiver is designed to prevent this.
- the image frequency 402 is given by:
- f is the image frequency. This is illustrated in FIG. 4.
- a frequency that is spaced the IF frequency 410 below the local oscillator frequency (f RF ) 404, and a frequency that is spaced the intermediate frequency 412 above the local oscillator signal (fj) 402. will both be converted down to the intermediate frequency (f IF )408.
- the usual case is that a frequency that occurs lower than the local oscillator signal is the desired signal.
- the signal occurring at the local oscillator frequency plus the intermediate frequency 402 is an unwanted signal or noise at that frequency that is converted to the IF frequency causing interference with the desired signal.
- the exemplary 560 KHz signal 404 is a radio station that the tuner is tuned to receive.
- the exemplary 1470 KHz signal 402 is another radio station transmitting at that particular frequency. If a designer ofthe receiver had picked an exemplary local oscillator signal of 1015 KHz 406 then both of these radio stations would be simultaneously converted to an exemplary IF frequency of 455 KHz 408. The person listening to the radio would simultaneously hear both radio programs coming out of his speaker. This illustrates the need for the careful selection of local oscillator frequencies when designing a radio receiver.
- the selection of local oscillator frequencies is a part of frequency planning and used by those skilled in the art to design a receiver that will provide frequency conversions needed with minimal distortion.
- FIG. 5 illustrates a dual (or double) conversion receiver 502.
- a dual (or double) conversion receiver 502. Such a multiple conversion receiver allows selectivity, distortion and stability to be controlled through a judicious frequency planning.
- a received signal 504 is first mixed 506 to a first intermediate frequency, and then mixed 508 down to a second intermediate frequency.
- the first IF frequency is made to be high so that a good image rejection is achieved.
- the second IF is made low so that good adjacent channel selectivity is achieved.
- the selectivity ofthe receiver acts to attenuate the image frequency when a high IF frequency is used.
- a high image frequency provides less of a chance for interference from a high powered station. This is because at higher frequencies transmitted power is often lower due to the difficulties in generating RF power as frequency increases.
- a low second IF frequency produces a good adjacent channel selectivity. Frequency spacing between adjacent channels is fixed. To prevent interference from adjacent channels the receiver must possess a good selectivity. Selectivity can be achieved through a RF tuned circuit, and more importantly by the superior selectivity provided by a frequency conversion process.
- the selectivity improvement given by using a low IF is shown by considering a percent separation of a desired and an undesired signal relative to total signal bandwidth. If a separation between the desired and undesired signals is constant a second IF signal falling at the lower frequency will give a larger percent separation between the signals. As a result it is easier to distinguish between IF signals that are separated by a larger percentage of bandwidth.
- the judicious selection of two intermediate frequencies in a double conversion receiver is often used to achieve a given design goal, such as image frequency rejection and selectivity.
- a second IF frequency allows gain in the receiver to be distributed evenly. Distributing gain helps prevent instability in the receiver. Instability usually is seen as an oscillating output signal 512. Distributing the gain among several IF amplifiers 514, 516, 518 reduces the chance of this undesirable effect. Often to further distribute the gain required in a system design a third frequency conversion, and a third IF frequency, will be utilized.
- An amplifier in an IF strip does not require frequency tuning and provides signal gain to make up for signal losses, encountered in processing a received signal. Such losses can include conversion loss in mixers and the insertion loss encountered by placing a circuit element, such as a filter or an isolator in the IF strip.
- filters are used liberally to limit unwanted frequencies that have been escaped previous elimination in a "front end," or to eliminate unwanted frequencies that have been created immediately preceding a filter.
- a desired signal will also undergo some attenuation. This attenuation results from an insertion loss of a filter, or some other component, and if uncompensated, will degrade a signal. This is especially true when a series of filters are cascaded, since the effect is additive.
- a series of multiple filters are cascaded in a given IF strip. These filters typically have an identical response characteristic.
- the cascaded filters are used to increase the selectivity ofthe receiver. While it is true that the insertion loss in the pass band is the sum of individual filter insertion losses, as measured in decibels, a rejection improvement obtained outside ofthe pass band is the sum ofthe rejections at the given frequency.
- three cascaded filters, each having an insertion loss of .01 dB at a center frequency, would have a total insertion loss of .03 dB. If the rejection in the stop band, a given frequency away from the center frequency of the filter, were 20 dB, then a total rejection for 3 cascaded filters would be 60 dB, a great improvement in filter selectivity.
- One such rule is that designing for receiver selectivity is more important than designing for receiver sensitivity.
- the more desirable choice is to provide a design that will separate adjacent channels that interfere with each other rather than to design a receiver capable of picking up the weakest channels.
- Another rule of thumb in choosing intermediate frequencies is to choose the first intermediate frequency at twice the highest input frequency anticipated. This is to reduce the possibility of spurious second order intermodulation distortion.
- this rule can even be more restrictive, requiring an IF at greater than three times the highest input frequency.
- IF conversions A frequency range ofthe local oscillator needs to be determined to establish the locations of spurious responses of various orders. Two choices are possible for each of two possible LO frequency and the selection is not subject to an easy generalization. The two available frequencies are the absolute value ofthe quantity
- Receiver planning is a process that is centered upon frequency planning and receiver level diagrams. After initial frequency selections for a frequency plan are made, a receiver level plan is used to calculate noise figures, intercept points (IP) and levels of spurious responses. Each is evaluated in light of design requirements. After each set of selections performance is evaluated and a next set of parameter selections is made until an appropriate compromise in receiver performance is achieved. Once frequency planning and a level diagram yield a satisfactory design solution these tools are used to guide a detailed receiver design. Once parameters of a section of a receiver are defined, an engineer can use various circuit implementations to achieve a stated design goal. For example a frequency plan and level diagram may require a band pass filter with certain characteristics such as bandwidth, center frequency and insertion loss. The engineer would then either pick a single filter that meets all of these requirements or cascade one or more filters such that a composite response will yield the required design value.
- IP intercept points
- a design process and a result achieved is very dependent upon technology available, materials and methodologies known at the time.
- New improvements in design techniques, computer simulation, processing and a push for increased miniaturization continually fuel achievement of new and innovative receiver designs to solve technological problems.
- the next step in receiver design is to design circuitry that will generate one or more local oscillator signals. These signals could be provided by a source that is external to a chip. However, this would not be practical in seeking to miniaturize an overall receiver design. A better approach is to generate the local oscillator frequencies near the receiver. In reducing an entire receiver onto a single chip, problems in maintaining signal purity, and stability are encountered. An innovation that has allowed increased miniaturization in receiver design is the development of frequency synthesis. Local oscillator signals are required in receivers utilizing frequency conversion. These signals must be tunable and stable. A stable frequency is easily produced by a quartz crystal at a single frequency.
- a tunable frequency can be produced by an LC type oscillator.
- this LC oscillator does not have sufficient stability. Additionally using a large number of crystals to generate a range of local oscillator signals, or inductors required in an LC oscillator do not allow an easily miniaturized design. Frequency synthesis is space efficient.
- Variable frequency local oscillator signals used in a receiver must be generated by appropriate circuits. These frequency synthesis techniques derive variable LO signals from a common stable reference oscillator. A crystal oscillator has a stable frequency suitable for use in a synthesizer.
- Oscillators may provide a fixed or a variable output frequency. This fixed or variable frequency may be used for frequency conversion in a receiver as a local oscillator that is used to mix a received radio frequency (RF) input down to an intermediate frequency or a base band signal that is more easily processed in the following circuitry.
- RF radio frequency
- Another way that a received signal can be converted down to a base band or intermediate frequency signal is by using frequency synthesizer outputs as local oscillator signals to mix the signal down. Synthesizers provide accurate, stable and digitally programmable frequency outputs, without the use of multiple oscillators to tune across a band. Accuracy is maintained by using feed back.
- Direct synthesizers use frequency multipliers, dividers and mixers. Indirect synthesizers use phase-locked loops. Direct digital synthesizers use digital logic combined with a digital to analog converter to provide an analog output. Some designs combine the three techniques.
- a direct synthesizer will use a frequency reference such as a crystal oscillator as disclosed in FIG. 5 to generate a reference frequency. To achieve a desired output frequency, the reference frequency is multiplied through a series of multipliers. Dividers may be used similarly to reduce the frequency output to the desired lesser value. Additionally, two signals generated from the chain of multipliers and dividers can be fed into a mixer to generate a third frequency. The mix and divide direct synthesis approach permits the use of many identical modules that produce fine resolution with low spurious output.
- Indirect synthesis can take several forms. It can use divide by N to produce one or more ofthe digits, and mix and divide with loops imbedded among circuits. In each form of frequency synthesizer, the loops contained in it are governed by a derivative of a reference frequency. Indirect synthesis can be used to generate a frequency of — ⁇ f m . Circuits of this type are often used as local oscillators for digitally tuned radio and television receivers.
- Indirect synthesizers make use of a number of phase locked loops (PLLs) in order to create a variety of frequency outputs.
- PLLs phase locked loops
- Each loop present in the system makes use of a common frequency reference provided by a single oscillator.
- Frequency synthesizers provide the advantage of being digitally programmable to a desired frequency as well as providing an extremely stable frequency.
- Frequency stability in a synthesizer is achieved with phase locked loops.
- a phase locked loop is programmed to generate a desired frequency. Once it approximates the frequency, the frequency is divided down to the value of a reference frequency, provided by an external oscillator, and compared to that reference frequency. When the difference reaches zero the phase locked loop stops tuning and locks to the frequency that it has just produced.
- the frequency reference used to tune the phase locked loop is typically provided by a single frequency oscillator circuit.
- Frequency synthesizers in a radio frequency receiver often incorporate two phase locked loops.
- One PLL is used to provide coarse tuning within the frequency band of interest while the second PLL provides fine tuning steps.
- a coarse tuning must be such that a desired channel will initially fall within the selectivity of the receiver to produce a signal output. It would be an advantage in receiver design if tuning speed could be increased so that initially several channels would fall within the selectivity ofthe receiver. Tuning in this manner would allow an output to be created with an extremely coarse tuning range that could be dynamically adjusted.
- this type of tuning is not seen in the state ofthe art.
- PLLs use a common reference frequency oscillator. Local oscillator signals produced by a frequency synthesizer's phase locked loops inject noise produced in the reference frequency oscillator and the PLLs into a the signal path by way of a PLL output.
- a range of output frequencies from a synthesizer can span many decades, depending on the design.
- a “resolution” ofthe synthesizer is the smallest step in frequency that can be made. Resolution is usually a power of 10.
- a “lock up time” ofthe synthesizer is the time it takes a new frequency to be produced once a command has been made to change frequencies.
- the present embodiments of the invention allow all channel selectivity and image rejection to be implemented on an integrated circuit. Integration is a achievable by utilizing differential signal transmission, a low phase noise oscillator, integrated low Q filters, filter tuning, frequency planning, local oscillator generation and PLL tuning to achieve a previously unrealized level of receiver integration.
- the embodiments ofthe invention advantageously allow a LC filters to be integrated on a receiver chip, resulting in an integrated circuit that contains substantially the entire receiver.
- an architecture is achieved that allows LC filters to be integrated on a receiver chip so that acceptable performance is produced when converting a received signal to one having a lower frequency that is easily processed.
- the embodiments utilize particular aspects of an arbitrarily defined input spectrum to first shift the received frequencies to a higher frequency in order that interference may be more easily eliminated by filtering and then shifting the spectrum to a nominal IF for processing.
- This first shifting process advantageously shifts interfering image signals away from a center frequency of a first LC filter bank so that the LC filter bank is more effective in reducing the interfering signal strength.
- multiple LC filters that are tuned to the same frequency are cascaded, further reducing the interfering signal strength.
- the exemplary embodiments ofthe invention utilize a complex mixing stage following an LC filter bank to reduce the image frequency interference by an additional amount that might be necessary to meet a particular image rejection target (i.e., an about 60 dB to 65 dB rej ection target) .
- a complex mixer creates a signal as a result of its normal operation that cancels an image frequency interference by the remaining amount needed to achieve satisfactory performance with LC filters.
- the ultimate goal of a receiver is to reduce the frequency of an incoming signal to a frequency that is lower than received, so that processing of the desired signal can be easily achieved.
- the receiver architecture utilizes two frequency down conversions to achieve this goal.
- Each frequency conversion is susceptible to interference that requires filtering.
- Radio receivers require one or more local oscillator (LO) signals in order to accomplish frequency conversion to an intermediate (IF) frequency. In a typical receiver these local oscillator signals must be stable and free from noise. When a receiver is fabricated as an integrated circuit, the chances of injecting noise via the LO signals increases.
- Local oscillator signals for a receiver are typically generated in close proximity to the frequency conversion circuitry. The close proximity of this frequency generation circuitry to the signal path creates an increased likelihood of noise being radiated or conducted to cause interference with the received signal.
- the exemplary embodiments ofthe invention may utilize circuitry to generate the local oscillator signals that possess superior noise performance.
- the local oscillator signals may also be advantageously transmitted differentially to the mixers present on the integrated circuit. It should be noted that in alternate embodiments ofthe invention that a single ended output can be produced from the differential signal by various techniques known in the art. This technique is used advantageously whenever external connections to the receiver are required that are single ended.
- An exemplary embodiment ofthe present invention utilizes a differential oscillator having low phase noise or jitter and high isolation, as a frequency reference that substantially increases the performance of a tuner architecture integrated onto a single silicon substrate.
- a crystal oscillator circuit is provided and constructed so as to define a periodic, sinusoidal, balanced differential signal across two symmetrical terminals of a crystal resonator which are coupled in a parallel configuration across symmetrical, differential terminals of a differential oscillator circuit.
- the differential oscillator circuit is configured such that it is constructed of simple active and passive components which are easily implemented in modern integrated circuit technology, thus allowing the differential oscillator circuit to be accommodated on a monolithic integrated circuit chip for which the crystal oscillator (as a whole) is providing a suitable, stable periodic timing reference signal.
- resonating crystal crystal resonator or quartz crystal resonator
- quartz crystal resonator only the resonating crystal (crystal resonator or quartz crystal resonator) is provided as an off-chip component. This particular configuration allows for considerable savings in component parts costs by partitioning more and more functionality into the integrated circuit chip.
- interconnecting leads of finite length.
- these interconnecting leads are typically implemented as circuit pads and conductive wires formed on a PC board substrate to which package leads are bonded (soldered) in order to effect electrical connection between the crystal resonator and an associated oscillator circuit.
- External electrical connections of this type are well known as being susceptible to noise and other forms of interference that might be radiated onto the interconnecting leads and, thence, into the oscillator circuit, degrading its overall noise performance.
- a sinusoidal signal source having a differential output configuration, defines a pair of periodic sinusoidal signals, with the signal at one output terminal defined as being 180° out of phase with a similar periodic, sinusoidal signal appearing at the other output terminal.
- Classical differential signals are termed "balanced" in that both signals exhibit equal peek-to-peek amplitudes although they exhibit a 180° phase relationship.
- differential signals have a particular advantage in that common-mode interference, that is injected on either terminal, is canceled when the signal is converted to single- ended.
- Such common mode interference is typically of equal amplitude on each pin and is caused by radiation into the circuit from external sources or is often generated in the circuit itself.
- signal-P oscillates about a zero reference, but is shifted by a common-mode interference component, denoted I CM .
- signal-n also oscillates about a zero reference, exhibiting a 180° phase relationship with signal-p, and is also offset by a common mode interference component denoted
- a superposition ofthe positive and negative periodic signals is illustrated in the timing diagram denoted "composite", which clearly illustrates that the peek-to-peek difference between the positive and negative signals remains the same, even in the presence of a common mode interference component I CM .
- FIG. 7 there is depicted a semi-schematic block diagram of a periodic signal generation circuit including a differential crystal oscillator driving a differential linear buffer amplifier.
- the present invention contemplates differential signal transmission throughout its architecture to maintain the purity ofthe derived periodic signal and to minimize any common mode interference components injected into the system.
- the present invention incorporates differential signal transmission in the construction of a differential crystal oscillator circuit, including a crystal resonator and its associated oscillator driver circuit. Differential signal transmission is maintained through at least a first linear buffer stage which functions to isolate the differential oscillator circuit switch transients and other forms of noise that might be generated by follow-on digital integrated circuit components.
- a differential crystal oscillator circuit is configured to function as a source of stable, synchronous and periodic signals.
- a differential crystal oscillator 710 suitably incorporates a resonating crystal 712 and a pair of symmetrical load capacitors 714 and 716, each load capacitor respectively coupled between ground potential and one ofthe two symmetrical output terminals ofthe resonating crystal 712.
- Resonating crystal 712 is coupled between differential terminals of a differential oscillator driver circuit 718, in turn connected to differential inputs of a differential linear buffer integrated circuit 720.
- the symmetrical terminals of the resonating crystal 712 are coupled across differential terminals ofthe resonator and linear buffer, with a first terminal ofthe crystal being shunted to ground by the first shunt capacitor 14.
- the second terminal ofthe crystal is shunted to ground by the second shunt capacitor 716.
- the oscillator driver circuit portion ofthe differential crystal oscillator 710 functions, in cooperation with the crystal resonator 712, to define a pure sinusoidal and differential signal across the crystal's symmetrical terminals. As will be developed in greater detail below, this pure sinusoidal and differential signal is then used by the linear buffer 720 to develop an amplified representation of periodic signals synchronized to the crystal resonant frequency. These amplified signals are also contemplated as differential inform and are eminently suitable for driving digital wave shaping circuitry to define various digital pulse trains us ⁇ able by various forms of digital timing circuitry, such as phase-lock-loops (PLLs), frequency tunable digital filters, direct digital frequency synthesizers (DDFS), and the like.
- PLLs phase-lock-loops
- DDFS direct digital frequency synthesizers
- the system depicted in FIG. 7 might be aptly described as a periodic function generator circuit, with the crystal oscillator portion 710 providing the periodicity, and with the buffer portion 720 providing the
- FIG. 8 depicts the conventional representation of a resonating crystal 712 having mirror- image and symmetrical terminals 822 and 824, upon which differential periodic signals may be developed at the crystal's resonant frequency.
- Resonating crystals also termed crystal resonators
- Resonating crystals so formed are commonly termed "quartz crystal resonators".
- a typical representational model ofthe equivalent circuit of a quartz crystal resonator 712 is illustrated in simplified, semi-schematic form in FIG. 9.
- a quartz crystal resonator can be modeled as a two terminal resonator, with an LCR circuit, incorporating a capacitor C m in series with an inductor L m and a resistor R,,,,, coupled in parallel fashion with a capacitor C 0 across the two terminals.
- LCR circuit incorporating a capacitor C m in series with an inductor L m and a resistor R,,,,, coupled in parallel fashion with a capacitor C 0 across the two terminals.
- the particular component values of the capacitor, inductor and resistor, forming the LCR filter portion of the circuit define the resonant characteristics ofthe crystal. These design values may be easily adjusted by one having skill in the art in order to implement a resonating crystal operating at any reasonably desired frequency.
- a particular exemplary embodiment of a crystal resonator might be desired to have a resonant frequency in the range of about 10 megahertz (MHz).
- the equivalent circuit of such a crystal might have a typical value of about 20 femto Farads (fF) for the capacitor C m .
- the inductor L m might exhibit a typical value of about 13 milli Henreys (mH), while the resistor might have a typical value of about 50 ohms.
- oscillation will be achieved for values ofthe capacitor C 0 that are less than a design worst case value.
- worst case values of 7 pico Farads (pF) might be chosen in order to ensure a design that oscillates at the desired resonant frequency over a wide range of crystal equivalent circuit values.
- the typical range of capacitance values for C 0 might be from about 3 to about 4 pF.
- FIGS. 10 and 11 are graphical representations depicting response plots of impedance and phase with respect to frequency, respectively, of a crystal resonator circuit constructed in accordance with the equivalent circuit model of FIG. 9 and using the values given above for the component C m , L m , R,,,, and C 0 parts.
- FIG. 10 is a plot ofthe real portion of impedance, in ohms, as a function ofthe resonator's frequency and mega Hertz.
- FIG. 11 is a representational plot of the imaginary impedance component (expressed as phase), again expressed as a function of frequency in mega Hertz.
- an exemplary crystal resonator constructed in accordance with the above values exhibits a resonant frequency in the range of about 10 MHz. Further, simulation results on such a crystal resonator exhibit a steep rise in the real impedance versus frequency plot of FIG. 10 in the resonance region about 10 MHz. A steep rise in real impedance in the resonance region is indicative of a high quality factor, Q, typically exhibited by quartz crystal resonators.
- An example of a quartz crystal resonator having the aforementioned characteristics and exhibiting a resonance fundamental at about 10 MHz is a Fox HC49U, quartz crystal resonator, manufactured and sold by Fox Electronics of Ft. Myers, Florida.
- a quartz crystal resonator including its resonant frequency
- Any type of crystal resonator may be used as the resonator component 712 of FIG. 7, so long as it is constructed with generally symmetrical terminals which can be driven, in a manner to be described in greater detail below, by an oscillator driver circuit 718 of FIG. 7 so as to develop a differential, sinusoidal signal with respect to the two terminals.
- the resonator need not oscillate at a frequency of 10 MHz.
- the choice of resonant frequency is solely a function of a circuit designer's preference and necessarily depends on the frequency plan of an integrated circuit in which the system of the invention is used to provide periodic timing signals.
- FIG. 12 there is depicted a simplified schematic diagram of a differential oscillator driver circuit, indicated generally at 718, suitable for differential coupling to a crystal resonator in order to develop balanced, differential sinusoidal signals for use by downstream components.
- the differential oscillator driver circuit 718 is constructed using common integrated circuit components and is symmetrical about a central axis.
- the oscillator driver 718 is constructed with a pair of P-channel transistors 1226 and 1228 having their source terminals coupled in common and to a current source 1230 connected, in turn, between the common source terminals and a positive supply potential V DD .
- the gate terminals of each ofthe P-channel transistors 1226 and 1228 are coupled to the drain nodes ofthe opposite transistor, i.e., the gate terminal of P-channel transistor 1228 is coupled to the drain node of P- channel transistor 1226, and vice versa.
- Output terminals are defined at each ofthe transistor's drain nodes, with the drain node of P-channel transistor 1226 defining the "negative" terminal (Von) and the drain terminal of P- channel transistor 1228 defining the "positive” output (Vop).
- the circuit is able to operate differentially by cross coupling the transistors 1226 and 1228 in order to provide feedback. Because transistors exhibit some measure of gain at all frequencies, particularly DC, conventional cross coupled transistors are often implemented as latches in digital circuit applications where large DC components are present. In the differential oscillator driver circuit 718 ofthe invention, latching is prevented by removing the DC gain component, while retaining the system's high frequency gain, particularly gain in the desirable 10 MHz region.
- a high pass filter is interposed between the gate and output terminals of each symmetrical half of the circuit.
- a high pass filter 1232 is coupled between the "negative" output terminal and the gate terminal of P-channel transistor 1228.
- the high pass filter 1234 is coupled between the "positive” output terminal and the gate terminal of P-channel transistor 1226.
- each of the high pass filters 1232 and 1234 are coupled between a virtual ground, identified as Vmid and indicated in phantom in the exemplary embodiment of FIG. 12, and the corresponding gate terminal ofthe respective one ofthe differential pair P-channel transistors 1226 and 1228.
- Each ofthe high pass filters 1232 and 1234 are implemented as RC filters, each including a resistor and capacitor in a series-parallel configuration. Each capacitor is series-connected between an output terminal and the gate terminal of a corresponding differential pair transistor, while each resistor is coupled between a gate terminal and the virtual ground.
- the first high pass filter 1232 includes a capacitor 1236 coupled between the "negative" terminal and the gate terminal of P-channel transistor 1228.
- a resistor 1238 is coupled between the gate of P-channel transistor 1228 and virtual ground.
- the second high pass filter 1234 includes a capacitor 1240 coupled between the "positive" terminal and the gate terminal of P-channel transistor 1226.
- a resistor 1242 is coupled between the gate of P-channel transistor 1226 and the virtual ground.
- high pass filter 1232 filters the input from Von prior to applying that signal to the gate of its respective differential pair transistor 1228.
- high pass filter 1234 filters the input from Vop prior to applying that signal to the gate of its respective differential pair transistor 1226.
- Each ofthe high pass filters are symmetrically designed and have component values chosen to give cutoff frequencies in the range of about 5 MHz.
- filter capacitors 1236 and 1240 might have values of about 1.5 pF
- filter resistors 1238 and 1242 might have values in the range of about 718 Kohms. Which would give a filter yielding the desired 5 MHz cutoff. It will be thus understood that the differential oscillator driver circuit 18 will have negligible gain at DC, while exhibiting its design gain values in the desired region of about 10 MHz.
- the component values for high pass filters 1232 and 1234 were chosen to give a particular cut off frequency of about 5 MHz, allowing the oscillator driver circuit to exhibit full design gain at a resonate frequency of about 10 MHz. If the resonant frequency ofthe crystal oscillator circuit were required to have a different value, the components ofthe high pass filters 1232 and 1234 would necessarily take on different values to accommodate the different operational characteristics ofthe circuit. Accordingly, the actual component values, as well as the cutoff frequency value of the exemplary embodiment, should not be taken as limiting the differential oscillator driver circuit according to the invention in any way.
- the values and characteristics ofthe differential oscillator driver circuit 18 of FIG. 12 are exemplary and have been chosen to illustrate only one particular application.
- the differential oscillator driver circuit 718 of FIG. 12 is provided with a common mode control circuit which functions to maintain any common mode output signal at reasonable levels.
- a differential pair of N-channel transistors 1244 and 1246 is provided with each having its drain terminal coupled to a respective one of the Von and Vop output terminals.
- the differential N-channel transistors 1244 and 1246 further have their source terminals tied together in common and to a negative supply potential V ss .
- Their gate terminals are tied together in common and are further coupled, in feedback fashion, to each transistor's drain node through a respective bias resistor 1248 and 1250.
- the bias resistors 1248 and 1250 each have a value, in the exemplary embodiment, of about 100 Kohms, with the gate terminals o the N-channel differential pair 1244 and 1246 coupled to a center tab between the resistors.
- This center tab defines the virtual ground Vmid which corresponds to a signal midpoint about which the sinusoidal signals Von and Vop oscillate. Any common mode component present at the outputs will cause a voltage excursion to appear at the gates ofthe N-channel differential pair 1244 and 1246.
- virtual ground Vmid can be thought of as an operational threshold for the current mode control differential pair 1244 and 1246. Common mode excursions above or below
- Vmid will cause a common mode control differential pair to adjust the circuit's operational characteristics so as to maintain Vmid at a virtual ground level, thus minimizing any common mode component.
- noise in such a linear differential oscillator driver circuit is filtered mainly by the crystal resonator, but also by the operational characteristics of the driver circuit.
- noise at 10 MHz is amplified by the positive feedback characteristics ofthe circuit and will continue to grow unless it is limited.
- signals in the 10 MHz region will continue to grow in amplitude until limited by a non-linear self-limiting gain compression mechanism.
- the effective transconductance g m ofthe P-channel differential pair transistors 1226 and 1228 fall off, thus limiting the gain of the differential amplifier.
- Amplifier gain falloff with increasing gate voltage excursions is a well understood principle, and need not be described in any further detail herein.
- the differential oscillator driver circuit 718 in combination with a crystal resonator (712 of FIG. 7) function to define periodic, sinusoidal and differential signals across the terminals ofthe crystal resonator.
- the signals are differential in that they maintain a 180 ° phase relationship.
- the exemplary differential oscillator driver circuit is designed to be highly linear with a relatively low gain, thus reducing phase noise (phase jitter) to a significantly better degree than has been achieved in the prior art.
- Signal quality and symmetry is further enhanced by the symmetrical nature ofthe two halves ofthe oscillator driver circuit.
- the oscillator driver circuit is symmetrical about a central axis and, when implemented in integrated circuit technology, that symmetry is maintained during design and layout.
- conductive signal paths and the spatial orientation of the driver's active and passive components are identical with respect to the "negative" and "positive” outputs, thereby enhancing signal symmetry and further minimizing phase jitter.
- differential crystal oscillator circuit is able to provide a periodic clock signal (approximately 10 MHz) that exhibits stable and robust timing characteristics with very low jitter.
- a particular exemplary embodiment of a periodic signal generator circuit incorporates a differential crystal oscillator circuit according to the present invention, including a crystal resonator 12 and differential oscillator driver circuit 718.
- a resonant crystal circuit 12 includes first and second timing capacitors (714 and 716 of FIG. 7) which are not shown merely for convenience in ease of explanation.
- the resonant crystal circuit 712 is coupled, in parallel fashion, across the output terminals of the oscillator driver circuit 718 which incorporates the active device circuitry for pumping energy into the circuit in order to sustain oscillation.
- This parallel combination is coupled, differentially, into a linear buffer amplifier 720, which functions to provide a linear gain factor K to the differential signal provided by the crystal oscillator circuit.
- Linear buffer amplifier 720 provides signal isolation, through high input impedance, as well as amplification of the oscillating (10 MHz) signal produced by the crystal resonator/oscillator driver combination.
- Linear buffer amplifier 720 is configured to output differential mode signals characterized by linear amplification ofthe input differential signals, that may then be used to drive one or more additional wave shaping-type devices, such as nonlinear buffer amplifiers 1352, 1354 and 1356.
- nonlinear buffers 1352, 1354 and 1356 function in order to provide signal translation (wave shaping) from the differential sign wave periodic signal present at the output of the linear buffer 720 to a digital pulse train at characteristic logic levels suitable for driving fall-on digital circuit blocks 1358, 1360 and 1362.
- nonlinear buffers 1352, 1354 and 1356 also provide a measure of signal conditioning, transforming the purely sinusoidal signal at their inputs to a very low jittergetter square wave output.
- the system ofthe present invention utilizes two stages of buffering.
- phase noise phase jitter
- phase noise is minimized in the nonlinear buffer amplifiers 1352, 1354 and 1356 by amplifying the differential signal provided by the crystal oscillator circuit through the linear amplifier 720 in order to increase the amplitude, and thus the slew rate, of the signal prior to its conversion to a square wave. Phase noise resulting from zero crossings of the nonlinear buffer amplifiers is thereby minimized.
- nonlinear buffers which might be cascaded in order to produce a suitable clock signal is an additional important feature in the design of a low phase noise oscillator circuit.
- multiple cascaded invertors are used to provide high isolation ofthe final, squared output signal.
- each time the signal passes through a nonlinear inverter zero crossing occurs which offers an additional opportunity for phase noise to be added to the circuit.
- the present invention contemplates a single stage of nonlinear buffering which presents a high input impedance to the linear buffer 720 which proceeds it.
- the linear buffer 720 is further provided with a high input impedance to further isolate the crystal resonator and its associated differential oscillator driver circuitry from noise loading.
- FIG. 14 An exemplary embodiment of a linear buffer suitable for use in connection with the periodic signal generation circuit of FIG. 13 is illustrated in simplified, semi-schematic form in FIG. 14.
- the exemplary embodiment of FIG. 14 illustrates the conceptual implementation of a differential-in differential-out amplifier.
- the differential implementation has several advantages when considered in practical applications. In particular, maximum signal swing is improved by a factor of 2 because ofthe differential configuration. Additionally, because the signal path is balanced, signals injected due to power supply variation and switch transient noise are greatly reduced.
- the exemplary implementation of a differential-in, differential-out amplifier (indicated generally at 720) of FIG. 14 uses a folded cascade configuration to produce a differential output signal, denoted V out . Since the common-mode output signal of amplifiers having a differential output can often be indeterminate, and thus cause the amplifier to drift from the region where high gain is achieved, it is desirable to provide some form of common-mode feedback in order to stabilize the common-mode output signal.
- the common-mode output signal is sampled, at each ofthe terminals comprising the output V out and fed back to the current-sink loads ofthe folded cascade.
- Differential input signals V m are provided to the control terminals of a differential input pair 1464 and 1466, themselves coupled between respective current sources 1468 and 1470 and to a common current-sink load 1472 to V ss .
- Two additional transistors (P-channel transistors in the exemplary embodiment of FIG. 14) define the cascade elements for current-sources 1468 and 1470 and provide bias current to the amplifier circuit.
- High impedance current-sink loads at the output ofthe amplifier 1476 and 1478 might be implemented by cascoded current sink transistors (N-channel transistors for example) resulting in an output impedance in the region of about 1 Mohm.
- the common mode feedback circuit 1480 might be implemented as an N-channel differential pair, biased in their active regions and which sample the common-mode output signal and feedback a correcting, common-mode signal into the source terminals ofthe cascoded transistors forming the current-sinks 1476 and 1478.
- the cascade devices amplify this compensating signal in order to restore the common-mode output voltage to its original level.
- the exemplary linear amplifier of FIG. 14 might be implemented as any one of a number of appropriate alternative amplifiers.
- it need not be implemented as a fully differential folded cascade amplifier, but might rather be implemented as a differential-in, differential-out op amp using two differential-in single-ended out op amps.
- the input differential pair might be either an N-channel or a P-channel pair, MOS devices might be used differentially as active resistors or alternatively, passive resistor components might be provided, and the like. All that is required is that the linear amplifier 720 amplifies a differential input signal to produce a differential, sinusoidal signal at its output. Thus, the only frequency components reflected back through the linear amplifier 720 will be sinusoidal in nature and thus, will not affect the operational parameters ofthe differential crystal oscillator frequency. Further, the linear buffer
- FIG. 15 there is depicted a simplified semi-schematic diagram of a nonlinear buffer, indicated generally at 1582, such as might be implemented as a wave shaping or squaring circuit 1352, 1354 or 1356 of FIG. 13.
- the nonlinear buffer 1582 receives a differential, sinusoidal input signal at the gate terminals of an input differential transistor pair 1584 and 1586. Drain terminals of the differential pair 1584 and 1586 are connected together in common and to a current sink supply 1588 which is coupled to a negative potential.
- Each of the differential pairs' respective source terminals are coupled to a bias network, including a pair of differential bias transistors 1590 and 1592 having their gate terminals tied together in common and coupled to a parallel connected bias network.
- the bias network is suitably constructed of a resistor 1594 and a current sink 1596 connected in series between a positive voltage potential such as Vdd and Vss.
- a bias node between the resistor 1594 and current sink 1596 is coupled to the common gate terminals of the bias transistor network 1590 and 1592 and defines a bias voltage for the bias network which will be understood to be the positive supply value minus the IR drop across bias resistor 1594.
- the current promoting the IR drop across the bias resistor 1594 is, necessarily, the current I developed by the current sink 1596.
- a differential, square wave-type output (Vout) is developed at two output nodes disposed between the respective source terminals of the bias network transistors 1590 and 1592 and a respective pair of pull-up resistors 1598 and 1599 coupled, in turn, to the positive supply potential.
- the bias network including transistors 1590 and 1592, function to control the non-linear amplifier's common mode response in a manner similar to the linear amplifier's common mode network (transistors 1244 and 1246 and resistors 1248 and 1250 of FIG. 12).
- FIG. 16 is a semi-schematic illustration of an alternative embodiment ofthe differential oscillator driver circuit (718 of FIG. 12). From the exemplary embodiment of FIG. 16, it can be understood that the oscillator driver circuit is constructed in a manner substantially similar to the exemplary embodiment of FIG. 12, except that a crystal resonator is coupled across the circuit halves above the differential transistor pair, as opposed to being coupled across a circuit from the
- FIG. 16 operates in substantially the same manner as the embodiment of FIG. 12 and produces the same benefits as the earlier disclosed oscillator. It is offered here as an alternative embodiment only for purposes of completeness and to illustrate that the specific arrangement ofthe embodiment of FIG. 12 need not be followed with slavish precision.
- FIG. 17 illustrates one such application as a reference signal generator in a phase-lock-loop.
- the phase-lock-loop uses a low phase noise periodic signal generation circuit in accordance with the invention in order to generate a reference signal for use by a phase detector.
- Providing a clean reference signal to the phase detector is fundamental to providing a clean RF output from the PLL. Since noise and nonlinearities induced by signal generation circuit are carried through the PLL circuit, thus degrading the RF output, reducing phase noise and providing noise rejection early on in the signal processing chain is advantageous to maintaining a clean RF output.
- a differential crystal oscillator (710 of FIG.7) advantageously provides this claim signal by maintaining a differential signal across the terminals of the resonating crystal, an improvement not currently available in state-of-the-art crystal oscillators.
- PLLs have become available in integrated circuit form, they have been found to be useful in many applications. Certain examples of advantageous application of phase-lock-loop technology include tracking filters, FSK decoders, FM stereo decoders, FM demodulators, frequency synthesizers and frequency multipliers and dividers. PLLs are used extensively for the generation of local oscillator frequencies in TV and radio tuners. The attractiveness ofthe PLL lies in the fact that it may be used to generate signals which are phase-locked to a crystal reference and which exhibit the same stability as the crystal reference. In addition, a PLL is able to act as a narrow band filter, i.e., tracking a signal whose frequency may be varying.
- a PLL uses a frequency reference source in the control loop in order to control the frequency and phase of a voltage control oscillator (VCO) in the loop.
- VCO voltage control oscillator
- the VCO frequency may be the same as the reference frequency or may be a multiple ofthe reference frequency.
- a VCO is able to generate a multiple ofthe input frequency with a precise phase relationship between a reference frequency and an RF output.
- the frequency reference provided to the PLL must, necessarily, also be precise and stable.
- FIG. 18 is a simplified block diagram of an illustrative frequency synthesizer that might incorporate the differential periodic signal generation circuit of the invention.
- the frequency synthesizer is a signal generator that can be switched to output any one of a discrete set of frequencies and whose frequency stability is derived from a crystal oscillator circuit.
- Frequency synthesizers might be chosen over other forms of frequency sources when the design goal is to produce a pure frequency that is relatively free of spurious outputs.
- Particular design goals in frequency synthesizer design might include suppression of unwanted frequencies and the suppression of noise in a region close to the resonant frequency ofthe crystal that is a typical source of unwanted phase modulation. Synonymous terms for this type of noise are broadband phase noise, spectral density distribution of phase noise, residual FM, and short term fractional frequency deviation.
- crystal oscillators are commonly used due to their stability and low noise output.
- the use of a periodic signal generation circuit incorporating a differential crystal oscillator according to an embodiment ofthe present invention advantageously improves these performance parameters. Improved phase noise is achieved through the use of linear buffering followed by nonlinear amplification, while noise rejection is provided by the differential design utilized throughout the circuitry architecture.
- a periodic signal generation circuit has many uses in modem, state-of-the-art timing circuits and systems.
- the periodic signal generation circuit is constructed of simple active and passive components which are easily implemented in modem integrated circuit technology.
- the crystal oscillator portion is providing a suitable, stable periodic timing reference signal.
- Only the resonating crystal portion (crystal resonator or quartz crystal resonator) is provided as an off-chip component. This particular configuration allows for considerable savings in component parts costs by partitioning more and more functionality into the integrated circuit chip itself.
- the oscillator's output is a differential signal that exhibits high common mode noise rejection.
- Use of a low noise reference oscillator with differential signal transmission allows the synthesis of stable low noise local oscillator signals.
- a unique generation ofthe local oscillator signals allows complete integration of a receiver circuit on a CMOS integrated circuit by reducing noise in the signal path.
- Frequency synthesizers and a radio frequency receiver often incorporate phase locked loops that make use of a crystal oscillator as a frequency reference.
- a PLL is used to provide coarse tuning within the frequency band of interest while a second PLL provides fine tuning steps.
- the present embodiments ofthe invention utilize a method of coarse/fine PLL adjustment to improve the performance ofthe integrated tuner.
- FIG. 19 is a diagram illustrating receiver tuning.
- the combination of a wide band PLL 1908 and a narrow band PLL 1910 tuning provides a capability to fine tune a receiver's LOS 1902, 1904 over a large bandwidth in small frequency steps.
- a small frequency step is 100 kHz, and 25 kHz for NTSC modulation.
- Fine tuning is available over an entire exemplary 50 MHz to 860 MHz impact frequency band width 1906.
- the first PLL 1908 tunes a first LO 1902 in large 10 MHz frequency steps and the second PLL 1910 tunes a second LO 1904 in much smaller steps.
- the first intermediate frequency (IF) filter 1912 has a sufficiently wide band width to allow up to 10 MHz frequency error in tuning the first intermediate frequency, with the narrow band PLL providing final fine frequency tuning to achieve the desired final IF frequency 1914.
- FIG. 20 is a block diagram of an exemplary tuner 2002 designed to receive a 50 to 860 MHz bandwidth signal 2004 containing a multiplicity of channels.
- this exemplary band of frequencies there are 136 channels with a spacing between channel center frequencies of six megahertz 2008.
- the tuner selects one of these 136 channels 2006 that are at a frequency between 50 and 860 MHz by tuning to the center frequency ofthe selected channel 2010. Once a channel is selected the receiver rejects the other channels and distortion presented to it.
- the selected channel is down converted to produce a channel centered about a 44 MHz intermediate frequency (IF) 2012.
- IF intermediate frequency
- the value ofthe intermediate frequency ultimately produced by the tuner may be selected utilizing the method ofthe invention to provide any suitable final IF frequency, such as 36 MHz
- a maximum frequency error in the local oscillator (LO) frequency used to tune the channel to a given IF of plus or minus 50 kHz is allowable.
- LO local oscillator
- Using one frequency conversion to directly tune any one ofthe 136 channels to 44 MHz would require a tuning range in the local oscillator of 810 MHz. This would require a local oscillator that tunes from 94 to 854 MHz, if utilizing high side conversion. Achieving this with a single LO is impractical.
- Tuning range in local oscillators is provided by varactor diodes that typically require 33 volts to tune them across their tuning range.
- a frequency tuning step of 100 kHz is required to ensure that the center frequency of a tuned channel is tuned within plus or minus 50 kHz.
- a large range of frequencies would have to be tuned in small increments over a 33 volt tuning signal range.
- an exemplary 50 to 860 MHz signal 1906 is presented to a first mixer 1916 that is tuned with a wide band PLL 1908 that tunes a first LO 1902 in frequency steps of 10 MHz.
- This local oscillator 1902 is set to a frequency that will nominally center a channels that has been selected at a first
- the first IF 1918 is then mixed 1920 to the second IF of 275 MHz 1922. This is done by the narrow band PLL 1910 that tunes a second LO 1904 in frequency steps of 100 kHz.
- the second IF 1922 is next mixed 1924 down to a third IF 1926 of 44 MHz by a third local oscillator signal 1928.
- This third local oscillator signal 1930 is derived from the second local oscillator or narrow band PLL signal by dividing its frequency by a factor of four.
- FIG.21 is an exemplary table of frequencies utilizing coarse and fine PLL tuning to derive a 44 MHz IF ("IF-3").
- a process is utilized to determine the wide and narrow band PLL frequencies.
- the relationship between the wideband PLL and narrowband PLL frequencies to yield the desired intermediate frequency is found from:
- Fsig Input signal
- Fif e.g., 44MHz or 36MHz or whatever IF is required
- FIG 21 and 22 utilized this formula to derive the values entered into them to tune the exemplary cable TV signals "Frf.
- the first column 2102 of the table lists the frequencies needed to tune a signal centered at 50 MHz (“Frf) to a 44 MHz final IF ("IF-3").
- LO-1 1,250 MHz
- LO-2 924.8 MHz
- FIG. 22 is an illustration of an alternative embodiment ofthe coarse and fine PLL tuning method to produce an exemplary final IF of 36 MHz.
- a first IF IF- 1
- second LO LO-2
- LO-2 LO-2
- IF-3 IF-3
- These predetermined tuning frequencies are stored in a memory and applied when a command is given to tune a given channel.
- an algorithm may be supplied to produce the tuning frequencies. It is understood that these frequencies are exemplary and other frequencies that utilize this method are possible.
- a coarse, and a fine PLL use a common reference frequency oscillator.
- Local oscillator signals produced by the frequency synthesizer's phase locked loops inject noise produced in the reference frequency oscillator and the PLLs into a signal path through the PLL output.
- Noise injected can be characterized as either phase noise or jitter.
- Phase noise is the frequency domain representation of noise that, in the time domain is characterized as jitter.
- Phase noise is typically specified as a power level below the carrier per Hertz at a given frequency away from the carrier.
- Phase noise can be mathematically transformed to approximate a jitter at a given frequency for a time domain signal.
- jitter refers to the uncertainty in the time length between zero crossings ofthe clock signal. It is desirable to minimize the jitter produced in an oscillator circuit and transmitted through the signal chain into the signal path to prevent noise degradation in the receiver path. Equivalently, any oscillator producing a stable output frequency will suffice to produce a reference frequency for the PLL circuitry.
- FIG.23 is a block diagram of a dummy component used to model an operative component on an integrated circuit chip.s According to one aspect ofthe invention, a dummy circuit on an integrated circuit chip is used to model an operative circuit that lies in a main, e.g.
- RF radio frequency
- Adjustments are made to the dummy circuit in a control signal path outside the main signal path. Once the dummy circuit has been adjusted, its state is transferred to the operative circuit in the main signal path.
- main signal path 2201 there is a main signal path 2201 and a control signal path 2202 on an integrated circuit chip.
- a signal source 2203 is coupled by an operative circuit 2204 to be adjusted to a load 2205.
- Main signal path 2201 carries RF signals.
- Signal source 2203 generally represents the portion ofthe integrated circuit chip upstream of operative circuit 2204 and load 2205 generally represents the portion ofthe integrated circuit chip downstream of operative circuit 2204.
- a control circuit 2206 is connected to a dummy circuit 2207 and to operative circuit 2204.
- Dummy circuit 2207 is connected to control circuit 2206 to establish a feedback loop.
- Dummy circuit 2207 replicates operative circuit 2204 in the main signal path in the sense that, having been formed in the same integrated circuit process as operative circuit 2204, its parameters, e.g., capacitance, inductance, resistance, are equal to or related to the parameters of operative circuit 2204.
- a signal is applied by control circuit 2206 to dummy circuit 2207.
- the feedback loop formed by control circuit 2206 and dummy circuit 2207 adjusts dummy circuit 2207 until it meets a prescribed criterion.
- operative circuit 2204 is indirectly adjusted to satisfy the prescribed criterion, without having to be switched out of the main signal path and without causing disruptions or perturbations in the main signal path.
- operative circuit 2204 to be adjusted is a bank of capacitors in one or more operative bandpass filters in an RF signal path
- dummy circuit 2207 is a bank of related capacitors in a dummy bandpass filter
- control circuit 2206 is a phase detector and an on-chip local oscillator to which the operative filter is to be tuned.
- the output ofthe local oscillator is coupled to the dummy filter.
- the output ofthe dummy filter and the output ofthe local oscillator are coupled to the inputs ofthe phase detector to sense the difference between the frequency of the local oscillator and the frequency to which the dummy filter is tuned.
- the output ofthe phase detector is coupled to the dummy filter to adjust its bank of capacitors so as to tune the dummy filter to the local oscillator frequency.
- the state of its capacitor bank is transferred, either on a one-to-one or scaled basis , to the operative filter. Since the capacitor bank in the dummy filter replicates that of the operative filter, the frequency to which the operative filter is tuned can be easily scaled to the frequency of the dummy filter.
- operative circuit 2204 to be adjusted is a filter having a spiral inductor that has a temperature sensitive internal resistance. Dummy circuit 2207 has an identical spiral inductor.
- Control circuit 2206 has a controllable variable resistor in series with the inductor of dummy circuit 2207.
- the controllable resistor is driven by a feedback loop to offset changes in the internal resistance of the inductor of dummy circuit 2207.
- Operative circuit 2204 has a similar controlled resistor in series with its inductor to transfer the resistance value of the controllable resistor in control circuit 2206 to the resistor of the operative circuit 2204 in open loop fashion.
- FIG. 23 a is a block diagram illustrating the use of a tuning circuit outside of a signal path to tune bandpass filters present in a receiver.
- a tuning circuit 2302 utilizes a substitute or "dummy" filter stage 2310 to derive tuning parameters for a filter bank 2304 present in a signal path 2306.
- the tuning circuit utilizes a local oscillator signal 2308 available in the receiver to tune the dummy filter 2310 to the center frequency ofthe local oscillator.
- the dummy filters 2310 tuned component values that result in a tuned response at the local oscillator frequency are scaled in frequency and applied to the bandpass filter 2312.
- the filters are tuned at startup, and the tuning circuitry is turned off during normal operation. This prevents the injection of additional noise into the signal path during operation.
- FIG.23b is a flow diagram ofthe tuning process in operation receiver is initially powered up 2312 and local oscillator signals generated by PLLs are centered at their design frequency 2314. Once the PLLs are locked their frequency is a known condition. Next substitute filter tuning is initiated 2316 and performed. When finished a signal is received back from the filter tuning network indicating that it is ready 2318. Information from the tuning network is copied to the receive path filter circuit 2320. Next the filter tuning circuit is turned off 2322 disconnecting it from the filter circuit. In the embodiments ofthe invention the narrow band PLL (2308, of FIG.23a) is used as reference frequency in the tuning circuit. However, it is understood that this tuning technique may be utilized with any readily available signal. Returning to FIG.
- a 925 MHz signal is directly available from the narrow band PLL 2308. It is used to tune the dummy filter 2310 contained in the tuning circuit 2302 associated with the 1 ,200 MHz filter 2304. After the dummy filter is tuned to 925 MHz, frequency scaling is used to obtain the proper component values for the 1 ,200 MHz filter response to be centered.
- the exemplary 925 MHz signal generated by the narrow band PLL is divided by 4 to yield a 231 MHz third LO signal utilized in additional tuning circuitry.
- a second exemplary filter tuning circuit 2302 for a 275 MHz filter contains a dummy filter 2310 that is tuned to a center frequency of 231 MHz. Once tuned, the component values used to center the 231 MHz dummy filter 2310 are scaled to yield a centered response for the 275 MHz filter 2304. At this point in time the tuning circuits 2302 are switched off. It is especially important to turn off the exemplary tuning circuits on the 275 MHz filter since the 231 MHz signal used to tune its dummy filter falls in an exemplary 50-860 MHz band.
- any available frequency may be used to tune a substitute filter so that another filter, that does not have an appropriate tuning signal present, may be tuned. This is done by scaling the component values ofthe tuned dummy filter to values appropriate for the filter not having the tuning frequency present. Tuning values obtained for a dummy filter may be applied to all filters present in a bank of filters having a common center frequency. Also tuning values obtained for a dummy filter may be applied to multiple filters present having differing center frequencies by applying differing scaling factors. Finally multiple filters at different locations in a signal path that have common center frequencies may be tuned by a common tuning circuit. Capacitors disposed on an integrated circuit vary in capacitance value by as much as +/-
- Capacitors with the same dimensions are provided in a bandpass filter and a dummy filter to provide satisfactory matching between the devices.
- Switchable caps in the embodiments ofthe invention are MOS caps that are all of the same value and from factor.
- other weighting of capacitor values could be provided to achieve an equivalent function.
- binary or 1/x weighted values of capacitors could be disposed in each filter to provide tuning.
- a bank of fixed capacitors and a bank of electronically tunable capacitors are provided.
- the adjustable capacitors in the exemplary embodiment represent 40% ofthe total capacitance provided. This is done to provide for the ⁇ 20% variance in center frequency due to manufacturing variances.
- FIG. 24 is an exemplary illustration of a tuning process utilizing switched capacitors.
- Filter responses shown at the bottom plot 2402 illustrate a tuning of a dummy filter 2310 that is contained in a tuning circuit 2302 of FIG. 23a.
- a frequency response being tuned in the upper graph 2404 shows the tuning of the exemplary 1.200 MHz bandpass filter 2304 of FIG. 23a.
- none of the switched capacitors are applied in a dummy filter circuit. This places the filter response initially 2406 above the final desired tuned response frequency 2408.
- capacitors are added until the filter response ofthe dummy filter is centered about 925 MHz.
- the tuned response ofthe 925 MHz dummy filter 2408 is not the desired center frequency ofthe bandpass filter in the signal path.
- the values used in to tune the dummy filter would not tune the 1,200 MHz filter to the correct response.
- Frequency scaling is used to tune the desired response. This can be achieved because identical capacitors disposed on a chip are very well matched in value and parasitics. In particular capacitor matching is easy to achieve by maintaining similar dimensions between groups of capacitors. In scaling a response to determine a capacitance to apply in a bandpass filter, identical inductance values have been maintained in the dummy and bandpass circuits. Thus, only a scaling of the capacitors is necessary.
- the frequency relation in the exemplary embodiment is given by the ratio:
- an offset control circuit is provided within the tuning circuit of FIG.23 to move the tuning ofthe filters up or down slightly by providing a manual means of adding or removing a capacitor. This control is shown by an
- FIG. 25 is a block diagram of an exemplary tuning circuit.
- a reset signal 2502 is utilized to eliminate all the capacitors from the circuit at power up by resetting a counter 2504 that controls the application of the switched capacitors.
- the reset signal may be initiated by a controller or generated locally. This provides a known starting point for filter tuning. Next a filter figure of merit is examined to determine iteratively when to stop tuning.
- FIG. 26 illustrates the amplitude 2602 and phase 2604 relationship in an LC filter tuned to its center frequency, fc.
- Amplitude and phase response are parameters that may be used to tune the filter.
- amplitude response 2602 is not the optimal parameter to monitor.
- the top of the response curve is flat making it difficult to judge if the response is exactly centered.
- the phase response 2604 however, has a rather pronounced slope at the center frequency. The steep slope of the phase signal provides an easily discemable transition for determining when the center frequency has been reached.
- phase detection is used to detect when a dummy filter 2506 has been tuned.
- An exemplary 925 MHz input from a narrow band PLL is input 2508 to a phase detector 2510.
- the phase detector compares the phase of a signal input to a dummy filter 2508 to a phase of the output 2512 of that filter 2506.
- the phase detector produces a signal that is internally low pass filtered to produce a DC signal 2514 proportional to the phase difference of the two input signals 2512, 2508.
- the comparator 2516 following the low pass filter is designed to output 2518 a high signal that enables filter capacitors to be switched in until the phase detector 2510 indicates no phase difference is present across the filter 2506 at the tuned frequency. With a zero degree phase shift detected the comparator 2516 disables the counter preventing any further capacitors from being switched into the filter circuit.
- the phase detector 2510 ofthe exemplary embodiment utilizes a gilbert cell mixer 2512 and an integral low pan filter 2525 to detect phase.
- phase detectors may be equivalently substituted for the mixer circuit.
- the 90° phase shift between an i port 2508 and a q port 2512 is being detected by the mixer.
- a 90° phase shift between the i and the q signals in the mixer provides a 0 volt output indicating that those signals are in quadrature relation to each other.
- the signals are shown as differential signals, however single ended signals may equivalently be used.
- the phase detector out 2514 is next fed into a comparator 2516 that is set to trip on a zero crossing detected at its input.
- a comparator 2516 that is set to trip on a zero crossing detected at its input.
- the comparator latches and a counter 2504 is shut off and reset 2518.
- the comparator function is equivalently provided by any standard comparator circuit known by those skilled in the art.
- the counter 2504 counts based on the 10 MHz reference clock 2524, although many periodic signals will suffice as a clock. As the counter advances more filter capacitors are switched into the circuit. In the embodiments ofthe invention 15 control lines 2526 are used to simultaneously switch the capacitors into the dummy filter and the bandpass filter bank. The control lines remain hard wired to both filters 2528, 2506, and are not switched off. However, once the comparator 2516 shuts the counter 2504 off the tuning circuit 2530 is inactive and does not affect the band pass filter 2520 in the signal path.
- FIG. 27 is a schematic diagram showing the internal configuration of switchable capacitors in a differential signal transmission embodiment of the dummy filter 2506 and the construction ofthe phase detector 2510.
- a set of fifteen control lines 2526 are utilized to switch fifteen pair of MOS capacitors 2702 on and off.
- the capacitors are switched in and out by applying a given control signal to a virtual ground point 2704 in this configuration.
- the control signal is being applied at a virtual ground.
- parasitic capacitances at this point will not affect the filter 2506 performance.
- a gain producing LC stage 2706 ofthe dummy filter is of a differential configuration and has its LC elements 2708 connected in parallel with the MOS capacitors 2702.
- a hard wired bus 2526 going to the dummy filter 2506 will switch in 5 unit capacitors, while the other end ofthe line that goes to the bandpass filter (2528 of FIG.25) in the signal path will switch in 3 unit capacitors.
- differential image (“i") signals I P and I N and differential quadrature (“q") signals Q P and Q N are input to the phase detector.
- a conventional Gilbert cell mixer configured as a phase detector 2710, as shown, has delay between the i port 2508 and q port 2512 to the output 2514.
- the i delay to the output tends to be longer due to the fact that it must travel through a greater number of transistors than the q input to output path.
- a second Gilbert cell mixer is duplicated 2710 and connected in parallel with the first 2710.
- phase detectors and other means of equalizing the delay are understood by those skilled in the art to provide an equivalent function.
- the loss pass filter is implemented by a single capacitor 2714 at each output.
- other equivalent methods of achieving a low pass filter known to those skilled in the art are acceptable as well.
- a method of filter tuning the advantageously uses the frequency synthesizer output is fully described in U.S. Patent Application No. filed (B600:34013) entitled “System and Method for On-Chip Filter Tuning" by Pieter Vorenkamp, Klaas Bult and Frank Carr; based on U.S. Provisional Application No. 60/108,459 filed November 12, 1998 (B600:33586), the subject matter of which is incorporated in its entirety by reference.
- Filters contain circuit elements whose values are frequency and temperature dependent.
- frequency dependent circuit elements are capacitors and inductors.
- the fabrication of capacitors is not as problematic as the fabrication of inductors on an integrated circuit. Inductors require relatively more space, and because of their size has a temperature dependent Q.
- FIG. 28 is a plan view of a multi-track spiral inductor.
- An inductor of this type is made from several long narrow strips of metal connect in parallel and disposed upon an integrated circuit substrate.
- a multi-track integrated spiral inductor tends to produce an inductance with a high Q.
- High Q is desirable to achieve lower noise floors, lower phase noise and when used in filters, a better selectivity.
- To reduce series resistance and thus Q of a spiral inductor wide track widths in the spiral are used. However, when track width is increased beyond 10-15 ⁇ m the skin affect causes the series resistance of a spiral inductor to increase at high frequencies. Thus, Q is reduced even though a wide track has been used. This trend tends to limit the maximum Q achievable in integrated spiral inductors.
- An exemplary embodiment ofthe invention utilizes a spiral inductor that is wound with several narrow tracks disposed in parallel upon a substrate. By splitting an exemplary 30 ⁇ m wide track into two 15 ⁇ m tracks disposed in parallel on the substrate, the inductor Q tends to increase.
- Alternative embodiments of the invention by utilize single track spiral inductors or multiple track inductors containing one or more tracks disposed in parallel upon a substrate. In the multiple track inductors described, the tracks are joined together at the beginning of a winding and again joined together at the end of the winding by a conductive material.
- One or more spirals of metal have a series resistance associated with them.
- a spiral can be quite long, thus, the series resistance of the inductor is not negligible in the design of the circuit even with a parallel connection of tracks.
- the series resistance ofthe inductor increases, thus causing the Q to decrease. Circuitry is provided to continuously compensate for this increasing series resistance.
- inductor or coil
- inductors are typically not used in integrated circuits due to the difficulty of fabricating these devices and due to the large amount of area required to fabricate them.
- a given inductance may be realized by a single strip or metallic ribbon of a given width and thickness suspended over a ground plane.
- a multiple track inductor also requires more space than a simple track device. It is a rule of thumb that the higher the frequency the smaller the dimensions of the integrated circuit component required in a filter to achieve a given set of circuit values.
- a spiral inductor ofthe type described in the embodiments ofthe invention allows an inductance to be satisfactorily fabricated on a CMOS substrate. Many alternative embodiments ofthe spiral are known to those skilled in the art.
- the realization of inductance required in any embodiment of the invention is not limited to a particular type of integrated inductor.
- FIG. 29 is an exemplary illustration of the possible effects of inductor Q on filter selectivity in a parallel LC circuit, such as shown in 2706 of FIG. 27.
- the Q of a spiral inductor tends to be low.
- calibration of inductor Q is used.
- the overall effect of this is that when a device with high series resistance and thus, low Q is used as a component in a filter that the overall filter Q is low 2902.
- a high Q filter response is sharper 2984.
- the goal of a filter is to achieve frequency selectivity.
- the filter selectivity is the same electrical property as selectivity in the "front end" ofthe receiver previously described. If the filter has a low Q frequencies outside the pass band of the filter will not achieve as great of an attenuation as if the filter contained high Q components.
- the high degree of selectivity is required to reject the multitude of undesirable distortion products present in a receiver that fall close to the tuned signal. Satisfactory inductor dimensions and device Q have been obstacles in integrating filters on a CMOS substrate. Prediction of the inductance yielded by the spiral is closely approximated by formula.
- FIG. 30 is an illustration of a typical filter bank 3002 utilized in embodiments of the invention for filtering I and Q IF signals 3208.
- Band pass filters utilized in the embodiments of the invention have a center frequency f c and are designed to provide a given selectivity outside of the pass bond.
- the exemplary filters 3002 also inco ⁇ orate gain. Gain and selectivity are provided by a transconductance stage with an LC load resulting in an active filter configuration that gives the filter response shown. Over temperature the filter response degrades as indicated. This degradation is attributed to inductors . With the spiral inductors utilized in the embodiments ofthe invention the gain of this filter stage is substantially determined by the Q or quality factor ofthe inductor.
- the Q is in turn substantially determined by the series resistance ofthe metal in the spiral of the inductor.
- the Q decreases as temperature increases causes an increase in inductor series resistance.
- the decrease in Q with increasing temperature adversely affects the filter characteristics. As can be seen in 306 at FIG. 30 as the temperature increases from 50 °C 3004 to 100°C 3006 overall gain decreases, and selectivity is degraded.
- FIG. 31 is a diagram of an exemplary differential transconductance stage 3102 with an LC load 3104.
- This figure comprises elements of one of the filter gain stages that are a part of one ofthe filters that comprise the filter bank 3002 of FIG. 30 .
- Two forms ofthe LC load's equivalent circuit are shown in the figure 3106, 3108.
- Resistor R(T) has been added 3106 to account for the series resistance of inductor L that tends to increase in direct proportion to the temperature ofthe inductor.
- the circuit may in turn be represented in parallel form 3108 to yield an equivalent response using the elements L' and R'(T).
- a method of compensating for the parallel R'(T) is desirable. It is done by increasing the Q ofthe filters with Q enhancement, and by stabilizing the enhanced value of Q obtained over the range of temperatures encountered in circuit operation. First the implementation of Q enhanced filters is explained.
- FIG. 32 shows a transconductance stage 3102 with an LC load 3104 that is provided with Q enhancement 3202 and Q compensation over temperature 3206.
- Q enhancement 3202 tends to increase the circuit Q thus, increasing the frequency selectivity of the circuit.
- a Q enhancement is provided by the transconductance element's G m , 3202 connected as shown. Addition of this transconductance element is equivalent to adding a negative resistance 3024 that is temperature dependent in parallel with R'(T). This negative resistance tends to cause cancellation ofthe parasitic resistance thus, tending to increase the circuit Q.
- the details of Q enhanced filters are disclosed in more detail in U.S. Patent Application No. filed (B600: ) entitled, "New CMOS Differential Pair Linearization
- inductor quality factor Due to a large positive temperature coefficient inductor quality factor (Q) is proportional to temperature. As temperature increases the resistance in the spiral increases, degrading the Q. The addition of transconductance from the G m stage 3102 tends to increase the Q ofthe filter. However, the effects of temperature on quality factor tends to cause wide gain variation tending to need further improvement.
- Q and gain vary +/- 15% in an unenhanced filter.
- the Q and gain variation is doubled. In multiple stages of filtering used in the embodiments, over 20 db of gain variation is thus encountered over temperature with the Q enhanced filters. This results in an unacceptable change in the conversion gain ofthe receiver.
- FIG. 33 shows a method of stabilizing inductor Q over temperature 3206.
- This method advantageously uses a DC calibration loop 3202 and a dummy inductor 3304 to control the value of inductor series resistance R(T) and a resistive element R(l/T) 3314 to produce a net constant resistance.
- R(T) inductor series resistance
- R(l/T) resistive element
- An electronic device that supplies a variable resistance 3310 of an amount inversely proportional to temperature is added into the circuit 3314.
- the decreasing resistance of the additional resistance 3314 with increasing temperature counteracts the increasing resistance of the inductor's series resistance R(T).
- this decreasing resistance is shown schematically as R(l/T).
- This resistance is provided by the active resistance of a PMOS transistor biased accordingly 3314.
- a PMOS resistor is used in two places 3312,3314 to place the control element 3314 in the circuit and remove the control circuit 3208 from a main circuit 3308.
- the PMOS transistor's gate to source connection is placed in series with the spiral inductor 3306 ofthe LC circuit 3308 making up an active filter stage.
- the active filter stage is controlled from a remotely located control circuit 3208 that contains a duplicate PMOS resistor 3312 and inductor 3304.
- Inductor 3304 is advantageously fabricated with the same mask pattern as used for inductor 3306.
- the control circuitry 3208 is not a part ofthe filter circuitry 3308 in order to prevent undesirable interactions with the radio frequency signals present in the filter.
- the active resistor 3312 in series with the spiral inductor 3304 is duplicated remotely from the filter circuit 3308. To communicate the control signal 3316 the gate ofthe PMOS resistor 3312 is coupled to the gate ofthe PMOS resistor in the filter 3314.
- the control circuit provides a conventional constant current and a conventional constant voltage source function to maintain a constant current through and voltage across the dummy spiral inductor 3304 duplicated in the control circuit.
- An exemplary constant current and constant voltage source is shown 3302 inco ⁇ orating a dummy inductor 3304.
- any circuit that maintains a constant voltage across, and current through the inductor 3304 in the control circuit 3208 is sufficient for the design.
- the gate control signal 3316 is simultaneously fed to the LC filter stage 3308 PMOS transmitter 3314 to control the resistance, and thus the Q, ofthe inductor in the filter circuit 3308.
- An exemplary constant current and voltage source is illustrated 3302 comprising dummy inductor 3304.
- a temperature independent voltage reference V ref is established by resistor R and conventional current sources I.
- Amplifier A's negative input is connected to the voltage reference, and its positive input is connected to a symmetrical point between an identical current source and the dummy inductor.
- the output of amplifier A is fed into the gate ofthe transistor functioning as a variable resistor 3312.
- the constant voltage drop over temperature at the node V ref is compared to the voltage at the positive amplifier terminal.
- the amplifier controls the resistance ofthe PMOS transistor so that a constant current and constant voltage are maintained across the dummy inductor.
- FIG. 34 is a block diagram of a communications network utilizing a receiver 3402 according to an exemplary embodiment of the invention.
- a communications network such as a cable TV network 3404, capable of generating signals provides radio frequency signals 3406 over the air waves, through a cable or other transmission.
- a receiver front end 3408 next converts the RF single ended signal to a differential signal.
- a receiver front end, or a Balun may be used to convert a single ended signal 3406 to a differential signal or vise versa 3410.
- the receiver block which contains an exemplary embodiment of the invention next converts the differential radio frequency signal 3410 to a differential intermediate frequency (IF) 3412.
- the IF signal 3412 is next converted down to PC and demodulated into a base band signal 3414 by a demodulator 3416.
- the base band signal 3414 is suitable for presentation to the video input of a television receiver, the audio inputs to a stereo, a set top box, or other such circuitry that converts the base band signal into the intended information output.
- the communication system described is contemplated to provide the function described above in one or more circuit assemblies, integrated circuits or a mixture of these implementations.
- the RF front end 3408 may be integrated in a single chip with receiver 3402.
- the front end and receiver may be implemented as individual integrated circuits, on any suitable material such as CMOS.
- the receiving system described utilizes additional exemplary embodiments that inco ⁇ orate one or more transmitters and one or more receivers to form a "transceiver" or “multiband transceiver.”
- the transceiver contemplated may transmit and receive on differing frequencies or the same frequency with appropriate diplexer, transmit receive switching or functionally equivalent circuitry.
- control signal 4302 representative ofthe signal level of base band signal 3414 (FIG. 34) is fedback from block 3416 to RF front end 3408.
- control signal 4302 could be formed by sampling the sync pulses ofthe base band television signal and averaging the amplitude ofthe sync pulses over a period of time.
- the present invention has eliminated the need for switches, reducing a major contributor to increased noise figure.
- an integrated switchless programmable attenuator and low noise amplifier only two elements are present in the signal path to contribute to the noise figure.
- First an attenuator is present in the circuit path.
- the next element in series with the attenuator in the signal path is a differential pair low noise (LNA) amplifier.
- LNA differential pair low noise
- the differential pair noise figure is lowered by introducing a sufficient bias current to increase a transconductance g m associated with the amplifier. The increased g m decreases the noise contribution of the differential pair.
- FIG.35 is an illustration ofthe input and output characteristics of an integrated switchless programmable attenuator and low noise amplifier 3502.
- Attenuator/ amplifier 3502 simulates a continuously variable potentiometer that feed a linear amplifier.
- the exemplary embodiment is a two radio frequency (RF) port device ⁇ the input port 3504 is configured to receive a single ended input signal from a source 3508 and the output port 3506 is configured to present a differential signal.
- RF radio frequency
- multiple control signals 3512 are applied to the integrated switchless attenuator and LNA 3502. For example these signals are used to program the attenuator to various levels of attenuation, and for an output smoothness control.
- the differential output 3506 advantageously tends to provide noise rejection.
- the signal at one terminal is 180 ° out of phase from the signal at the other terminal and both signals are of substantially equal amplitude.
- Differential signals have the advantage that noise that is injected on either terminal tends to be canceled when the signal is converted back to a single ended signal.
- Such common mode noise is typically of equal amplitude on each pin and is typically caused by radiation into the circuit from external sources, or it is often generated in the circuit substrate itself.
- the present invention uses differential signal transmission at its output. It should be noted that in alternate embodiments of the invention, that a signal ended output can be produced from the differential signal by various techniques known in the art. Also, equivalently a differential input may be substituted for the single ended input shown.
- FIG. 36 is a functional block diagram of the integrated switchless programmable attenuator and low noise amplifier circuit. This embodiment illustrates how it is possible to eliminate switches that would be required in a conventional attenuator and LNA.
- a resistive attenuator 3601 is configured as a ladder circuit made up of resistors configured as multiple pi sections 3602. A method of selecting resistor values such that a constant impedance is presented to the signal source is accomplished as is conventionally known in the art.
- An exemplary embodiment utilizes an R/2R configuration.
- Each pi section 3602 of the attenuator 3601 is connected to one input to a differential pair amplifier 3603. The other input to amplifier 3603 is grounded.
- the resulting attenuation produced at the output 3604 is controlled by the number of differential amplifier stages that are turned on and the degree to which they are turned on.
- tail-current generators 3605 are turned on or off by tail-current generators 3605 associated with each stage 3603, respectively. Generation ofthe tail currents is discussed in more detail below in connection with FIG. 44a and 44b.
- a zero or one is used to indicate if the corresponding tail-current generator 3605 is turned on or off, that is whether or not a tail- current is present. For example, a zero is used to show that no tail-current is present and the corresponding generator 3605 is turned off.
- a one represents a tail-current generator 3605 that is turned on rendering the corresponding amplifier 3603 functional.
- the zeroes or ones are provided by the control lines 3512 of FIG. 35 in a manner described in more detail in FIG. 43. All ofthe individual amplifier outputs 3506 are differential.
- Differential outputs 3506 are tied in parallel with each other.
- the resulting output 3604 is the parallel combination ofthe one or more amplifiers 3608,3610,3612 that are turned on.
- amplifiers have been implemented, with various combinations turned on successively. By using tail currents to selectively turn amplifiers 3603 on and off, the use of switches is avoided.
- any combination of amplifiers 3603 could be turned on or off to achieve a given attenuation before amplification of the signal.
- adjacent pairs of amplifiers are turned on and off.
- Groupings of amplifiers in the on state can be of any number.
- ten contiguous amplifiers are turned on.
- the attenuation is adjusted up or down by turning an amplifier tail current off at one end of a chain of amplifiers, and on at the other to move the attenuation in the desired direction.
- the exemplary circuit is controlled such that a group of amplifiers that are turned on slides up and down the chain according to the control signals 3512 of FIG. 35.
- any number of amplifiers 3603 can be grouped together to achieve the desired resolution in attenuation.
- input signals 3614 that are presented to attenuator pi sections 3602 whose amplifiers are not turned on do not contribute to the output signal 3604. It can be seen from FIG. 36 that the signal strength ofthe output is dependent upon where the grouping of generators 3605 are turned on.
- FIG. 37 is a simplified diagram showing the connection 3702 of multiple attenuator sections 3602 to the output 3604.
- An attenuator 3601 is made up of multiple pi sections 3602 cascaded together. Each pi section consists of two resistances of 2R shunted to ground, with a resistor of value R connected between the non grounded nodes. Tap points 3702 are available at the nodes ofthe resistor R. In FIG. 37 the first set of nodes available for tap points in the first pi section would be nodes 3706 and 3708. After cascading all of the pi sections to form a ladder network, a variety of tap points are available, these are noted as node numbers 3706- 37150 in FIG. 37.
- a path from the input 3614 to any ofthe tap points, or nodes on the ladder network yields a known value of attenuation at the output 3604. If multiple tap points are simultaneously connected to the attenuator, the resulting attenuation is the parallel combination of each connection.
- the combined or average attenuation at the output terminal can be calculated mathematically or, it can be determined using circuit simulation techniques available in computer analysis programs.
- FIG. 37 it can be seen from FIG. 37 that by providing multiple tap points on a ladder network that in effect a sliding multiple contact action can be implemented contacting a fixed number of contacts, for any given position of the simulated slide 3716.
- the slide 3716 is implemented electronically in the embodiments ofthe invention
- the average attenuation by contacting a fixed number of these tap points 3706-3715 will increase as the slide or switch is moved from the left to the right on the ladder network.
- minimum attenuation will be present when the slider 3716 contacts the force tap points 3706,3707,3708,3709 at the far left ofthe ladder network 3601.
- the maximum attenuation will be achieved when the slider 3716 is positioned to contact tap points 3712,3713,3714,3715 at the far right ofthe network.
- contacts are shown, however, in practice any number of contacts may be utilized.
- FIG.38 is an illustration of an exemplary embodiment showing how the attenuator 3601 can be removed from the circuit, so that only the LNAs or differential stages 3605 are connected.
- Reference numerals 3801 to 3816 each represent a differential amplifier 3603 and a generator 3605 in FIG. 36. In the 0 dB attenuation case shown the signal strength of the output would be equal to the gain of the parallel combination of the four amplifiers that are turned on 3801,3802,3803,3804.
- the four activated amplifiers are indicated by a "1" placed on the circuit diagram.
- the sliding tap arrangement is used such that a given number of amplifiers are always turned on the configuration of FIG. 38 is necessary such that zero decibels of attenuation can be achieved when the required number of amplifiers are always turned on.
- a full 14 dB gain from a combination of ten amplifiers is seen when a ten tap configuration is used with the top set to the 0 dB attenuation position.
- FIG. 39 shows an exemplary attenuator circuit used to achieve 1 dB/step attenuation.
- Each resistive pi section 3602 makes up one step.
- the characteristic impedance of the embodiment shown is 130 ohms.
- a pi pad having a characteristic impedance of 130 ohms may be realized utilizing series resistors R, of 14 ohms or parallel or shunt resistors of 1,300 ohms R p .
- FIG.40 illustrates an exemplary embodiment of an attenuator for achieving a finer resolution in attenuation.
- a resolution of .04 dB/tap is achieved.
- each series resistor R ⁇ ., connected between the shunt resistors in the ladder network has a string of series resistors connected in parallel with it.
- Each interconnection point between the added resistors 3402 provides a tap point that provides a finer adjustment in attenuation values.
- calculating the overall gain of a parallel combination of amplified and attenuated signals is analytically complex to calculate. For example, consider an embodiment utilizing 10 differential pair amplifiers in the output, connected to 10 different tap points. Ten signals receiving varying attenuations are fed into individual differential pair amplifiers. Gain ofthe amplifiers varies according to an adjustment for monotonicity . The amplified signals are then combined in parallel to yield the output signal.
- Tail currents in the differential output amplifiers are not all equal.
- the tail currents determine the gain of a differential pair, and are adjusted to provide a specific degree of monotonicity.
- the gain of each of the differential pair amplifiers varies across the 10 interconnected amplifier.
- the attenuation varies since each tap is taken at a different point to be fed into each ofthe differential amplifiers.
- the middle signal line would represent the average, yielding an approximate figure for the attenuation and gain of the combination of 10 signal lines.
- this is not the result.
- Through the use of computer simulation the behavior of this network has been simulated. In simulating behavior of this network it is found that the first tap predominates in defining a response from the sum ofthe 10 taps. The first tap has the least attenuation and this yields the predominant signal characteristics.
- the amplifier gain is a constant 14dB.
- the attenuator range is from 0-25 dB in IdB steps. This yields an overall range of -11 dB to +14 dB for the combination of attenuator and amplifiers.
- FIG.41 illustrates the construction ofthe series and parallel resistors used an integrated attenuator.
- all ofthe resistors used are 130 ohms. This is done to control the repeatability ofthe resistor values during fabrication.
- Ten of these resistors are connected in parallel to yield the 13 ohm resistor used as the series attenuator element R j of FIG. 39.
- Ten of these 130 ohm resistors are connected in series to yield 1,300 ohms to realize the parallel resistance legs R p of FIG. 39 ofthe attenuator.
- Building the attenuator from unit resistors of 130 ohms also, provides improved matching. By matching resistor values in this method ariability is minimized to that ofthe interconnections between the resistors. This allows the ratio between series and parallel resistances to remain constant from pi section to pi section 3602 in the ladder network that makes up the attenuator 3601 of FIG. 36.
- FIG. 42 is an illustration of an exemplary embodiment utilized to turn on each ofthe differential amplifiers. This arrangement produces a monotonically increasing output verses control voltage 4202.
- five amplifiers 4204-4208 grouped together make up the electronically sliding tap arrangement. Numbers on the illustration indicate the fractions of tail-currents relative to the full value used to turn on each amplifier.
- Amplifiers are partially turned on at the ends ofthe group. Gradual turn on ofthe amplifiers at the ends ofthe group is done to control overshoots and undershoots in the amplifier gain. These over shoots and under shoots are seen upon the application of a control voltage applied.
- Varying a smoothness control provided in a programmable attentuator and LNA to one extreme yields good linearity in the frequency response but overshoots in gain with increases in control voltage. Varying the smoothness control to the other extreme yields a very smooth gain verses control voltage curve with more nonlinearity.
- the optimum value for the smoothness control yields a value of monotonicity that is the maximum that the system can tolerate in the form of data loss throughout the circuit.
- the gain versus control voltage curve would be as shown in the solid line 4210. By not fully turning on some of the differential pair amplifiers the overshoot and undershoot in the gain versus control voltage curve may be minimized. With the tail-currents configured on the sliding tap as shown in FIG.42, the gain versus control voltage curve will appear as shown by the dotted line 4202. In this configuration, the middle three amplifiers have their tail-currents fully turned on with the remaining two amplifiers at the beginning and end ofthe chain only having their tail-currents half turned on. Equivalently, other weighing of total currents may be used to achieve substantially the same effect.
- a plot of gain versus control voltage for the entire integrated switchless programmable attenuator and low noise amplifier would preferably appear as a staircase over the entire control voltage range.
- the non-monotonicity ofthe gain versus the control voltage curve is reduced so that the gain monotonically increases with the application of an increasing control voltage to yield the desired stair step shape response, where
- FIG. 42 illustrates one "step” 4202 in the response.
- Non-monotonicity in gain versus control voltage is not a time dependent phenomenon. The shape ofthe curve tends to depends on the physical implementation of a circuit and a switching arrangement for turning tail-currents on and off. Non-monotonicity is an undesirable characteristic tends to degrade overall systems performance. In receiving QAM data the degradation is seen as a loss in received data. By improving the monotonicity characteristic of an amplifier linearity ofthe amplifier is degraded. Gradual switching ofthe tail-currents causes some differential pairs to only partially turn on. Differential pairs that are partially turned on introduce more nonlinearities into the circuit output than a fully turned on differential pair.
- a transistor that is only partially turned on is only capable of handling a smaller signal than one that is more fully turned on.
- the linearity tends to be degraded, however, this degradation in linearity allows a monotonically increasing gain versus control voltage curve to be achieved.
- an automatic gain control (AGC) 3512 of FIG. 35 would be generated as one ofthe control signals by external receiver circuitry to adjust the input signal level presented to the receiver.
- This AGC control voltage would be fed into a control voltage input 3512 to select a value of attenuation through the circuit assembly. It is desirable to switch the attenuator such that when the attenuation is adjusted, the data is not lost due to the switching period. In an exemplary embodiment of the present invention it is necessary to switch a maximum of .04 dB per step in attenuation value.
- FIG. 43 is an illustration of an embodiment showing how individual control signals 4301 used to turn on individual differential pair amplifiers are generated from a single control signal 4302.
- control signals to turn on the differential pair amplifiers There are many ways to generate control signals to turn on the differential pair amplifiers, individual control lines may be utilized, or a digital to analog converter may be used to transform a digital address to an analog control voltage.
- resistors 4304 are connected in series between a power supply voltage and ground to create a series of reference voltages at each interconnecting node. The voltages at each node between the resistors is the reference input for one of a series of comparators 4306.
- the reference input of the comparator connects to a node providing the reference voltage setting.
- the other input ofthe comparator is connected to the control voltage 4302.
- the comparator When the value ofthe control voltage exceeds that ofthe reference voltage for a given comparator the comparator goes from a zero state to a one state at its output.
- the zero state is typically zero volts and the one state is typically some voltage above zero.
- the voltage generated to produce the logic one state is such that when applied to a gate of a transistor making up the current tail 4308 it is sufficient to turn on the differential pair of amplifiers that constitute the low noise amplifier (LNA) controlled by that current tail.
- LNA low noise amplifier
- FIG. 44 is an illustration of an embodiment of one ofthe individual comparator stages 4308 of FIG. 43 used to turn on or off individual LNA amplifier stages.
- the circuitry used to activate individual cells is duplicated at each attenuator's tap point and interconnected so that a sliding tap can be simulated using a single control voltage, V ctr 4302.
- V ctr 4302. In describing a cell's operation it is convenient to start with the control voltage 4302 that is being applied to achieve a given attenuation value.
- a control voltage is applied to each of a series of comparators, as is shown in FIG. 43.
- the circuit of FIG. 44 makes up one of these comparators.
- FIG.44 shows the control voltage as V ctr , and the reference voltage as V ref . These voltages are applied to the gates of a differential pair of transistors (Q 1 Q2).
- next 10 cells are turned on by the control signal "next (cell n+10)". These cells have not yet had their comparators tripped by the control voltage present on their inputs. Thus the bottom of the sliding tap is pushed up and down by the control voltage, V ctr . In this state transistors Q16 and Q17 in the next 10 cells are not conducting current away from the current mirror. This allows the current tails of each amplifier, Q 15 to conduct causing amplifier Amp n to be turned on in each ofthe 10 cells.
- Transistors Q3 and Q10 are being used as variable resistors. These variable resistors are used to change the gain ofthe comparator. Varying the gain ofthe comparator allows the abruptness in the overall amplifier gain to be controlled. Putting a high voltage on "smoothness control" causes the drain of Q5 and Q6 to be shorted together. The gain is reduced and a very gradual transition between states is provided by doing this.
- FIG. 19 a block diagram illustrating the exemplary frequency conversions utilized in the embodiments ofthe invention.
- An RF signal 1906 from 50 MHz to 860 MHz that is made up of a plurality of CATV channels is mixed 1916 down by a first LO (LO,) 1912 that ranges from 1250 MHz to 2060 MHz, depending upon the channel tuned, to a first IF signal 1918 that is centered at 1,200 MHz.
- This 1,200 MHz first IF signal is passed through a first filter bank 1912 of cascaded band pass filters to remove undesired spurious signals.
- the first frequency conversion in the receiver is an up conversion to a first intermediate frequency 1918 higher than the received RF frequency 1906.
- the first intermediate frequency is next mixed 1932 down to a second IF 1922.
- a second local oscillator signal at 925 MHz (L0 2 ) 1904 is used to mix 1932 the first IF 1918 down to a second IF 1922 signal centered at 275 MHz.
- a second bank of band pass filters 1934 removes spurious outputs from this second IF signal 1922, that have been generated in the first two frequency conversions.
- a third frequency conversion 1924, or the second down conversion to the third IF 1926 is accomplished with a third LO (LO 3 ) 1930 of 231 MHz.
- a third filter 1936 removes any spurious responses created by the third frequency conversion and any remaining spurious responses that have escaped rejection through the previous two filter banks. This third band pass filter 1936 may have its response centered at 36 or 44 MHz.
- a 44 MHz IF produced by the 231 MHz LO is used in the United States while a 36 MHz IF is used in Europe.
- the L0 3 is adjusted accordingly to produce the 36 MHz IF.
- the local oscillator's signals are advantageously generated on chip in the described embodiments. However, the receiver implementation need not necessarily be limited to on chip frequency generation. LOCAL OSCILLATOR GENERATION
- FIG. 45 is a block diagram illustrating the exemplary generation of local oscillator signals utilized in the embodiments of the invention.
- the frequency plan utilized in the embodiments utilizes a pure third local oscillator signal (LO 3 ) 1930, created by direct synthesis 4502 that falls within the band of received signals.
- LO 2 1904 signals are generated using indirect synthesis achieved by a phase locked loops 4504,4506.
- the third local oscillator signal (LO 3 ) uses direct synthesis, to divide the second local oscillator down to create the third local oscillator (LO 3 ).
- the indirect synthesis ofthe first and second LOs utilizes a frequency reference 4508 provided by a 10 MHz crystal oscillator.
- the 10 MHz crystal oscillator utilizes the previously disclosed differential signal transmission and a unique design that advantageously tends to provide an extremely low phase noise reference signal.
- the first local oscillator (LO,) 1902 is produced by wide band tuning.
- the second local oscillator (LO 2 ) 1904 is produced by narrow band tuning.
- the exemplary embodiments advantageously utilize a narrow band tuning circuit and method to achieve frequency lock in an exemplary narrow band PLL.
- FIG. 46 is a schematic of a PLL having its VCO controlled by an embodiment of the VCO tuning control circuit.
- a VCO tuning control circuit is provided to tune a VCO that is contained in an exemplary narrow band PLL that generates a 925 MHz local oscillator signal.
- This device makes use of a temperature and process dependent window of voltage ranges to optimally choose a range of valid control voltages for the PLL.
- the control circuit uses a window to center a varactor diode's tuning range by adding or removing capacitance, thus tending to avoid gross varactor non-linearities.
- the circuit tends to mitigate dead band conditions and tends to improve loop stability over process and temperature variations.
- a VCO integrated on a chip can be up to ⁇ 20% off in its frequency range. Immediate calibration at power up is done to center the varactor diodes that provide a variable tuning capacitance to the middle of the varactor diode's tuning range. This is done by switching in capacitors and monitoring loop voltage. To center the VCO's tuning capacitance range ofthe varactors, the embodiments of the invention immediately calibrate the VCO by adding or removing capacitance. Switching capacitors in or out of the circuit centers the varactor' s capacitance into the middle ofthe VCO's tuning range. To monitor centering ofthe varactors a window comparator is used to look at the state of a control voltage that is used to tune the VCO. The window comparator determines when the control voltage is within its desired range.
- FIG.46 illustrates the VCO tuning control circuitry 4604 applied to a conventional PLL
- PLL 4602 comprises a crystal oscillator 4606 that inputs a stable frequency to a programmable 4608 reference divider 4610 that outputs a frequency 4612 based upon the reference frequency to the input of a phase detector 4614, a second input 4616 to the phase detector is the current output of a VCO 4618.
- the phases of the two inputs 4612,4616 are compared and a DC value representing the phase difference is output 4620 to the input of a charge pump 4622.
- the output of the charge pump is fed into a low pass filter 4624.
- the output of low pass filter 4624 is fed into the control voltage input ofthe VCO 4618.
- the VCO outputs an image and quadrature signal 4626 at a frequency as set by the frequency select line
- the voltage controlled oscillator 4618 is conventionally constmcted, and comprises a variable capacitance used to tune the output frequency.
- VCO 4618 additionally comprises a series of switchable capacitors utilized to center the tuning range ofthe variable capacitance elements comprising the VCO.
- the switchable capacitors are controlled by signals emanating from the VCO tuning control circuitry 4604.
- the control signals 4628 are routed from tuning register 4630 to VCO 4618.
- the VCO tuning control circuitry utilizes a control signal 4632 taken from low pass filter 4624.
- Control voltage 4632 is input to the positive inputs of a first comparator 4634 and the positive input of a second comparator 4636.
- the negative inputs of comparators 4634 and 4636 are coupled to DC reference voltages VI and V2.
- Comparator 4634 outputs signal lsb and comparator 4636 output signal msb.
- Voltages V, and V 2 set thresholds to form a sliding window which monitors the state ofthe closed PLL by monitoring voltage at low pass filter 4624.
- Control voltage 4632 is taken as the voltage across a capacitor in the low pass filter that induces a zero in the loop filter 4624.
- the control voltage is a filtered version of the control voltage ofthe PLL loop, and thus tends to have eliminated spurious components present on the VCO control line.
- Signals msb and lsb are fed in parallel to an AND gate 4640 and an exclusive NOR gate 4642.
- the output of exclusive NOR gate 4642 is fed into the D input of a DQ flip-flop 4644.
- the Q output ofthe flip-flop is fed into an AND gate 4646. whose output is in turn fed into the clock input of a 6-bit bi-directional tuning register 4630.
- DQ flip-flop 4644 receives a reset signal based on the output of low pass filter 4624. flip-flop 4644 is also clocked by a signal based on the divided reference oscillator signal 4612.
- FIG. 47 is a process flow diagram illustrating the process of tuning the VCO with an embodiment of a VCO control circuit.
- the control voltage 4632 of FIG. 46
- the control voltage is evaluated to see if it falls within a predetermined window 4702. If the voltage is within the desired range, the time it has remained so is determined 4704.
- the PLL tends to be in a state of lock when the control voltage applied to the VCO has remained unchanged for a predetermined period of time. If the voltage does not remain in range for the predetermined time, the process is reinitiated by looping back to the beginning. If the control voltage remains in the range for the predetermined time, the loop is deemed in lock, and the process is ended
- the process flow is routed to the beginning ofthe process, where the control voltage is again reevaluated 4702.
- the VCO tuning control circuitry 4604 of FIG. 46 functions to carry out the process of
- FIG. 47 If the voltage ofthe loop lies outside the window defined by the threshold voltages
- the clock input to the 6-bit bi-directional tuning register 4630 is enabled.
- This register function may be provided by a conventional circuitry known in the art to provide this function and is not limited to the circuitry depicted.
- a "lock time out" circuit 4648 of FIG.46 is reset on the rising edge ofthe clock signal to the 6-bit bi-directional tuning register 4630 of
- FIG. 46 The "lock time out" circuit is conventionally constmcted and is not limited to the components depicted in FIG. 46.
- control voltage 4632 exceeds the upper threshold set by the comparators, zeros are shifted through the register 4630. A zero voltage decreases the capacitance in the VCO tuning circuitry by switching out a capacitance controlled by one of the 6 control lines 4628.
- control lines may be used other then the exemplary six.
- This shifting of values in a register allows one of six exemplary capacitor switch control lines to be activated or deactivated, an evaluation made and another line activated or deactivated so that the previous tuning setting is not lost.
- This function may be implemented by passing a value (on or off) down a line of capacitors by shifting or by activating a capacitor associated with a given line and then a next capacitor without shifting the capacitance control signal.
- control voltage 4632 is less than the lower threshold voltage of the comparator
- Is are shifted through the 6-bit bi-directional tuning register.
- the Is increase the capacitance applied in the VCO tuning circuit by switching in a capacitance controlled by one ofthe 6 control lines 4628.
- control voltage 4632 enters the predetermined valid range of operation as set by voltages V, and V 2 the shift register 4630 is disabled. At this time the locked time out circuit
- FIG. 48 is a block diagram of a first exemplary embodiment of a receiver.
- FIGS. 48, 51, 52, 53 and 54 are embodiments of receivers that utilize band pass filters and image reject mixers to achieve image rejection that tend to reduce the distortion previously described.
- the embodiments advantageously convert an input signal (1906 of FIGs 19, 48, 51, 52, 53 and 54) to a final IF frequency (1914 of FIGs 1948, 51, 52, 53 and 54) by processing the input signal substantially as shown in FIG. 19.
- Image rejection is measured relative to the signal strength of the desired signal.
- the strength ofthe unwanted image frequency is measured in units of decibels below the desired carrier (dB c ).
- an image frequency rejection of 60 to 65 dB c is required.
- this requirement has been split more or less equally among a series of cascaded filter banks and mixers following the filters.
- the filter banks 1912,1934 provide 30 to 35 dB c image rejection and complex mixers 4802,4806 used provide an additional 30 to 35 dB c of image rejection yielding an overall image rejection of 60 to 70 dB c for the combination.
- the use of complex mixing advantageously allows the rejection requirements on the filters to be relaxed. First, a channel of an input spectrum is centered about a first IF frequency.
- FIG. 49 is an exemplary illustration of the frequency planning utilized in the embodiments ofthe invention for the reception of CATV signals.
- the frequency spectrum at the top of the figure 4902 illustrates exemplary received RF signals ranging from 50 to 860 MHz 4904.
- the received RF signals are applied to a band pass filter 4921 to eliminate out of band distortion products Imagel 4906.
- the frequency plan advantageously utilizes a trade off between image rejection achievable by filters and mixers at different frequencies.
- the processing of the first IF and the second IF have many features in common and will be discussed together in the following paragraphs.
- the second mixer 4802 and second bank of IF filters 4834 of FIG. 48 achieve 35 dB and 35 dB of image rejection, respectively.
- IF filter bank 1936 of FIG. 48 achieve 25 dB and 40 dB of image rejection respectively.
- the last distribution reflects the fact that at the lower third IF frequency the Q ofthe filters tend to be lower, and the image rejection ofthe mixers tend to be improved at lower frequencies.
- a signal 1906 in the 50 to 860 MHz range is up converted by mixer 1916 and L02 1908 to 1,200 MHz IF- 1 1918.
- the presence of LO-2 1904 at 925 MHz that is required to mix the signal IF-1 1918 down to the 275 MHz IF-2 1922 has an image frequency Image2 (4908 as shown in FIG.49) at 650 MHz.
- the filter Q ofthe 1,200 MHz center frequency LC filter 1912 causes Image2 to undergo 35 dB of rejection thus, attenuating it.
- Phase matching at lower frequencies is more accurate allowing better image rejection to be obtained from the third mixer.
- the method of trading off filter selectivity against mixer image rejection at different frequencies advantageously allows a receiver to successful integrate the filters on chip with the desired image frequency rejection. This process is described in detail in the following paragraphs.
- a local oscillator 1908 produces frequencies from 1,250 MHz to 2060 MHz. For example, a channel centered at 50 MHz is mixed with the local oscillator set at 1,250 MHz to produce first IF frequency components 1918 at 1,200 MHz and 1.300 MHz. Only one of the two frequency components containing identical information produced by the mixing process is needed; the low side 1,200 MHz component is kept. Filtering 1912 tends to remove the unneeded high side component and other desired signals.
- first IF 1918 to be centered at 1,200 MHz makes the first IF susceptible to interference from a range of first image frequencies from 2,450 MHz to 3,260 MHz (4906 as shown in FIG. 49), depending upon the channel tuned.
- the lower image frequency of 2,450 MHz results from the first IF of 1,200 MHz being added to the lowest first LO present at 1,250 MHz to yield 2,450 MHz.
- the highest image frequency results from the first IF of 1 ,200 MHz being added to the highest first LO of 2.060 MHz to yield 3 ,260 MHz as the highest first image.
- Choosing the first IF 1918 at 1,200 MHz yields image frequencies (4906 of
- FIG. 49 that are well out of the band of the receiver. The result tends to place undesired frequencies far down on the filter skirts of filters present in the receiver, attenuating them.
- a channel is up conversion to a first IF 1918 of 1 ,200 MHz, it is next filtered by a bank of 3 LC band pass filters 1912 each having its response centered at 1,200 MHz in the embodiment.
- These filters in conjunction with the second mixer 4802 provide 70 dB of image frequency rejection (4908 of FIG. 49).
- Filters are advantageously integrated onto the CMOS substrate.
- An LC filter comprises inductors (or coils) and capacitors.
- An inductor implemented on a CMOS substrate tends to have a low Q. The low Q has the effect of reducing the selectivity and thus the attenuation of signals out of band.
- the attenuation of signals out of band can be increased by cascading one or more filters.
- Cascading filters with identical response curves has the effect of increasing the selectivity, or further attenuating out of band signals.
- the embodiments of the invention advantageously inco ⁇ orate active g m stage filters 1912,1934 to increase selectivity and provide circuit gain to boost in band signal strength.
- Three cascaded active LC filters implemented on a CMOS substrate yield a satisfactory in band gain, and provide approximately 35 dB of out of band image signal rejection in the embodiment described.
- the filters need not be limited to active LC filters, other characteristics and passive filters are contemplate equivalents.
- differential I/Q mixers 4802,4806 are advantageously used to achieve this approximate 35 dB of additional image rejection required in the first IF.
- FIG. 50 is a block diagram illustrating how image frequency cancellation is achieved in an I/Q mixer.
- An I/Q mixer is a device previously developed to achieve single side band signal transmission. It is one of three known methods for eliminating one of two side bands. This type of mixer is able to transmit one signal while eliminating or canceling another signal.
- An I/Q mixer advantageously possesses the properties of image frequency cancellation in addition to frequency conversion. For example, returning to FIG. 48, a second LO 1904 of 925 MHz is used to create the down conversion to a second IF 1922 of 275 MHz, while rejecting image frequencies from the previous frequency conversion by LOl 1908.
- the I/Q mixers are implemented in several ways in the invention. However the overall function is maintained. An interconnection of components that achieves I/Q mixing is illustrated in the exemplary I/Q mixer 4802 shown in FIG. 48.
- First an input signal 1918 is input to a mixer assembly comprising two conventional mixers 4828, 4830 of either a differential (as shown) or single ended construction.
- Local oscillator signals 1904 that need not necessarily be buffered to achieve I/Q mixing, are applied to each mixer.
- the local oscillator signals applied to each mixer are ofthe same frequency, but 90 degrees out of phase with each other. Thus, one signal is a sine function, and the other is a cosine at the local oscillator frequency.
- the 90 degree phase shift can be generated in the I/Q mixer or externally.
- a conventional poly phase circuit 4832 provides the phase shift and splitting of a local oscillator signal generated by PLL2 4806.
- Two IF signals, an I IF signal and a Q IF signal are output from the mixers and fed into another conventional poly phase circuit 4834.
- the poly phase circuit outputs a single differential output IF signal.
- the I/Q mixer uses two multipliers 5002,5004 and two phase shift networks 5006,5008 to implement a trigonometric identity that results in passing one signal and canceling the other.
- the trigonometric identity utilized is:
- f ⁇ is an input signal 5010 f L0 , is the first LO 5012
- the product ofthe sine waves 5014 is:
- Two frequencies are created by each multiplication. Two ofthe frequencies have the same sign and frequency, so that when they are added together 5018 the resultant signal is a positive sum 5020. The other frequency created cancels itself out 5022.
- the sum frequency component created by the product ofthe sines is a negative quantity.
- the same sum frequency component created by the multiplication of the cosines is positive and of equal magnitude.
- the difference that is present in each signal has twice the amplitude of the individual signals and the second, sum frequency created is of opposite polarity ofthe other signal created and cancels out when the signals are added together.
- the difference frequency is passed to the output while the sum frequency component is canceled.
- a required image frequency rejection is obtained.
- the frequency of a first up conversion has been advantageously selected to place an image frequency of a first LO well down the filter skirts of a 1 ,200 MHz LC filter bank, thus achieving the desired image frequency rejection.
- buffer amplifiers 4810 are used to recondition the amplitudes of LO signals 1908,1904,1930 that drive the I/Q ports of mixers 4802,4806.
- a distance of several millimeters across a chip from where LOs are generated 4504,4506,4508,4502 to where it is applied at the mixers 1916,4802,4806 tends to require reconditioning ofthe slopes ofthe local oscillator signals. Buffering also tends to prevent loading ofthe PLLs 4504,4806.
- Eliminating any preselection filtering requiring tunable band pass filters is desirable.
- To do this image frequency response and local oscillator (LO) signals are set to fall outside of a received signals bandwidth.
- the first signal conversion tends to eliminate any requirements for channel selectivity filtering in the receiver front end. Because of the integrated circuit approach to this design it is desirable to locate an LO outside ofthe signal bandwidth to reduce distortion created by the interaction ofthe received signals and the first local oscillator signals.
- a SAW filter is a piezoelectric device that converts an electrical signal to a mechanical vibration signal and then back to an electrical signal. Filtering is achieved through the interaction of signal transducers in the conversion process.
- a filter of this type is typically constmcted on a zinc oxide (ZnO 2 ), a material that is incompatible with integration on a CMOS circuit utilizing a silicon (Si) substrate.
- SAW or other filter types known in the art including external LC filters are contemplate embodiments.
- a hybrid construction utilizing receiver integrated circuit bonded to a hybrid substrate and filters disposed on the substrate is contemplated.
- Image2 image response
- a 650 MHz signal will be mixed down to the second IF frequency (IF 2 ) ( 1922 of FIG.48) causing interference with the desired received signal which is now located at the second IF frequency.
- the receiver has been designed to produce greater than 65 dB of rejection of Lmage2 by the mechanism previously described for the 1,200 MHz LC filter bank 1912 of FIG. 48.
- the third IF is next generated.
- the third LO 1930 is created by direct synthesis.
- the divide by 4 block 4802 creates a 231 MHz third LO (L0 3 ) consisting of I and Q signals required to mix the 275 MHz second IF 1922 down to the third and final IF frequency of 44 MHz 1926.
- a second down conversion to the 275 MHz third IF is used in the design. If a 1,200 MHz first IF signal were down converted directly to 44 MHz a local oscillator signal of 1156 MHz (1,200 MHz - 44 MHz) would be required. A resulting image frequency for this local oscillator would be at 1 , 112 MHz ( 1 ,200 MHz - 88 MHz).
- a 1 , 112 MHz image would fall within the band ofthe 1,200 MHz LC filter. Thus, there would be no rejection of this image frequency from the first IF's filter since it falls in the pass hand. Therefore, the intermediate frequency conversion to a second IF of 275 MHz is used to reduce the effects ofthe problem.
- the 231 MHz third LO 1936 falls close to the center ofthe received signal band width
- the third LO necessarily falls within the received signal band. This is undesirable from a design standpoint. This is because any spurious responses created by a third local oscillator signal fall within the received signal bandwidth.
- the present embodiment of this invention advantageously minimizes these undesirable effects.
- the present embodiments ofthe invention advantageously avoids the use of a PLL and the attendant VCO in producing the third LO signal 1930 at 231 MHz.
- a divide by 4 circuit 4802 utilizes two flip-flops that create the I and Q third LO signals 1930 from the 925 MHz second LO 1904. This simple direct synthesis of the third LO tends to produce a clean signal. The reduced generation of distortion within the signal band tends to be important in an integrated circuit design where all components are in close physical proximity.
- LC filter tuning 4812,4814,4816 in the embodiment is advantageously performed at startup ofthe chip.
- a "1,200 MHz filter tuning" circuit 4812 tunes the 1,200 MHz low pass filters 1912; a "275 MHz filter tuning” circuit 4814 tunes the 275 MHz low pass filter 1934; and a "44/36 MHz filter tuning” circuit 4816 alternatively tunes a final LC filter 1936 to one of two possible third IF frequencies (44 MHz or 36 MHz) depending upon the application.
- the filtering ofthe third IF frequencies is done by an external filter 4818. This external filter may have a saw device or other type of filter that provides satisfactory filtering ofthe third IF frequency.
- the filter tuning circuits 4812,4814,4816 utilize tuning signals based on the PLL2 signal 4806, with the "44/36 MHz filter tuning" circuit utilizing the PLL2 frequency divided by four 4802.
- the tuning signals selected may vary. Any or all of the PLLs 4804,4806,4802 or reference oscillator 4808 may be used to generate a filter tuning signal. Also a single frequency can be used to tune all filters with the appropriate frequency scaling applied.
- tuning the LC filters first the chip is turned on and PLL2 4806 must lock. PLL2 must first lock at 925 MHz as previously described.
- a VCO in the PLL 4806 is centered by adjusting its resonant circuit with tunable capacitors as previously described.
- a write signal is sent out to indicate that a stable reference for filter tuning is available.
- a stable 925 MHz reference for tuning is available the 1,200 MHz filter, the 275 MHz filter tuning previously described takes place.
- the filter tuning circuitry sends out a signal over an internal control bus structure, linking the receiver to a controller indicating that the tuning has finished.
- the receiver is now ready to select and tune a channel. Frequency tuning of received channels is accomplished in the embodiment with a coarse and fine PLL adjustment as previously described. The tuning is performed in such a way that there is always a third IF present at the output during the tuning process.
- PLL1 4804 is the coarse tuning PLL that tunes in 10 MHz steps.
- PLL24806 is the fine tuning PLL that tunes in 100 KHz steps. Exemplary tuning steps can be made as small as 25 KHz. A 100 kHz step is used for QAM modulation, and a 25 KHz step is used for NTSC modulation.
- each exemplary channel is separated by 6 MHz.
- PLL1 jumps in tuning steps of 10 MHz. Therefore, + or - 4 MHz is the maximum tuning error. If the filters used had a narrow band pass characteristic this tuning approach tends to become less desirable. For example, if the filter bandwidth was one channel, 6 MHz, wide and the first IF could be 1204 MHz or 1196 MHz. Thus, the selected channel would not be tuned.
- the bandwidth of the cascaded filters in the first IF strip is approximately 260 MHz.
- the bandwidth ofthe filters centered at 275 MHz in the second IF strip is approximately 50 MHz.
- the bandwidths are set to be several channels wide, a characteristic that advantageously takes advantage ofthe low Q in the LC filters built on the chip.
- the two PLLs guarantee that a third IF output is always obtained.
- the first PLL that tunes coarsely must tune from 1,250 to 2,060 MHz, a wide bandwidth.
- PLL2 the fine tuning PLL, must tune from + to - 4 MHz, which tends to be easier to implement.
- FIG. 51 shows a second exemplary embodiment ofthe invention. This embodiment is similar to the embodiment of FIG. 48, however it eliminates the first IR reject mixer (4802 of
- FIG. 48 The approximately 35 dB of image rejection that has been eliminated due to the removal ofthe IR reject mixer is made up by increased filter rejection provided by a 1 ,200 MHz LC filter bank 5101.
- the IR reject mixer is replaced with a conventional differential mixer 5104.
- the IO required is a single differential LO signal 5106 rather than the differential I and Q signals previously described.
- Better filters are used or alternatively an additional series of three 1,200 MHz LC filters 1912 for a total of six cascaded filters 5101 to provide sufficient image rejection are provided. This design provides the advantage of being simpler to implement on an integrated circuit.
- the third down conversion can be accomplished in a similar manner by eliminating the third I/Q mixer 4806 and increasing the selectivity ofthe 275 MHz filter bank 5102.
- the mixer 4806 is replaced with a conventional mixer requiring only a single differential third LO.
- FIG. 52 shows a third alternate embodiment of the invention that tends to provide continuous tuning of the filter over temperature, and tends to more accurately keeps the response curve of the filter centered on the desired frequency.
- This embodiment of the invention preserves the separation of I 5202 and Q 5204 signals through the second IF stage 5206.
- the I and Q signals are transformed into I', , Q, andQ signals.
- This alternate embodiment ofthe invention relies on a "three-stage poly phase" 5210 to provide image cancellation.
- the advantage of using a gyrator in place of dual LC filter bank 5212 is that a close relationship between I and Q tends to be maintained throughout the circuit. The phase relationship at the output ofthe gyrator filter tends to be very close to 90°.
- the gyrator circuit has the additional advantage of tending to improve the phase relationship of signals initially presented to it that are not exactly in quadrature phase. For example, an I signal that is initially presented to the gyrator that is 80° out of phase with its Q component has the phase relation continuously improved throughout the gyrator such that when the signals exit the gyrator quadrature phase of 90° tends to be established between the I and Q signals, such as in a polyphase circuit element.
- This present embodiment ofthe invention provides the additional benefit of being easily integrated onto a CMOS substrate since the gyrator eliminates the inductors that an LC filter would require. Filter timing and frequency generation utilize the methods previously described.
- FIG. 53 is a block diagram of an exemplary CATV tuner that inco ⁇ orates an embodiment of the present invention.
- the exemplary embodiments of the receiver are for terrestrial and cable television reception of signals from 50 to 860 MHz.
- Television signals in this exemplary band are frequency QAM or NTSC modulated signals.
- a receiver as described performs equally well in receiving digital or analog signals.
- the receiver architecture disclosed will function equally well regardless ofthe frequencies used, the type of transmission, or the type of signal being transmitted.
- the dynamic range of the devices used in the receiver may be adjusted accordingly.
- the receiver disclosed in the exemplary embodiments ofthe present invention tends to advantageously reduces interference problems created by this type of distortion.
- signals input to the receiver may range from +10 to +15 dB m .
- zero dB m 101og(lmV/lmV).
- This exemplary single up-conversion dual down conversion CATV tuner utilizes two PLLs that run off of a common 10 MHz crystal oscillator 5302. From the 10 MHz crystal oscillator references the PLLs generate two local oscillator signals that are used to mix down a received radio frequency to an intermediate frequency.
- This integrated CATV tuner advantageously uses differential signals throughout its architecture to achieve superior noise rejection and reduced phase noise.
- the receiver of the present invention advantageously provides channel selectivity and image rejection on the chip to minimize the noise injected into the received signal path.
- the differential configuration also tends to suppress noise generated on the CMOS substrate as well as external noise that is radiated into the differential leads ofthe 10 MHz crystal that connect it to the substrate.
- an external front end as previously described is supplied on a separate chip 5304 and an external filter 5306 is utilized.
- FIG.54 is a block diagram of a low power embodiment of the receiver that has been configured to receive cable telephony signals.
- These services among other cable services offered make use of RF receivers.
- a cable telephone receiver converts an RF signals present on the cable to a baseband signal suitable for processing to an audio, or other type of signal routed to a telephone system and a subscriber via two way transmission.
- When such services are widely offered, and are packaged into a common device, per unit cost and power dissipation tend to become concerns. It is desirable to provide a low cost and power efficient receiver.
- Receivers integrated onto a single chip that inco ⁇ orates filters on the chip reduce cost.
- an input signal is passed through an RF front end chip 5304 as previously described.
- the first frequency up conversion to the first IF 5402 is performed on the integrated receiver chip.
- the 1 ,270 to 2,080 MHz LO 5406 is generated on chip by a first PLL circuit, PLL 1 5408.
- the 1220 MHz differential signal is passed through buffer amplifiers 5410 and is applied to an off chip differential signal filter 5412, with a center frequency at 1,220 MHz having a characteristic impedance of 200 Ohms.
- the differential signal tends to provide the necessary noise rejection when routing the signal off and subsequently back onto the chip.
- the signal is routed back on to the integrated circuit 5404 where it is again passed through a send buffer amplifier 5414.
- the second frequency down conversion to the second IF 5416 is performed on the integrated receiver chip.
- An 1,176 MHz differential I and Q LO 5418 is generated on the integrated circuit by a second PLL, PLL2 5420 and polyphase 5422.
- the resulting second IF frequency 5616 is 44 MHz.
- the mixer used to generate the second IF is an I/Q type mixer 5424 that subsequently passes the signal through a polyphase circuit 5426.
- the second IF is then passed through a third buffer amplifier 5428.
- the signal is next routed off chip to a differential filter centered at 44 MHz 5430. After filtering the signal is returned to the integrated circuit where it undergoes amplification by a variable gain amplifier 5432.
- FIG. 55 shows a set top box 5502 used in receiving cable television (CATV) signals. These boxes typically inco ⁇ orate a receiver 5504 and a descrambling unit 5506 to allow the subscriber to receive premium programming. Additionally, on a pay for view basis subscribers can order programming through their set top boxes. This function additionally requires modulation circuitry and a radio frequency transmitter to transmit the signal over the CATV network 5508.
- CATV cable television
- Set top boxes can, depending on the nature of the network, provide other services as well. These devices include, IP telephones, digital set-top cards that fit into PCs, modems that hook up to PCs, Internet TVs, and video conferencing systems.
- the set-top box is the device that interfaces subscribers with the network and lets them execute the applications that reside on the network.
- Other devices in the home that may eventually connect with the network include IP telephones, digital set-top cards that fit into PCs, modems that hook up to PCs, Internet TVs, and video conferencing systems.
- set top boxes must provide a easy to use interface between the user and CATV provider.
- Memory 5510 and graphics driven by a CPU 5512 tend to make the application as appealing as possible to a user when interfaced with a set top box 5514.
- the set-top can receive data in Internet Protocol format and has an IP address assigned to it.
- satisfactory methods of handling reverse path communications are required to provide interactive digital services. All of these services utilize an operating system resident in the set top box 5502 for providing a user interface and communicating with the head end 5514 where the services are provided.
- the set top box is a convenient place to modulate the carrier for transmission, or to convert the modulated carrier to a base band signal for use at the user's location.
- a bidirectional signal from a cable head end 5514 is transmitted over a cable network that comprises cable and wireless data transmission.
- a signal 3406 is received an input to the subscriber ' s set top box 5502.
- the signal 3406 is input to a set top box transceiver 5504.
- the set top box transceiver 5504 comprises one or more receiver and transmitter circuits.
- the receiver circuits utilized are constmcted according to an embodiment of the invention. From the set top box transceiver, received data is passed to a decryption box 5506. If the television signal has been encrypted, this box performs a necessary descrambling operation on the signal .
- the signal After being passed through the decryption box, the signal next is presented to a set top box decoder 3416 where the signal is demodulated into audio and video outputs 3414.
- the set top box inco ⁇ orates a CPU 5512 with graphics capabilities and a memory 5510 to provide an interface and control the set top box through a data transfer stmcture 5514.
- An optional input output capability 5516 is provided for a direct user interface with the set top box.
- FIG. 56 is an illustration of the integrated television receiver 5602. This television could be one that processes digital or analog broadcast signals 5604.
- An exemplary integrated switchless attenuator and low noise amplifier 3408 is the first stage in a receiver contained in a television set. The integrated switchless attenuator and low noise amplifier is used as a "front end" ofthe receiver to adjust the amplitude ofthe incoming signal.
- Incoming television signals whether received from a cable or antenna vary widely in strength, from received channel to channel. Differences in signal strength are due to losses in the transmission path, distance from the transmitter, or head end, obstmctions in the signal path, among others.
- the front end adjusts the received signal level to an optimum value.
- a signal that is too strong produces distortion in the subsequent circuitry by over driving it into a non linear operating region.
- a signal that is too week will be lost in the noise floor when subsequent high noise figure circuitry is used in an attempt to boost the signal strength.
- automatic level control (5604) circuitry the integrated switchless attenuator and low noise amplifier responds to a generated feed back signal input to its control voltage terminal to adjust the input signal level to provide optimum performance.
- the RF signals 5604 are input to tuner 5620.
- This tuner circuit is as described in the previous embodiments where a single channel is selected from a variety of channels presented in the input signal 5604.
- An automatic fine tuning circuit (“AFT") 4622 is provided to adjust the level of the final IF signal 5624 being output to the television signal processing circuitry 5610.
- the signal processing circuitry splits the audio signal 5602 off of the final IF signal 5624 and outputs it to an audio output circuit such as an amplifier and then to a speaker 5618.
- the video signal split from IF signal 5624 is delivered via video signal 5606 to video processing circuitry 5612.
- analog or digital video signal is processed for application as control signals to the circuitry 5614 that controls the generation of an image on a display device 5626.
- a receiver would typically be contained in a television set. a set top box, a VCR, a cable modem, or any kind of tuner arrangement.
- FIG. 57 is a block diagram of a VCR that inco ⁇ orates an integrated receiver embodiment 5702 in its circuitry.
- VCRs are manufactured with connections that allow reception and conversion of a television broadcast signal 5704 to a video signal 5706.
- the broadcast signals are demodulated 5708 in the VCR and recorded 5710 on a recording media such as a tape, or output as a video signal directly.
- VCRs are a commodity item. Cost pressures require economical high performance circuitry for these units to provide additional more features as the prices decline in the marketplace.
- FIG. 58 shows a block diagram of a typical cable modem.
- a "Cable Modem” is a device that allows high speed data connection (such as to the Internet) via a cable TV (CATV) network 5812.
- a cable modem commonly has two connections, one to the cable TV wall outlet 5802 and the other to a computer 5804.
- the coax cable 5808 connects to the cable modem 5806, which in turn connects to an Ethernet card 5814 in a PC.
- the function of the cable modem is to connect broadband (i.e., the cable television network) to Ethernet. Once the Ethernet card has been installed, the TCP/IP software is typically used to manage the connection.
- On-line access through cable modems allows PC users to download information at a speeds approximately 1,000 times faster than with telephone modems.
- Cable modem speeds range from 500Kbps to 10Mbps.
- a cable modem sends and receives data in two slightly different, or asynchronous fashions.
- Data transmitted downstream, to the user, is digital data modulated onto a typical 6 MHz channel on a television carrier, between 42 MHz and 750 MHz.
- Two possible modulation techniques are QPSK (allowing data transmission of up to 10 Mbps) and QAM64 (allowing data transmission of up to 36 Mbps).
- the data signal can be placed in a 6MHz channel adjacent to an existing TV signals without disturbing the cable television video signals.
- the upstream channel to the ISP provider is transmitted at a rate between 5 and 40 MHz.
- Cable modems can be configured to inco ⁇ orate many desirable features in addition to high speed. Cable modems can be configured to include, but are not limited to, a modem, a tuner 5816, an encryption/decryption device, a bridge, a router, a NIC card, SNMP agent, and an Ethernet hub.
- RF radio frequency
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Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99965786A EP1145430B1 (en) | 1998-11-12 | 1999-11-12 | Integrated tuner architecture |
AT99965786T ATE276605T1 (en) | 1998-11-12 | 1999-11-12 | INTEGRATED TUNER ARCHITECTURE |
AU21479/00A AU2147900A (en) | 1998-11-12 | 1999-11-12 | Fully integrated tuner architecture |
DE69920273T DE69920273T2 (en) | 1998-11-12 | 1999-11-12 | INTEGRATED TUNER ARCHITECTURE |
Applications Claiming Priority (16)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10845998P | 1998-11-12 | 1998-11-12 | |
US10821098P | 1998-11-12 | 1998-11-12 | |
US10820998P | 1998-11-12 | 1998-11-12 | |
US60/108,210 | 1998-11-12 | ||
US60/108,209 | 1998-11-12 | ||
US60/108,459 | 1998-11-12 | ||
US11760999P | 1999-01-28 | 1999-01-28 | |
US60/117,609 | 1999-01-28 | ||
US13611699P | 1999-05-26 | 1999-05-26 | |
US13611599P | 1999-05-26 | 1999-05-26 | |
US60/136,115 | 1999-05-26 | ||
US60/136,116 | 1999-05-26 | ||
US13665499P | 1999-05-27 | 1999-05-27 | |
US60/136,654 | 1999-05-27 | ||
US15972699P | 1999-10-15 | 1999-10-15 | |
US60/159,726 | 1999-10-15 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2000028664A2 true WO2000028664A2 (en) | 2000-05-18 |
WO2000028664A8 WO2000028664A8 (en) | 2001-02-15 |
WO2000028664A3 WO2000028664A3 (en) | 2001-07-26 |
Family
ID=27574786
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/026700 WO2000028664A2 (en) | 1998-11-12 | 1999-11-12 | Fully integrated tuner architecture |
Country Status (6)
Country | Link |
---|---|
US (20) | US6879816B2 (en) |
EP (1) | EP1145430B1 (en) |
AT (1) | ATE276605T1 (en) |
AU (1) | AU2147900A (en) |
DE (1) | DE69920273T2 (en) |
WO (1) | WO2000028664A2 (en) |
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