US20060096781A1 - Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same - Google Patents
Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same Download PDFInfo
- Publication number
- US20060096781A1 US20060096781A1 US11/247,813 US24781305A US2006096781A1 US 20060096781 A1 US20060096781 A1 US 20060096781A1 US 24781305 A US24781305 A US 24781305A US 2006096781 A1 US2006096781 A1 US 2006096781A1
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- United States
- Prior art keywords
- layer
- hole
- protrusion
- substrate
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- 230000000149 penetrating effect Effects 0.000 title claims abstract description 124
- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 229910052751 metal Inorganic materials 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 64
- 238000009792 diffusion process Methods 0.000 claims description 49
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 34
- 239000011888 foil Substances 0.000 claims description 29
- 239000000853 adhesive Substances 0.000 claims description 15
- 230000001070 adhesive effect Effects 0.000 claims description 15
- 229910052763 palladium Inorganic materials 0.000 claims description 15
- 238000009713 electroplating Methods 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 238000007669 thermal treatment Methods 0.000 claims description 9
- 239000002245 particle Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 229910000679 solder Inorganic materials 0.000 description 13
- 238000007772 electroless plating Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 238000011161 development Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 230000004913 activation Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000002679 ablation Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-L Sulfate Chemical compound [O-]S([O-])(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-L 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H01L2924/01078—Platinum [Pt]
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0236—Plating catalyst as filler in insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09581—Applying an insulating coating on the walls of holes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10378—Interposers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1377—Protective layers
- H05K2203/1383—Temporary protective insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Definitions
- the present invention generally relates to a substrate and a method for manufacturing the same and, more particularly, a substrate having a penetrating via penetrating a base member, wiring connected to the penetrating via, and a method for manufacturing the same.
- MEMS Micro Electro Mechanical Systems
- substrates such as interposers mounting a semiconductor device therein.
- the above described substrate includes wirings formed on both sides of the substrate and penetrating vias penetrating the substrate and electrically connecting the wirings formed on both sides of the substrate.
- FIG. 1 is a diagram showing a conventional substrate.
- a substrate 10 is composed of a silicon member 11 , an insulating layer 13 , penetrating vias 15 , wirings 17 , solder resists 19 and 24 , and wirings 21 .
- through-holes 12 are formed in the silicon member 11 .
- the insulating layer 13 is formed on the surface of the silicon member 11 wherein a through-hole 12 is formed.
- the insulating layer 13 is provided for insulating the silicon member 11 from the penetrating via 15 , the wiring 17 , and the wiring 21 .
- the penetrating via 15 which is cylindrical in shape is provided in the through-hole 12 where the insulating layer 13 is formed.
- an edge part 15 a of the penetrating via 15 and a surface 13 a of the insulating layer 13 are to be even, and another edge part 15 b of the penetrating via 15 and another surface 13 b of the insulating layer 13 are to be even.
- the above described penetrating via 15 is formed by the steps of forming a seed layer by a spattering method on the silicon member 11 where the insulating layer 13 is formed, and separating out a conductive metal layer such as Cu on the seed layer by the electrolytic plating method and growing the metal layer (See Patent Document 1 , for example).
- the wiring 17 having an external connection terminal 18 is provided on the upper surface of the silicon member 11 so as to be connected to the edge part 15 a of the penetrating via 15 .
- MEMS and a semiconductor device 25 are mounted on the external connection terminal 18 .
- Solder resist 19 exposing the external connection terminal 18 is provided on the upper surface of the silicon member 11 so as to cover the wiring 17 except the external connection terminal 18 .
- the wiring 21 having an external connection terminal 22 is provided on the undersurface of the silicon member 11 so as to be connected to the other edge part 15 b of the penetrating via 15 .
- the external connection terminal 22 is provided for being connected to another substrate such as a motherboard.
- Solder resist 24 exposing the external connection terminal 22 is provided on the undersurface of the silicon member 11 so as to cover the wiring 21 except the external connection terminal 22 .
- Patent Document 1 Japanese Patent Application Laid-Open Disclosure No.1-258457
- the shape of the conventional penetrating via 15 is cylindrical. However, water infiltrates into a gap between the edge part 15 a of the penetrating via 15 and the insulating layer 13 , and a gap between the other edge part 15 b and the insulating layer 13 , and thereby, the penetrating via 15 becomes degraded and the electrical connection reliability of the penetrating via 15 connecting the wirings 17 and 21 is also degraded.
- the separated conductive metal layer on the surface of the seed layer is formed on the inside edges of the through-hole 12 and the conductive metal layer is grown along the inside edges of the through-hole 12 , and thus, a void (cavity) forms near the center of the penetrating via 15 . Therefore, the electrical connection reliability of the penetrating via 15 connected to the wirings 17 and 21 is degraded.
- a substrate which includes a base member having a through-hole, a penetrating via provided in the through-hole, and a first wiring and a second wiring connected to the penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole, the penetrating part having a first end and a second end, a first protrusion protruding from the base member, the first protrusion being connected to the first end of the penetrating part so as to be connected to the first wiring, and a second protrusion protruding from the base member, the second protrusion being connected to the second end of the penetrating part so as to be connected to the second wiring, wherein the first protrusion and second protrusion are wider than a diameter of the through-hole.
- the first protrusion and the second protrusion being wider than the diameter of the through-hole are connected to the penetrating via so as to prevent water from infiltrating the gap between the penetrating part and the base member, and thereby, the penetrating via is prevented from being degraded; thus, the electric connection reliability of the penetrating via connected to the wiring can be improved.
- a substrate which includes a base member having a through-hole, a penetrating via provided in the through-hole, and a first wiring and a second wiring connected to the penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole having a first end and a second end, and a protrusion to be connected to the first wiring, being connected to the first end of the penetrating part and another protrusion to be connected to the second wiring, being connected to the second end of the penetrating part, wherein the protrusion is wider than the diameter of the through-hole.
- a protrusion being wider than the diameter of the through-hole is connected to each end of the penetrating part so as to prevent water from infiltrating the gap between the penetrating part and the base member, and thereby, the penetrating via is prevented from being degraded; thus the electric connection reliability of the penetrating via connected to the wiring can be improved.
- a method for manufacturing a substrate which is composed of a base member having a through-hole, a penetrating via formed in the through-hole in the base member, and wiring connected to an end of the penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole, having a first end and a second end, a first protrusion protruding from the base member, being connected to the first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, being connected to the second end of the penetrating part, wherein the first protrusion and second protrusion are wider than the diameter of the through-hole is provided.
- the method for manufacturing the substrate further includes the steps of forming the penetrating via, and forming wiring so as to be connected to the first protrusion.
- the first protrusion and the second protrusion both wider than the diameter of the through-hole are connected to the penetrating via so as to prevent water from infiltrating the gap between the penetrating part and the base member, and thereby, the penetrating via is prevented from being degraded; thus, the electric connection reliability of the penetrating via connected to the wiring can be improved.
- FIG. 1 is a diagram showing a substrate of the prior art
- FIG. 2 is a cross-sectional diagram of the substrate according to a first embodiment of the present invention.
- FIG. 3 is a plan view of a base member for manufacturing the substrate according to the present embodiment
- FIGS. 4 through 29 are diagrams showing the manufacturing steps of the substrate according to the first embodiment.
- FIGS. 30 through 36 are diagrams showing the other manufacturing steps of the substrate.
- FIG. 2 is a cross-sectional diagram of the substrate according to the first embodiment of the present invention.
- the substrate 50 is composed of a base member 51 , an insulating layer 53 , penetrating vias 54 , an insulating layer 65 , wirings 68 , first diffusion protecting layers 61 , second diffusion protecting layers 71 , and solder resist 75 .
- the substrate 50 is an interposer. As shown in FIG.
- MEMS Micro Electro Mechanical Systems
- a semiconductor device mounted on the undersurface of the substrate 50 , for example, MEMS (Micro Electro Mechanical Systems) wherein fine processing technology of the semiconductor is used and a semiconductor device are mounted, while on the upper side of the substrate 50 , for example, another substrate such as a motherboard is connected.
- the base member 51 is a silicon member which is composed of silicon.
- the thickness Ml of the base member 51 is, for example, 150 ⁇ m.
- plural of through-holes 52 for disposing the penetrating vias 54 are provided so as to penetrate the base member 51 .
- the through-hole 52 having a diameter R 1 of the aperture is formed.
- the insulating layer 53 is provided on the surface of the base member 51 including the through-holes 52 . Accordingly, by providing the insulating layer 53 on the surface of the base member 51 including the through-holes 52 , the base member 51 is insulated from the penetrating via 54 .
- materials such as a glass material except silicon can be used as the base member 51 . In addition to this, when materials having an insulating property such as a glass material are used, it is not necessary to provide the insulating layer 53 .
- the penetrating via 54 is composed of a penetrating part 55 , wirings connecting part 56 as a first protrusion, and a connection pad 57 as a second protrusion.
- the penetrating part 55 is provided in the through-hole 52 on which the insulating layer 53 is formed, and the diameter is predetermined to be R 1 (hereinafter, the diameter is referred to as “Diameter R 1 ”).
- the size of the penetrating part 55 is Diameter R 1 .
- the wirings connecting part 56 is provided on the upper edge of the penetrating part 55 .
- the wirings connecting part 56 protrudes from a side 51 a of the base member 51 , and the size of the wirings connecting part 56 is wider than Diameter R 1 of the penetrating part 55 .
- the width W 1 of the wirings connecting part 56 is set larger than R 1 of the penetrating part 55 (W 1 >R 1 ).
- the wirings connecting part 56 is unified with the penetrating part 55 .
- the wirings connecting part 56 is provided for connecting a wiring 68 .
- connection pad 57 is provided on the undersurface of the penetrating part 55 .
- the connection pad 57 protrudes from a side 51 b of the base member 51 , and the size of the connection pad 57 is wider than Diameter R 1 of the penetrating part 55 .
- the width W 2 of the connection pad 57 is set larger than Diameter R 1 of the penetrating part 55 (W 2 >R 1 ).
- the connection pad 57 is provided for connecting devices such as a semiconductor device.
- the penetrating part 55 , wirings connecting part 56 , and connection pad 57 are unified by a conductive metal layer.
- the conductive metal layer for example, a Cu layer can be used.
- the first diffusion protecting layer 61 is provided on the connection pad 57 .
- the first diffusion protecting layer 61 is formed for improving wettability of solder and protecting Cu contained in the penetrating via 54 from diffusing into the solder (drawing is omitted) connected to the connection pad 57 .
- the first diffusion protecting layer 61 comprises, for example, a lamination layer which is composed of a Ni layer 62 and an Au layer 63 .
- the thickness of the Ni layer 62 is, for example, 2 through 5 ⁇ m and the thickness of the Au layer 63 is, for example, 0.1 through 0.5 ⁇ m.
- a Ni/Pd layer and a Ni/Pd/Au layer can be used as the first diffusion protecting layer 61 (the Ni layer being the connected to the connection pad 57 ).
- the insulating layer 65 having an open part exposing the wirings connecting part 56 is formed on the surface 51 a of the base member 51 .
- resin can be used where one of metal particles functioning as a catalyst for plating and particles of metal compound (chloride, hydroxide, oxide and others) is dispersed.
- metal compound chloride, hydroxide, oxide and others
- the resin for example, epoxy resin and polyimide resin can be used.
- the metal functioning as a catalyst palladium and platinum can be used, especially, platinum is desirable.
- the metal compound for example, palladium chloride and palladium sulfate can be used.
- epoxy resin where palladium particles are dispersed is used for the insulating layer 65 .
- the thickness M 2 of the insulating layer 65 is, for example, 5 ⁇ m.
- the wiring 68 is provided on the insulating layer 65 so as to be connected to the wirings connecting part 56 .
- the wiring 68 having an external connection terminal 69 is composed of a conductive metal layer 67 and a seed layer 66 .
- the external connection terminal 69 is provided for being connected to a substrate such as a motherboard. By providing this external connection terminal 69 , the position of the external connection terminal 69 can be set corresponding to the position of the external connection terminal of the substrate like a motherboard.
- the conductive metal layer 67 for example, a Cu layer can be used. When a Cu layer is used for the conductive metal layer 67 , the thickness M 3 of the conductive metal layer 67 is, for example, 3 through 10 ⁇ m.
- the seed layer 66 for example, a Ni layer can be used. The thickness of the seed layer 66 is, for example, 0.1 ⁇ m.
- the solder resist 75 having an open part 76 exposing the external connection terminal 69 is provided so as to cover the wiring 68 and insulating layer 65 except the external connection terminal 69 .
- the solder resist 75 is provided for protecting the wiring 68 .
- the second diffusion protecting layer 71 is provided on the external connection terminal 69 .
- the second diffusion protecting layer 71 is formed for improving wettability of solder and protecting Cu contained in the wiring 68 from diffusing into the solder (drawing is omitted) connected to the external connection terminal 69 .
- the second diffusion protecting layer 71 comprises, for example, a lamination layer which is composed of a Ni layer 72 and an Au layer 73 .
- the thickness of the Ni layer 72 is, for example, 2 through 5 ⁇ m and the thickness of the Au layer 73 is, for example, 0.1 through 0.5 ⁇ m.
- Ni/Au layer for example, a Ni/Pd layer and a Ni/Pd/Au layer can be used as the second diffusion protecting layer 71 (the Ni layer must be connected to the external connection terminal 69 ).
- FIG. 3 is a plan view of a base member 51 for manufacturing the substrate 50 according to the present embodiment.
- “A” shown in FIG. 3 is an area where the substrate 50 is formed (hereinafter, “A” is referred to as “Substrate Forming Area A”).
- a silicon base member silicon wafer
- the base member 51 is cut into a plurality of pieces, and thus, plural of the substrates 50 are manufactured all at once. Accordingly, the productivity of manufacturing the substrate 50 is improved.
- FIGS. 4 through 29 are diagrams showing the manufacturing steps of the substrate 50 according to the first embodiment. It should be noted that an example is given where a silicon member is used as the base member 51 .
- an adhesive 92 is provided on a support board 91 .
- the support board 91 is provided for supporting the base member 51 .
- a glass member and a silicon member (specifically a silicon wafer) can be used.
- the thickness M 4 of the support board 91 is, for example, 725 ⁇ m.
- the adhesive 92 is provided on the support board 91 for bonding a metal foil 93 which is described below.
- a thermo peal tape and a thermal ablation adhesive can be used which lose adhesion when being heated.
- a metal foil 93 such as a Cu layer is bonded to the support board 91 via the adhesive 92 (the metal foil providing step).
- a first resist layer 94 which is not in the exposure state is formed on the metal foil 93 (the first resist layer forming step).
- a photosensitive dry film resist and a liquid resist can be used for the first resist layer 94 which is a resist having adhesion.
- the base member 51 having through-holes 52 can be fixed on the support board 91 via the first resist layer 94 (as shown in FIG. 7 ).
- the thickness of the first resist layer is, for example, 10 through 15 ⁇ m.
- another adhesive such as epoxy and polyimide can be used if the adhesive can be dissolved by some treatment liquid.
- the through-hole 52 can be formed by, for example, one of drill processing, laser processing, and anisotropic etching.
- the diameter R 2 of the through-hole 52 can be selected properly from the range of, for example, 10 through 60 ⁇ m.
- the insulating layer 53 for example, an oxide layer (SiO 2 ) formed by a CVD method and a thermal oxide layer (SiO 2 ) formed by an oxidizing furnace can be used. Furthermore, the thickness M 1 of the base member 51 is, for example, 150 ⁇ m.
- a developer is supplied to the inside of the through-hole 52 , and then, the developer dissolves the first resist layer 94 exposed by the through-hole 52 so as to form a space 97 (the space forming step).
- the space 97 is wider than the diameter R 2 of the through-hole 52 , and the width W 2 of the space 97 is larger than the diameter R 2 of the through-hole 52 (W 2 >R 2 ).
- a method for supplying the developer into the through-hole 52 for example, a dip development method where a structure shown in FIG. 7 is dipped into the developer and a spray development method where the developer is sprayed like a shower on the through-hole 52 are applied.
- the space can be formed.
- a pressure of spraying the developer is 2.0 kgf/cm 2
- a temperature is 25 through 30° C.
- a developer spraying time is 6 min.
- a size of a through-hole is the diameter R 2 of the through-hole 52 .
- a through-hole 52 is exposed on the insulating layer 53 formed on the surface 51 a of the base member 51 , and a second resist layer 101 having an open part 102 wider than the diameter R 2 of the through-hole 52 is formed (the second resist layer forming step).
- the diameter W 1 of the first open part, i.e. the open part 102 is formed larger than the diameter R 2 of the through-hole 52 (W 1 >R 2 ).
- the metal foil 93 as a power supply layer, an Au layer 63 and a Ni layer 62 are separated out in turn on the metal foil 93 according to the electrolytic plating method and grown, and thus the first diffusion protecting layer 61 is formed (the first diffusion protecting layer forming step).
- the thickness of the Au layer 63 is, for example, 0.1 through 0.5 ⁇ m, and the thickness of the Ni layer 62 is, for example, 2 through 5 ⁇ m. Accordingly, the first diffusion protecting layer 61 is formed by the electrolytic plating method; thus the diffusion protecting layer having a layer superior to the layer formed by the electroless plating method can be obtained.
- a conductive metal layer 104 is separated out and grown so as to fill the space 97 , through-hole 52 and open part 102 (the conductive metal layer forming step).
- the conductive metal layer 104 protrudes from the surface 101 a of the second resist layer 101 .
- a Cu layer can be used as the conductive metal layer 104 .
- the conductive metal layer 104 protruding from the surface 101 a of the second resist layer 101 is ground to be removed so that the conductive metal layer 104 and the surface 101 a of the second resist layer 101 become flat. Accordingly, the following components are formed all at once: the connection pad 57 having the width W 2 in the space 97 , the penetrating part 55 having the diameter R 1 in the through-hole 52 , and the wirings connecting part 56 (the first protrusion) having the width W 1 in the open part 102 . And thus, the penetrating via 54 is formed. The widths W 1 and W 2 are wider than the diameter R 1 of the penetrating part 55 .
- connection pad 57 and wirings connecting part 56 are formed wider than the diameter R 1 of the penetrating part 55 in the penetrating via 54 , water is prevented from infiltrating the gap between the penetrating part 55 and the base member 51 , and the degradation of the penetrating via 54 is controlled. Therefore, the electric connection reliability of the penetrating via 54 connected to the wiring 68 is improved.
- the metal foil 93 is used as a power supply layer, the conductive metal layer 104 is separated and grown on the metal foil 93 so as to fill the space 97 , through-hole 52 and the first open part 102 , and thus a void (cavity) is prevented from forming in the penetrating via 54 .
- the second resist layer 101 is removed by a resist stripper (the second resist layer removing step).
- an insulating layer 65 having an open part 103 exposing the wirings connecting part 56 is provided on the surface 51 a of the base member 51 (the insulating layer forming step).
- an epoxy resin containing palladium particles therein is used for the insulating layer 65 .
- the thickness M 2 of the insulating layer 65 is, for example, 5 ⁇ m.
- a seed layer 66 is formed on the upper surface 65 a and the lateral surface 65 b of the insulating layer 65 by the electroless plating method (the seed layer forming step).
- a desmear treatment is performed on the surface of the resin (insulating layer) and roughed in advance, and then a palladium activation treatment is performed on the surface of the resin.
- the palladium activation treatment is dipping a sample to be plated in either a catalyzing treatment solution or an accelerating treatment solution, and then separating out the palladium which will be a core to be plated by the electroless plating method on the surface of the resin.
- a plated layer can not be formed by the electroless plating method until the palladium activation treatment is performed. Therefore, according to the conventional technology, the steps are very troublesome.
- an epoxy resin containing the palladium particles therein is applied to the insulating layer, so that the seed layer 66 can be formed directly on the insulating layer by the electroless plating method without performing the desmear treatment and palladium activation treatment in advance. Accordingly, the manufacturing steps of the substrate 50 can be simplified.
- the seed layer 66 for example, a Ni layer can be used.
- resin containing palladium particles therein is used for the insulating layer 65 , a Ni—B layer can be formed.
- a dry film resist 105 having an open part 106 corresponding to the area where the wiring 68 is provided is formed on the seed layer 66 .
- the thickness of the dry film resist 105 is, for example, 10 through 15 ⁇ m.
- a conductive metal layer 67 is separated out on open parts 103 and 106 by the electrolytic plating method.
- the conductive metal layer 67 and the penetrating via 54 are electrically connected.
- the dry film resist 105 is removed by the resist stripper.
- a dry film resist 111 is formed exposing the conductive metal layer 67 corresponding to the area B where an external connection terminal 69 is to be formed.
- Open parts 112 are formed in the dry film resist 111 , and the conductive metal layer 67 corresponding to the area B is exposed from the open part 112 .
- a Ni layer 72 and an Au layer 73 are separated out in turn and grown on the conductive metal layer 67 exposed from the open part 112 so as to form a second diffusion protecting layer 71 (the second diffusion protecting layer forming step).
- the thickness of the Ni layer 72 is, for example, 2 through 5 ⁇ m
- the thickness of the Au layer 73 is, for example, 0.1 through 0.5 ⁇ m. Accordingly, the second diffusion protecting layer 71 is formed by the electrolytic plating method, thus the second diffusion protecting layer 71 having a layer superior to the layer formed by the electroless plating method can be obtained.
- the dry film resist 111 is removed after the second diffusion protecting layer 71 is formed.
- a dry film resist layer 114 is formed so as to cover only the conductive metal layer 67 and the second diffusion protecting layer 71 .
- the seed layer 66 formed on the insulating layer 65 is removed by etching. Accordingly, the external connection terminal 69 is provided and the wiring 68 including the seed layer 66 and conductive metal layer 67 is formed.
- the dry film resist 114 is removed by the resist stripper.
- a heat-resistant protective member i.e. a temperature-resistant tape 116 is attached so as to cover the wiring 68 , second diffusion protecting layer 71 and an upper surface 65 a of the insulating layer 65 (the protective member disposing step).
- the temperature-resistant tape 116 is a tape having a resistance against the etchant. Accordingly, the wiring 68 and the second diffusion protecting layer 71 are covered by the temperature-resistant tape 116 so as to protect the wiring 68 and the second diffusion protecting layer 71 from the heat generated in a second thermal treatment (as shown in FIG. 25 ) performed in removing the support board 91 from the base member 51 .
- a PET and a PEN which are flame retardant can be used. It should be noted that the temperature-resistant tape 116 is provided so as to cover at least the wiring 68 and second diffusion protecting layer 71 .
- the structure shown in FIG. 24 is heated (the second thermal treatment) and the adhesive 92 and support board 91 are removed from the base member 51 (the support board removing step).
- a thermo peal tape which loses adhesion when being heated is used as the adhesive 92 .
- the conditions of the second thermal treatment are, for example, a heating temperature of 150° C. and a heating time of 30 min.
- the metal foil 93 is removed by etching (the metal foil removing step). Accordingly, the first resist layer 94 and the first diffusion protecting layer 61 are exposed.
- the wiring 68 is covered by the temperature-resistant tape 116 having a resistance against the etchant, and thereby, the wiring 68 is not etched.
- the first resist layer 94 is removed by the ablation liquid.
- the temperature-resistant tape 116 is removed.
- solder resist 75 is provided so as to expose the second diffusion protecting layer 71 and cover the wiring 68 and insulating layer 65 .
- the solder resist 75 has open parts 76 exposing the second diffusion protecting layer 71 .
- the base member 51 is diced into a plurality of the substrates 50 as shown in FIG. 2 .
- the penetrating via 54 is formed including the wiring connection part 56 which is formed on one edge of the penetrating part 55 and the wiring connection part 56 is wider than the diameter R 1 of the penetrating part 55 , and the connection pad 57 which is formed on the other edge of the penetrating part 55 and has a shape wider than the diameter R 1 of the penetrating part 55 . Accordingly, water is prevented from infiltrating a gap between the penetrating part 55 and the base member 51 , and degradation of the penetrating via 54 is controlled; therefore, the electric connection reliability of the penetrating via 54 connected to the wiring 68 is improved. Moreover, the wiring 68 is connected to the wirings connecting part 56 having a shape wider than the diameter R 1 of the penetrating part 55 , and thus, the wirings connecting part 56 is easily connected to the wiring 68 .
- a diffusion protecting layer is formed on the connecting part 56 by electrolytic plating method without forming the above described layers such as a conductive metal layer. Then, the support board 91 , the adhesive 92 , the metal foil 93 , and the first resist layer 94 are removed so as to obtain a substrate having only the penetrating via 54 .
- This substrate can also be applied to the present invention.
- FIGS. 30 through 36 are diagrams showing the other method's manufacturing steps of the substrate 50 .
- the adhesive 92 is provided on the support board 91 and the metal foil 93 such as Cu is attached on the adhesive 92 (the metal foil disposing step). Then, a dry film resist 118 having an open part 119 is provided on the metal foil 93 . The open part 119 exposes the metal foil 93 .
- a first resist layer 121 which is not in the exposure state is provided on the metal foil 93 so as to cover the first diffusion protecting layer 61 (the first resist layer forming step).
- the first resist layer 121 which is a resist having adhesion for example, photosensitive dry film resist can be used.
- the thickness of the first resist layer 121 is, for example, 10 ⁇ m through 15 ⁇ m.
- a through-hole 52 having a diameter R 2 is formed and a base member 51 where an insulating layer 53 is formed so as to cover a surface of the base member 51 (including the base member part corresponding to the through-hole 52 ) is disposed on the first resist layer 121 having adhesion and fixed on the first resist layer 121 (the base member disposing step).
- the developer is supplied into the through-hole 52 , and the developer dissolves the first resist layer 121 exposed on the through-hole 52 so as to form a space 123 (the space forming step).
- the space 123 is a space wider than the diameter R 2 of the through-hole 52 , and the width W 3 of the space 123 is larger than the diameter R 2 of the through-hole 52 (W 3 >R 2 ).
- the space 123 is exposed from the Ni layer 62 .
- the dip development and the spray development described in the first embodiment can be applied.
- the through-hole 52 is exposed on the insulating layer 53 formed on the surface 51 a of the base member 51 , and the second resist layer 101 having an open part 102 wider than the diameter R 2 of the through-hole 52 is formed (the second resist layer forming step).
- the width W 1 of the open part 102 which is the first open part is larger than the diameter R 2 of the through-hole 52 (W 1 >R 2 ).
- the substrate 50 can be manufactured by steps similar to those in FIGS. 11 through 29 .
- the plating solution used to form Ni layer 63 is prevented from being mixed with the plating solution used to form a conductive metal layer 104 . Therefore, the conductive metal layer 104 having an excellent layer can be formed.
- the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention.
- the wiring 68 is formed on only the upper surface 51 a of the base member 51 , but a wiring (including an external connection terminal) connected to the connection pad 57 can also be provided according to the similar manufacturing step shown in FIGS. 14 through 23 .
- the wirings are disposed on both sides 51 a and 51 b of the base member 51 so as to connect various substrates such as a motherboard, semiconductor device, and MEMS. Therefore, the scope of the application of the substrate can be expanded and the electrical connection reliability between the wirings formed on both sides of the base member 51 can be improved.
- the present invention can be applied to a substrate improving the electrical connection reliability of the penetrating via connecting the wiring and a method for manufacturing the same.
- a diffusion protecting layer is provided on the external connection terminal and on the second protrusion, and when the wiring and the penetrating via contain Cu therein, the Cu contained in the external connection terminal and in the second protrusion is protected from diffusing by the diffusion protecting layer.
- the conductive metal layer is separated on the metal foil and grown according to the electrolytic plating method; the space, the through-hole, and the first open part are filled in turn with the conductive metal layer to be a penetrating via, and thereby, a void (cavity) is prevented from forming in the penetrating via.
- the first resist layer is hardened according to the first thermal treatment so as to give the first resist layer tolerance against the etchant.
- a first diffusion protecting layer is formed according to the electrolytic plating method, and thereby, the diffusion protecting layer having a layer superior to the layer formed according to an electroless plating method can be obtained.
- the resin layer containing the palladium particles therein is used for the insulating layer, when the seed layer is formed on the insulating layer, it is not necessary to perform a treatment in advance on the insulating layer. Therefore, the steps of manufacturing the substrate can be simplified.
- the second diffusion protecting layer is formed according to the electrolytic plating method, and thereby, the diffusion protecting layer having a layer superior to the layer formed according to the electroless plating method can be obtained.
- the heat-resistant protecting member is provided so as to cover at least the wiring and the second diffusion protecting layer, and thereby, the wiring and the second diffusion protecting layer are protected from the heat generated in the second thermal treatment performed for removing the adhesive and the support board from the base member.
- the method for manufacturing the substrate includes the steps of removing the metal foil by etching after the step of removing the support board, removing the first resist layer, and removing the protecting member after the step of removing the first resist layer.
- the protecting member is removed after the step of removing the metal foil so as to protect the wiring from being etched.
- the step of forming the first diffusion protecting layer is performed immediately after the step of disposing the metal foil; thus a plating solution used for forming the first diffusion protecting layer is prevented from being mixed with another plating solution used for forming the penetrating via, and thereby, the conductive metal layer having an excellent layer can be formed.
- a substrate wherein the electric connection reliability of the penetrating via connected to the wirings is improved and a method for manufacturing the same can be provided.
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Abstract
A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.
Description
- 1. Field of the Invention
- The present invention generally relates to a substrate and a method for manufacturing the same and, more particularly, a substrate having a penetrating via penetrating a base member, wiring connected to the penetrating via, and a method for manufacturing the same.
- 2. Description of the Related Art
- In these years, by using fine processing technology of a semiconductor, packages called MEMS (Micro Electro Mechanical Systems) for micro machines and substrates such as interposers mounting a semiconductor device therein, are developed. The above described substrate includes wirings formed on both sides of the substrate and penetrating vias penetrating the substrate and electrically connecting the wirings formed on both sides of the substrate.
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FIG. 1 is a diagram showing a conventional substrate. As shown inFIG. 1 , asubstrate 10 is composed of asilicon member 11, aninsulating layer 13, penetratingvias 15,wirings 17, solder resists 19 and 24, andwirings 21. In thesilicon member 11, through-holes 12 are formed. The insulatinglayer 13 is formed on the surface of thesilicon member 11 wherein a through-hole 12 is formed. Theinsulating layer 13 is provided for insulating thesilicon member 11 from the penetrating via 15, thewiring 17, and thewiring 21. The penetrating via 15 which is cylindrical in shape is provided in the through-hole 12 where theinsulating layer 13 is formed. Moreover, anedge part 15 a of the penetrating via 15 and asurface 13 a of theinsulating layer 13 are to be even, and anotheredge part 15 b of the penetrating via 15 and anothersurface 13 b of theinsulating layer 13 are to be even. The above described penetrating via 15 is formed by the steps of forming a seed layer by a spattering method on thesilicon member 11 where theinsulating layer 13 is formed, and separating out a conductive metal layer such as Cu on the seed layer by the electrolytic plating method and growing the metal layer (SeePatent Document 1, for example). - The
wiring 17 having anexternal connection terminal 18 is provided on the upper surface of thesilicon member 11 so as to be connected to theedge part 15 a of the penetrating via 15. MEMS and asemiconductor device 25 are mounted on theexternal connection terminal 18. Solder resist 19 exposing theexternal connection terminal 18 is provided on the upper surface of thesilicon member 11 so as to cover thewiring 17 except theexternal connection terminal 18. - The
wiring 21 having anexternal connection terminal 22 is provided on the undersurface of thesilicon member 11 so as to be connected to theother edge part 15 b of the penetrating via 15. Theexternal connection terminal 22 is provided for being connected to another substrate such as a motherboard. Solder resist 24 exposing theexternal connection terminal 22 is provided on the undersurface of thesilicon member 11 so as to cover thewiring 21 except theexternal connection terminal 22. - [Patent Document 1] Japanese Patent Application Laid-Open Disclosure No.1-258457
- The shape of the conventional penetrating via 15 is cylindrical. However, water infiltrates into a gap between the
edge part 15 a of the penetrating via 15 and theinsulating layer 13, and a gap between theother edge part 15 b and theinsulating layer 13, and thereby, the penetrating via 15 becomes degraded and the electrical connection reliability of the penetrating via 15 connecting thewirings hole 12 and the conductive metal layer is grown along the inside edges of the through-hole 12, and thus, a void (cavity) forms near the center of the penetrating via 15. Therefore, the electrical connection reliability of the penetrating via 15 connected to thewirings - It is a general object of the present invention to provide a substrate improving the electrical connection reliability of a penetrating via connecting the wirings and a method for manufacturing the same that substantially obviate one or more problems caused by the limitations and disadvantages of the related art.
- Features and advantages of the present invention are presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by the substrate particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
- According to at least one of the embodiments of the present invention, a substrate is provided which includes a base member having a through-hole, a penetrating via provided in the through-hole, and a first wiring and a second wiring connected to the penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole, the penetrating part having a first end and a second end, a first protrusion protruding from the base member, the first protrusion being connected to the first end of the penetrating part so as to be connected to the first wiring, and a second protrusion protruding from the base member, the second protrusion being connected to the second end of the penetrating part so as to be connected to the second wiring, wherein the first protrusion and second protrusion are wider than a diameter of the through-hole.
- Accordingly, the first protrusion and the second protrusion being wider than the diameter of the through-hole are connected to the penetrating via so as to prevent water from infiltrating the gap between the penetrating part and the base member, and thereby, the penetrating via is prevented from being degraded; thus, the electric connection reliability of the penetrating via connected to the wiring can be improved.
- According to another embodiment of the present invention, a substrate is provided which includes a base member having a through-hole, a penetrating via provided in the through-hole, and a first wiring and a second wiring connected to the penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole having a first end and a second end, and a protrusion to be connected to the first wiring, being connected to the first end of the penetrating part and another protrusion to be connected to the second wiring, being connected to the second end of the penetrating part, wherein the protrusion is wider than the diameter of the through-hole.
- Accordingly, a protrusion being wider than the diameter of the through-hole is connected to each end of the penetrating part so as to prevent water from infiltrating the gap between the penetrating part and the base member, and thereby, the penetrating via is prevented from being degraded; thus the electric connection reliability of the penetrating via connected to the wiring can be improved.
- According to another embodiment of the present invention, a method for manufacturing a substrate which is composed of a base member having a through-hole, a penetrating via formed in the through-hole in the base member, and wiring connected to an end of the penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole, having a first end and a second end, a first protrusion protruding from the base member, being connected to the first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, being connected to the second end of the penetrating part, wherein the first protrusion and second protrusion are wider than the diameter of the through-hole is provided. The method for manufacturing the substrate further includes the steps of forming the penetrating via, and forming wiring so as to be connected to the first protrusion.
- According to at least one embodiment of the present invention, the first protrusion and the second protrusion both wider than the diameter of the through-hole are connected to the penetrating via so as to prevent water from infiltrating the gap between the penetrating part and the base member, and thereby, the penetrating via is prevented from being degraded; thus, the electric connection reliability of the penetrating via connected to the wiring can be improved.
- Therefore, a substrate wherein the electric connection reliability of the penetrating via connected to the wiring is improved, and a method for manufacturing the same can be provided.
- Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a diagram showing a substrate of the prior art; -
FIG. 2 is a cross-sectional diagram of the substrate according to a first embodiment of the present invention; -
FIG. 3 is a plan view of a base member for manufacturing the substrate according to the present embodiment; -
FIGS. 4 through 29 are diagrams showing the manufacturing steps of the substrate according to the first embodiment; and -
FIGS. 30 through 36 are diagrams showing the other manufacturing steps of the substrate. - In the following, embodiments of the present invention are described with reference to the accompanying drawings.
- First, with reference to
FIG. 2 , a detailed description is given of a configuration of asubstrate 50 according to the first embodiment of the present invention.FIG. 2 is a cross-sectional diagram of the substrate according to the first embodiment of the present invention. Thesubstrate 50 is composed of abase member 51, aninsulating layer 53, penetratingvias 54, aninsulating layer 65,wirings 68, firstdiffusion protecting layers 61, seconddiffusion protecting layers 71, and solder resist 75. Thesubstrate 50 is an interposer. As shown inFIG. 2 , on the undersurface of thesubstrate 50, for example, MEMS (Micro Electro Mechanical Systems) wherein fine processing technology of the semiconductor is used and a semiconductor device are mounted, while on the upper side of thesubstrate 50, for example, another substrate such as a motherboard is connected. - The
base member 51 is a silicon member which is composed of silicon. The thickness Ml of thebase member 51 is, for example, 150 μm. In thebase member 51, plural of through-holes 52 for disposing the penetratingvias 54 are provided so as to penetrate thebase member 51. The through-hole 52 having a diameter R1 of the aperture is formed. Theinsulating layer 53 is provided on the surface of thebase member 51 including the through-holes 52. Accordingly, by providing theinsulating layer 53 on the surface of thebase member 51 including the through-holes 52, thebase member 51 is insulated from the penetrating via 54. It should be noted that as thebase member 51, materials such as a glass material except silicon can be used. In addition to this, when materials having an insulating property such as a glass material are used, it is not necessary to provide theinsulating layer 53. - The penetrating
via 54 is composed of apenetrating part 55,wirings connecting part 56 as a first protrusion, and aconnection pad 57 as a second protrusion. The penetratingpart 55 is provided in the through-hole 52 on which theinsulating layer 53 is formed, and the diameter is predetermined to be R1 (hereinafter, the diameter is referred to as “Diameter R1”). The size of the penetratingpart 55 is Diameter R1. - The
wirings connecting part 56 is provided on the upper edge of the penetratingpart 55. Thewirings connecting part 56 protrudes from aside 51 a of thebase member 51, and the size of thewirings connecting part 56 is wider than Diameter R1 of the penetratingpart 55. In other words, the width W1 of thewirings connecting part 56 is set larger than R1 of the penetrating part 55 (W1>R1). Thewirings connecting part 56 is unified with the penetratingpart 55. Thewirings connecting part 56 is provided for connecting awiring 68. - The
connection pad 57 is provided on the undersurface of the penetratingpart 55. Theconnection pad 57 protrudes from aside 51 b of thebase member 51, and the size of theconnection pad 57 is wider than Diameter R1 of the penetratingpart 55. In other words, the width W2 of theconnection pad 57 is set larger than Diameter R1 of the penetrating part 55 (W2>R1). Theconnection pad 57 is provided for connecting devices such as a semiconductor device. The penetratingpart 55,wirings connecting part 56, andconnection pad 57 are unified by a conductive metal layer. As the conductive metal layer, for example, a Cu layer can be used. - The first
diffusion protecting layer 61 is provided on theconnection pad 57. The firstdiffusion protecting layer 61 is formed for improving wettability of solder and protecting Cu contained in the penetrating via 54 from diffusing into the solder (drawing is omitted) connected to theconnection pad 57. The firstdiffusion protecting layer 61 comprises, for example, a lamination layer which is composed of aNi layer 62 and anAu layer 63. The thickness of theNi layer 62 is, for example, 2 through 5 μm and the thickness of theAu layer 63 is, for example, 0.1 through 0.5 μm. It should be noted that instead of the above described Ni/Au layer, for example, a Ni/Pd layer and a Ni/Pd/Au layer can be used as the first diffusion protecting layer 61 (the Ni layer being the connected to the connection pad 57). - The insulating
layer 65 having an open part exposing thewirings connecting part 56 is formed on thesurface 51 a of thebase member 51. For the insulatinglayer 65, for example, resin can be used where one of metal particles functioning as a catalyst for plating and particles of metal compound (chloride, hydroxide, oxide and others) is dispersed. For the resin in this case, for example, epoxy resin and polyimide resin can be used. For the metal functioning as a catalyst, palladium and platinum can be used, especially, platinum is desirable. Moreover, for the metal compound, for example, palladium chloride and palladium sulfate can be used. In the present embodiment, for the insulatinglayer 65, epoxy resin where palladium particles are dispersed is used. By using resin including palladium as the insulatinglayer 65, electroless plating can be performed directly on the insulatinglayer 65 without performing a desmear treatment and a palladium activation treatment. Accordingly, the manufacturing steps of thesubstrate 50 can be simplified. The thickness M2 of the insulatinglayer 65 is, for example, 5 μm. - The
wiring 68 is provided on the insulatinglayer 65 so as to be connected to thewirings connecting part 56. Thewiring 68 having anexternal connection terminal 69 is composed of aconductive metal layer 67 and aseed layer 66. Theexternal connection terminal 69 is provided for being connected to a substrate such as a motherboard. By providing thisexternal connection terminal 69, the position of theexternal connection terminal 69 can be set corresponding to the position of the external connection terminal of the substrate like a motherboard. As theconductive metal layer 67, for example, a Cu layer can be used. When a Cu layer is used for theconductive metal layer 67, the thickness M3 of theconductive metal layer 67 is, for example, 3 through 10 μm. As theseed layer 66, for example, a Ni layer can be used. The thickness of theseed layer 66 is, for example, 0.1 μm. - The solder resist 75 having an
open part 76 exposing theexternal connection terminal 69, is provided so as to cover thewiring 68 and insulatinglayer 65 except theexternal connection terminal 69. The solder resist 75 is provided for protecting thewiring 68. - The second
diffusion protecting layer 71 is provided on theexternal connection terminal 69. The seconddiffusion protecting layer 71 is formed for improving wettability of solder and protecting Cu contained in thewiring 68 from diffusing into the solder (drawing is omitted) connected to theexternal connection terminal 69. The seconddiffusion protecting layer 71 comprises, for example, a lamination layer which is composed of aNi layer 72 and anAu layer 73. The thickness of theNi layer 72 is, for example, 2 through 5 μm and the thickness of theAu layer 73 is, for example, 0.1 through 0.5 μm. It should be noted that instead of the above described Ni/Au layer, for example, a Ni/Pd layer and a Ni/Pd/Au layer can be used as the second diffusion protecting layer 71 (the Ni layer must be connected to the external connection terminal 69). -
FIG. 3 is a plan view of abase member 51 for manufacturing thesubstrate 50 according to the present embodiment. “A” shown inFIG. 3 is an area where thesubstrate 50 is formed (hereinafter, “A” is referred to as “Substrate Forming Area A”). As shown inFIG. 3 , according to the present embodiment, a silicon base member (silicon wafer) having a plurality of Substrate Forming Areas A is used as thebase member 51. As above described, the silicon member is used as thebase member 51, and after the respective manufacturing steps are performed, thebase member 51 is cut into a plurality of pieces, and thus, plural of thesubstrates 50 are manufactured all at once. Accordingly, the productivity of manufacturing thesubstrate 50 is improved. - Next, with reference to
FIGS. 4 through 29 , a description is given of a method for manufacturing thesubstrate 50 according to the first embodiment.FIGS. 4 through 29 are diagrams showing the manufacturing steps of thesubstrate 50 according to the first embodiment. It should be noted that an example is given where a silicon member is used as thebase member 51. - First, as shown in
FIG. 4 , an adhesive 92 is provided on asupport board 91. Thesupport board 91 is provided for supporting thebase member 51. As thesupport board 91, for example, a glass member and a silicon member (specifically a silicon wafer) can be used. When the silicon member is used as thesupport board 91, the thickness M4 of thesupport board 91 is, for example, 725 μm. The adhesive 92 is provided on thesupport board 91 for bonding ametal foil 93 which is described below. As the adhesive 92, for example, a thermo peal tape and a thermal ablation adhesive can be used which lose adhesion when being heated. - Next, as shown in
FIG. 5 , ametal foil 93 such as a Cu layer is bonded to thesupport board 91 via the adhesive 92 (the metal foil providing step). Then, as shown inFIG. 6 , a first resistlayer 94 which is not in the exposure state is formed on the metal foil 93 (the first resist layer forming step). For the first resistlayer 94 which is a resist having adhesion, for example, a photosensitive dry film resist and a liquid resist can be used. - By using the first resist
layer 94 having adhesion, thebase member 51 having through-holes 52 can be fixed on thesupport board 91 via the first resist layer 94 (as shown inFIG. 7 ). The thickness of the first resist layer is, for example, 10 through 15 μm. Moreover, instead of the first resistlayer 94, another adhesive such as epoxy and polyimide can be used if the adhesive can be dissolved by some treatment liquid. - Next, as shown in
FIG. 7 , the through-hole 52 having a diameter R2 (R1=R2) is formed, and thebase member 51 where the insulatinglayer 53 is formed so as to cover the surface of the base member 51 (including thebase member 51 part corresponding to the through-hole 52), is provided on the first resistlayer 94 having adhesion and fixed (the base member disposing step). The through-hole 52 can be formed by, for example, one of drill processing, laser processing, and anisotropic etching. Moreover, the diameter R2 of the through-hole 52 can be selected properly from the range of, for example, 10 through 60 μm. As the insulatinglayer 53, for example, an oxide layer (SiO2) formed by a CVD method and a thermal oxide layer (SiO2) formed by an oxidizing furnace can be used. Furthermore, the thickness M1 of thebase member 51 is, for example, 150 μm. - Next, as shown in
FIG. 8 , a developer is supplied to the inside of the through-hole 52, and then, the developer dissolves the first resistlayer 94 exposed by the through-hole 52 so as to form a space 97 (the space forming step). Thespace 97 is wider than the diameter R2 of the through-hole 52, and the width W2 of thespace 97 is larger than the diameter R2 of the through-hole 52 (W2>R2). As a method for supplying the developer into the through-hole 52, for example, a dip development method where a structure shown inFIG. 7 is dipped into the developer and a spray development method where the developer is sprayed like a shower on the through-hole 52 are applied. - In either method of development, by controlling the dipping time in the developer, the space can be formed. As a condition for forming the
space 97 by the spray development method, for example, a pressure of spraying the developer is 2.0 kgf/cm2, a temperature is 25 through 30° C., and a developer spraying time is 6 min. It should be noted that “a size of a through-hole” is the diameter R2 of the through-hole 52. Then, a thermal treatment (a first thermal treatment) is performed on the structure as shown inFIG. 8 , and a polymerization reaction is carried out on the first resistlayer 94 which is not in the exposure state so as to harden the first resist layer 94 (the first resist layer hardening step). Thus the first resist layer is hardened so that the first resist layer can be tolerant of the plating solution. - Next, as shown in
FIG. 9 , a through-hole 52 is exposed on the insulatinglayer 53 formed on thesurface 51 a of thebase member 51, and a second resistlayer 101 having anopen part 102 wider than the diameter R2 of the through-hole 52 is formed (the second resist layer forming step). The diameter W1 of the first open part, i.e. theopen part 102 is formed larger than the diameter R2 of the through-hole 52 (W1>R2). - Next, as shown in
FIG. 10 , by using themetal foil 93 as a power supply layer, anAu layer 63 and aNi layer 62 are separated out in turn on themetal foil 93 according to the electrolytic plating method and grown, and thus the firstdiffusion protecting layer 61 is formed (the first diffusion protecting layer forming step). The thickness of theAu layer 63 is, for example, 0.1 through 0.5 μm, and the thickness of theNi layer 62 is, for example, 2 through 5 μm. Accordingly, the firstdiffusion protecting layer 61 is formed by the electrolytic plating method; thus the diffusion protecting layer having a layer superior to the layer formed by the electroless plating method can be obtained. - Next, as shown in
FIG. 11 , by using themetal foil 93 and theNi layer 62 as a power supply layer, aconductive metal layer 104 is separated out and grown so as to fill thespace 97, through-hole 52 and open part 102 (the conductive metal layer forming step). In this case, theconductive metal layer 104 protrudes from thesurface 101 a of the second resistlayer 101. As theconductive metal layer 104, for example, a Cu layer can be used. - Next, as shown in
FIG. 12 , theconductive metal layer 104 protruding from thesurface 101 a of the second resistlayer 101 is ground to be removed so that theconductive metal layer 104 and thesurface 101 a of the second resistlayer 101 become flat. Accordingly, the following components are formed all at once: theconnection pad 57 having the width W2 in thespace 97, the penetratingpart 55 having the diameter R1 in the through-hole 52, and the wirings connecting part 56 (the first protrusion) having the width W1 in theopen part 102. And thus, the penetrating via 54 is formed. The widths W1 and W2 are wider than the diameter R1 of the penetratingpart 55. - Accordingly, by forming the
connection pad 57 andwirings connecting part 56 wider than the diameter R1 of the penetratingpart 55 in the penetrating via 54, water is prevented from infiltrating the gap between the penetratingpart 55 and thebase member 51, and the degradation of the penetrating via 54 is controlled. Therefore, the electric connection reliability of the penetrating via 54 connected to thewiring 68 is improved. - Moreover, the
metal foil 93 is used as a power supply layer, theconductive metal layer 104 is separated and grown on themetal foil 93 so as to fill thespace 97, through-hole 52 and the firstopen part 102, and thus a void (cavity) is prevented from forming in the penetrating via 54. - Next, as shown in
FIG. 13 , the second resistlayer 101 is removed by a resist stripper (the second resist layer removing step). Then, as shown inFIG. 14 , an insulatinglayer 65 having anopen part 103 exposing thewirings connecting part 56 is provided on thesurface 51 a of the base member 51 (the insulating layer forming step). In the present embodiment, an epoxy resin containing palladium particles therein is used for the insulatinglayer 65. The thickness M2 of the insulatinglayer 65 is, for example, 5 μm. - As shown in
FIG. 15 , aseed layer 66 is formed on theupper surface 65 a and thelateral surface 65 b of the insulatinglayer 65 by the electroless plating method (the seed layer forming step). It should be noted that conventionally, before forming a seed layer on resin by the electroless plating method, a desmear treatment is performed on the surface of the resin (insulating layer) and roughed in advance, and then a palladium activation treatment is performed on the surface of the resin. The palladium activation treatment is dipping a sample to be plated in either a catalyzing treatment solution or an accelerating treatment solution, and then separating out the palladium which will be a core to be plated by the electroless plating method on the surface of the resin. According to the conventional technology, a plated layer can not be formed by the electroless plating method until the palladium activation treatment is performed. Therefore, according to the conventional technology, the steps are very troublesome. - On the contrary, according to the present embodiment, an epoxy resin containing the palladium particles therein is applied to the insulating layer, so that the
seed layer 66 can be formed directly on the insulating layer by the electroless plating method without performing the desmear treatment and palladium activation treatment in advance. Accordingly, the manufacturing steps of thesubstrate 50 can be simplified. As theseed layer 66, for example, a Ni layer can be used. When resin containing palladium particles therein is used for the insulatinglayer 65, a Ni—B layer can be formed. - Next, as shown in
FIG. 16 , on theseed layer 66, a dry film resist 105 having anopen part 106 corresponding to the area where thewiring 68 is provided is formed. The thickness of the dry film resist 105 is, for example, 10 through 15 μm. Then, as shown inFIG. 17 , by using thewirings connecting part 56 andseed layer 66 as a power supply layer, aconductive metal layer 67 is separated out onopen parts - Accordingly, the
conductive metal layer 67 and the penetrating via 54 are electrically connected. After theconductive metal layer 67 and the penetrating via 54 are connected, as shown inFIG. 18 , the dry film resist 105 is removed by the resist stripper. Then, as shown inFIG. 19 , on the structure shown inFIG. 18 , a dry film resist 111 is formed exposing theconductive metal layer 67 corresponding to the area B where anexternal connection terminal 69 is to be formed.Open parts 112 are formed in the dry film resist 111, and theconductive metal layer 67 corresponding to the area B is exposed from theopen part 112. - Next, as shown in
FIG. 20 , by using theconductive metal layer 67 as a power supply layer, according to the electrolytic plating method, aNi layer 72 and anAu layer 73 are separated out in turn and grown on theconductive metal layer 67 exposed from theopen part 112 so as to form a second diffusion protecting layer 71 (the second diffusion protecting layer forming step). The thickness of theNi layer 72 is, for example, 2 through 5 μm, and the thickness of theAu layer 73 is, for example, 0.1 through 0.5 μm. Accordingly, the seconddiffusion protecting layer 71 is formed by the electrolytic plating method, thus the seconddiffusion protecting layer 71 having a layer superior to the layer formed by the electroless plating method can be obtained. The dry film resist 111 is removed after the seconddiffusion protecting layer 71 is formed. - Next, as shown in
FIG. 21 , a dry film resistlayer 114 is formed so as to cover only theconductive metal layer 67 and the seconddiffusion protecting layer 71. Then, as shown inFIG. 22 , theseed layer 66 formed on the insulatinglayer 65 is removed by etching. Accordingly, theexternal connection terminal 69 is provided and thewiring 68 including theseed layer 66 andconductive metal layer 67 is formed. After theseed layer 66 is removed, as shown inFIG. 23 , the dry film resist 114 is removed by the resist stripper. - Next, as shown in
FIG. 24 , a heat-resistant protective member, i.e. a temperature-resistant tape 116 is attached so as to cover thewiring 68, seconddiffusion protecting layer 71 and anupper surface 65 a of the insulating layer 65 (the protective member disposing step). The temperature-resistant tape 116 is a tape having a resistance against the etchant. Accordingly, thewiring 68 and the seconddiffusion protecting layer 71 are covered by the temperature-resistant tape 116 so as to protect thewiring 68 and the seconddiffusion protecting layer 71 from the heat generated in a second thermal treatment (as shown inFIG. 25 ) performed in removing thesupport board 91 from thebase member 51. As the temperature-resistant tape 116, for example, a PET and a PEN which are flame retardant can be used. It should be noted that the temperature-resistant tape 116 is provided so as to cover at least thewiring 68 and seconddiffusion protecting layer 71. - Next, as shown in
FIG. 25 , the structure shown inFIG. 24 is heated (the second thermal treatment) and the adhesive 92 andsupport board 91 are removed from the base member 51 (the support board removing step). According to the present embodiment, a thermo peal tape which loses adhesion when being heated is used as the adhesive 92. The conditions of the second thermal treatment are, for example, a heating temperature of 150° C. and a heating time of 30 min. Then, as shown inFIG. 26 , themetal foil 93 is removed by etching (the metal foil removing step). Accordingly, the first resistlayer 94 and the firstdiffusion protecting layer 61 are exposed. As described above, thewiring 68 is covered by the temperature-resistant tape 116 having a resistance against the etchant, and thereby, thewiring 68 is not etched. - Next, as shown in
FIG. 27 , the first resistlayer 94 is removed by the ablation liquid. Then, as shown inFIG. 28 , the temperature-resistant tape 116 is removed. After the tape is removed, as shown inFIG. 29 , solder resist 75 is provided so as to expose the seconddiffusion protecting layer 71 and cover thewiring 68 and insulatinglayer 65. The solder resist 75 hasopen parts 76 exposing the seconddiffusion protecting layer 71. After the solder resist 75 is formed, thebase member 51 is diced into a plurality of thesubstrates 50 as shown inFIG. 2 . - As the described manufacturing steps, the penetrating via 54 is formed including the
wiring connection part 56 which is formed on one edge of the penetratingpart 55 and thewiring connection part 56 is wider than the diameter R1 of the penetratingpart 55, and theconnection pad 57 which is formed on the other edge of the penetratingpart 55 and has a shape wider than the diameter R1 of the penetratingpart 55. Accordingly, water is prevented from infiltrating a gap between the penetratingpart 55 and thebase member 51, and degradation of the penetrating via 54 is controlled; therefore, the electric connection reliability of the penetrating via 54 connected to thewiring 68 is improved. Moreover, thewiring 68 is connected to thewirings connecting part 56 having a shape wider than the diameter R1 of the penetratingpart 55, and thus, thewirings connecting part 56 is easily connected to thewiring 68. - It should be noted that in the substrate shown in
FIG. 13 , a diffusion protecting layer is formed on the connectingpart 56 by electrolytic plating method without forming the above described layers such as a conductive metal layer. Then, thesupport board 91, the adhesive 92, themetal foil 93, and the first resistlayer 94 are removed so as to obtain a substrate having only the penetrating via 54. This substrate can also be applied to the present invention. - Next, with reference to
FIGS. 30 through 36 , a description is given of another method for manufacturing thesubstrate 50.FIGS. 30 through 36 are diagrams showing the other method's manufacturing steps of thesubstrate 50. - First, as shown in
FIG. 30 , the adhesive 92 is provided on thesupport board 91 and themetal foil 93 such as Cu is attached on the adhesive 92 (the metal foil disposing step). Then, a dry film resist 118 having anopen part 119 is provided on themetal foil 93. Theopen part 119 exposes themetal foil 93. - Next, as shown in
FIG. 31 , by using themetal foil 93 as a power supply layer, anAu layer 63 and aNi layer 62 are separated out in turn and grown on themetal foil 93 exposed from theopen part 119 so as to form a first diffusion protecting layer 61 (the first diffusion protecting layer forming step). And then, as shown inFIG. 32 , the dry film resist 118 is removed by the resist stripper. - Next, as shown in
FIG. 33 , a first resistlayer 121 which is not in the exposure state is provided on themetal foil 93 so as to cover the first diffusion protecting layer 61 (the first resist layer forming step). As the first resistlayer 121 which is a resist having adhesion, for example, photosensitive dry film resist can be used. The thickness of the first resistlayer 121 is, for example, 10 μm through 15 μm. - Next, as shown in
FIG. 34 , a through-hole 52 having a diameter R2 is formed and abase member 51 where an insulatinglayer 53 is formed so as to cover a surface of the base member 51 (including the base member part corresponding to the through-hole 52) is disposed on the first resistlayer 121 having adhesion and fixed on the first resist layer 121 (the base member disposing step). - Next, as shown in
FIG. 35 , the developer is supplied into the through-hole 52, and the developer dissolves the first resistlayer 121 exposed on the through-hole 52 so as to form a space 123 (the space forming step). Thespace 123 is a space wider than the diameter R2 of the through-hole 52, and the width W3 of thespace 123 is larger than the diameter R2 of the through-hole 52 (W3>R2). Thespace 123 is exposed from theNi layer 62. As for a method for supplying the developer in the through-hole 52, the dip development and the spray development described in the first embodiment can be applied. - Next, as shown in
FIG. 36 , the through-hole 52 is exposed on the insulatinglayer 53 formed on thesurface 51 a of thebase member 51, and the second resistlayer 101 having anopen part 102 wider than the diameter R2 of the through-hole 52 is formed (the second resist layer forming step). The width W1 of theopen part 102 which is the first open part is larger than the diameter R2 of the through-hole 52 (W1>R2). Then, thesubstrate 50 can be manufactured by steps similar to those inFIGS. 11 through 29 . - Accordingly, by inserting another step between the first diffusion protecting layer forming step and the conductive metal layer forming step (in the present embodiment, for example, the first resist layer forming step), the plating solution used to form
Ni layer 63 is prevented from being mixed with the plating solution used to form aconductive metal layer 104. Therefore, theconductive metal layer 104 having an excellent layer can be formed. - Further, the present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. It should be noted that the
wiring 68 is formed on only theupper surface 51 a of thebase member 51, but a wiring (including an external connection terminal) connected to theconnection pad 57 can also be provided according to the similar manufacturing step shown inFIGS. 14 through 23 . Thus, the wirings are disposed on bothsides base member 51 so as to connect various substrates such as a motherboard, semiconductor device, and MEMS. Therefore, the scope of the application of the substrate can be expanded and the electrical connection reliability between the wirings formed on both sides of thebase member 51 can be improved. - The present invention can be applied to a substrate improving the electrical connection reliability of the penetrating via connecting the wiring and a method for manufacturing the same.
- According to at least one embodiment of the present invention, a diffusion protecting layer is provided on the external connection terminal and on the second protrusion, and when the wiring and the penetrating via contain Cu therein, the Cu contained in the external connection terminal and in the second protrusion is protected from diffusing by the diffusion protecting layer.
- By using the metal foil as a power supply, the conductive metal layer is separated on the metal foil and grown according to the electrolytic plating method; the space, the through-hole, and the first open part are filled in turn with the conductive metal layer to be a penetrating via, and thereby, a void (cavity) is prevented from forming in the penetrating via.
- The first resist layer is hardened according to the first thermal treatment so as to give the first resist layer tolerance against the etchant.
- Moreover, a first diffusion protecting layer is formed according to the electrolytic plating method, and thereby, the diffusion protecting layer having a layer superior to the layer formed according to an electroless plating method can be obtained.
- Since the resin layer containing the palladium particles therein is used for the insulating layer, when the seed layer is formed on the insulating layer, it is not necessary to perform a treatment in advance on the insulating layer. Therefore, the steps of manufacturing the substrate can be simplified.
- The second diffusion protecting layer is formed according to the electrolytic plating method, and thereby, the diffusion protecting layer having a layer superior to the layer formed according to the electroless plating method can be obtained.
- The heat-resistant protecting member is provided so as to cover at least the wiring and the second diffusion protecting layer, and thereby, the wiring and the second diffusion protecting layer are protected from the heat generated in the second thermal treatment performed for removing the adhesive and the support board from the base member.
- According to another aspect of the embodiment of the present invention, the method for manufacturing the substrate includes the steps of removing the metal foil by etching after the step of removing the support board, removing the first resist layer, and removing the protecting member after the step of removing the first resist layer.
- According to the above described steps, the protecting member is removed after the step of removing the metal foil so as to protect the wiring from being etched.
- According to the embodiment of the invention, the step of forming the first diffusion protecting layer is performed immediately after the step of disposing the metal foil; thus a plating solution used for forming the first diffusion protecting layer is prevented from being mixed with another plating solution used for forming the penetrating via, and thereby, the conductive metal layer having an excellent layer can be formed.
- According to the embodiment of the present invention, a substrate wherein the electric connection reliability of the penetrating via connected to the wirings is improved and a method for manufacturing the same can be provided.
- The present application is based on Japanese Priority Application No.2004-323939 filed on Nov. 8, 2004, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
Claims (13)
1. A substrate comprising:
a base member having a through-hole;
a penetrating via provided in said through-hole, wherein
said penetrating via includes
a penetrating part provided in said through-hole, said penetrating part having a first end and a second end;
a first protrusion protruding from said base member, said first protrusion being connected to the first end of said penetrating part; and
a second protrusion protruding from said base member, said second protrusion being connected to the second end of said penetrating part, wherein
said first protrusion and second protrusion are wider than a diameter of said through-hole.
2. The substrate as claimed in claim 1 , wherein
a diffusion protecting layer is formed on said first protrusion and on said second protrusion.
3. A substrate comprising:
a base member having a through-hole;
a penetrating via provided in said through-hole; and
a first wiring and a second wiring connected to said penetrating via, wherein
said penetrating via includes
a penetrating part provided in said through-hole having a first end and a second end; and
a protrusion to be connected to said first wiring, being connected to the first end of said penetrating part and another protrusion to be connected to said second wiring, being connected to the second end of said penetrating part, wherein
said protrusion is wider than a diameter of said through-hole.
4. The substrate as claimed in claim 3 , wherein one of said first wiring and said second wiring has an external connection terminal; and a diffusion protecting layer is formed on said external connection terminal.
5. A method for manufacturing a substrate comprising a base member having a through-hole; and a penetrating via formed in said through-hole in said base member, wherein said penetrating via includes; a penetrating part provided in said through-hole, said penetrating part having a first end and a second end; a first protrusion protruding from said base member, said first protrusion being connected to the first end of said penetrating part; and a second protrusion protruding from said base member, said second protrusion being connected to the second end of said penetrating part, wherein said first protrusion and second protrusion are wider than a diameter of said through-hole,
said method comprising the step of forming said penetrating via.
6. The method for manufacturing the substrate as claimed in claim 5 , wherein the step of forming said penetrating via further includes the steps of:
attaching a metal foil on a support board by an adhesive;
forming a first resist layer on said metal foil;
disposing said base member having said through-hole on said first resist layer;
removing said first resist layer exposed from said through-hole by a developer so as to expose said metal foil and to form a space being wider than a diameter of said through-hole;
forming a second resist layer having a first open part being wider than the diameter of said through-hole so as to expose the through-hole in said base member; and
forming a conductive metal layer according to an electrolytic plating method so as to fill the space, the through-hole and the first open part.
7. The method for manufacturing the substrate as claimed in claim 6 , further comprising the step of hardening said first resist layer according to a thermal treatment after the step of forming said space.
8. The method for manufacturing the substrate as claimed in claim 6 , further comprising the step of forming a first diffusion protecting layer on said metal foil exposed in said space according to an electrolytic plating method after the step of forming said second resist layer.
9. The method for manufacturing the substrate as claimed in claim 6 , further including a wiring forming step forming a wiring so as to be connected to said first protrusion, said wiring forming step comprising:
removing said second resist layer;
forming an insulating layer having a second open part exposing said first protrusion on said base member; and
forming a seed layer on said insulating layer where said wiring is formed; wherein
said insulating layer comprises a resin containing palladium particles therein.
10. The method for manufacturing the substrate as claimed in claim 9 , wherein said wiring has an external connection terminal, said method further comprising the step of forming a second diffusion protecting layer on said external connection terminal according to the electrolytic plating method after the step of forming said wiring.
11. The method for manufacturing the substrate as claimed in claim 10 , further comprising the steps of:
disposing a heat-resistant protecting member so as to cover at least said wiring and said second diffusion protecting layer after the step of forming said second diffusion protecting layer; and
removing said adhesive and said support board from said base member according to a thermal treatment after the step of forming said protecting member.
12. The method for manufacturing the substrate as claimed in claim 11 , further comprising the steps of:
removing said first resist layer; and
removing said protecting member after the step of removing said first resist layer.
13. The method for manufacturing the substrate as claimed in claim 8 , wherein the step of forming said first diffusion protecting layer is performed immediately after the step of disposing said metal foil.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/061,768 US7772118B2 (en) | 2004-11-08 | 2008-04-03 | Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-323939 | 2004-11-08 | ||
JP2004323939A JP3987521B2 (en) | 2004-11-08 | 2004-11-08 | Substrate manufacturing method |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/061,768 Division US7772118B2 (en) | 2004-11-08 | 2008-04-03 | Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US20060096781A1 true US20060096781A1 (en) | 2006-05-11 |
Family
ID=35784728
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/247,813 Abandoned US20060096781A1 (en) | 2004-11-08 | 2005-10-11 | Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same |
US12/061,768 Active 2025-12-18 US7772118B2 (en) | 2004-11-08 | 2008-04-03 | Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/061,768 Active 2025-12-18 US7772118B2 (en) | 2004-11-08 | 2008-04-03 | Substrate having high electrical connection reliability of a penetrating via connected to wirings and a method for manufacturing the same |
Country Status (7)
Country | Link |
---|---|
US (2) | US20060096781A1 (en) |
EP (1) | EP1656006B1 (en) |
JP (1) | JP3987521B2 (en) |
KR (1) | KR20060054104A (en) |
CN (1) | CN100517678C (en) |
DE (1) | DE602005004586T2 (en) |
TW (1) | TWI402956B (en) |
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Also Published As
Publication number | Publication date |
---|---|
CN1783472A (en) | 2006-06-07 |
JP3987521B2 (en) | 2007-10-10 |
JP2006135174A (en) | 2006-05-25 |
CN100517678C (en) | 2009-07-22 |
EP1656006B1 (en) | 2008-01-30 |
US7772118B2 (en) | 2010-08-10 |
TW200635021A (en) | 2006-10-01 |
DE602005004586D1 (en) | 2008-03-20 |
TWI402956B (en) | 2013-07-21 |
EP1656006A1 (en) | 2006-05-10 |
DE602005004586T2 (en) | 2009-03-19 |
US20080261396A1 (en) | 2008-10-23 |
KR20060054104A (en) | 2006-05-22 |
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Legal Events
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Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YAMANO, TAKAHARU;REEL/FRAME:017092/0050 Effective date: 20050926 |
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STCB | Information on status: application discontinuation |
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