TWI819653B - Electronic device and method of forming electronic device - Google Patents

Abstract

An electronic device includes a first electronic unit, a second electronic unit, a bonding pad, an insulating layer and a circuit layer. The bonding pad is disposed between the first electronic unit and the second electronic unit. The insulating layer is disposed corresponding to the first electronic unit, the second electronic unit and the bonding pad. The first electronic unit is electrically connected with the second electronic unit via the circuit layer and the bonding pad.

Description

Electronic device and method of forming electronic device

The present disclosure relates to an electronic device and a method of forming the electronic device, in particular to an electronic device and a method of forming the electronic device that can improve electrical reliability.

In the manufacturing process of electronic devices, it is often necessary to first place an electronic unit, such as a known good die (KGD), on a carrier board, and then perform electrical connection steps between several electronic units. However, there may be electrical reliability issues between several electronic units. For example, after several wafers are transferred, their positions may shift from a predetermined area due to subsequent processes, causing electrical problems.

In view of this, it is an urgent issue to provide a method of manufacturing an electronic device that can reduce electrical reliability problems caused by positional deviation.

Some embodiments of the present disclosure provide an electronic device. The electronic device may include a first electronic unit, a second electronic unit, bonding pads, an insulation layer and a circuit layer. The bonding pad is disposed between the first electronic unit and the second electronic unit. The insulating layer is arranged corresponding to the first electronic unit, the second electronic unit and the bonding pad. The first electronic unit is electrically connected to the second electronic unit through the circuit layer and the bonding pad.

Some embodiments of the present disclosure also provide a method of forming an electronic device. First, provide A substrate includes a bonding pad, a first electronic unit and a second electronic unit. Then, an insulating layer is provided on the substrate. The insulating layer surrounds the bonding pad, the first electronic unit and the second electronic unit. The bonding pad is disposed between the first electronic unit and the second electronic unit, and the bonding pad is electrically connected to the first electronic unit and the second electronic unit.

100: Electronic devices

101:Substrate

101S: Upper surface

110:First electronic unit

110C:Joining terminal

110S: Bottom surface

110T: Top surface

120: Second electronic unit

120C:Joining terminal

120S: Bottom surface

120T:Top surface

130:Joining pad

131: Conductor layer

131S:Surface

132: Basal layer

133: Bonding pad area

134: Bonding pad area

135: Bonding pad area

136: dividing line

137:Open your mouth

140:Insulation layer

1401:Part 1

1402:Part 2

1403:Part 3

140B: Bottom surface

140S: Surface

150:Circuit layer

151: First conductive layer

152: Second conductive layer

153: End shaft

159:Insulation layer

d: spacing

H1: height

H2: Maximum height

L1: extension line

L2: extension line

P1: Part

P2: Part

P3: Part

C: Arc lead angle

R: diagonal direction

W: maximum width

1 , 2 , 3 , 4 , 5 to 6 are flow diagrams of some embodiments of methods of forming an electronic device according to the present disclosure, and each illustrate a schematic top view of the electronic device.

1A is a schematic top view of a modified implementation of another method of forming an electronic device according to the present disclosure.

FIG. 5A is a schematic cross-sectional view of an electronic device according to some embodiments of the present disclosure, along line A-A’ in FIG. 5 .

FIG. 6 , FIG. 6A , and FIG. 6B respectively illustrate partial top views of different embodiments of bonding pads according to the present disclosure.

The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in order to make it easy for readers to understand and for the simplicity of the drawings, many of the drawings in the present disclosure only depict a part of the electronic device. And certain elements in the drawings are not drawn to actual scale. In addition, the number and size of components in the figures are only for illustration and are not intended to limit the scope of the present disclosure.

Throughout this disclosure and the appended claims, certain words are used to refer to particular elements. Those skilled in the art will understand that electronic device manufacturers may refer to the same component by different names. This article is not intended to differentiate between components that have the same function but have different names.

In the following description and claims, the words "including" and "include" are open-ended words, and therefore they should be interpreted to mean "including but not limited to...".

It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or directly connected to the other element or layer. to another element or layer, or there is an intervening element or layer between the two (indirect cases). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present.

In some embodiments of the present disclosure, terms related to joining and connecting, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact. There are other structures located between these two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect means of electrical connection.

Although the terms first, second, third... may be used to describe various constituent elements, the constituent elements are not limited to these terms. This term is only used to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but may be replaced by first, second, third... according to the order in which the elements are declared in the claims. Therefore, in the following description, a first constituent element may be a second constituent element in the claims.

It should be noted that the following embodiments can be replaced, reorganized, and mixed with technical features in several different embodiments without departing from the spirit of the present disclosure to complete other embodiments.

FIGS. 1 , 2 , 3 , 4 , 5 and 6 are flowcharts of some embodiments of methods of forming an electronic device according to the present disclosure, respectively illustrating a schematic top view of the electronic device 100 . In the present disclosure, the electronic device 100 may include an antenna device, a display device, a radar device, a lidar device, a packaging component, a packaging module, etc., but the disclosure is not limited thereto. Packaged components may include, for example, system-in-package (SiP) or system on a chip (SoC) and other architectures, but this disclosure is not limited to this. If the electronic device 100 is used in packaging, it may be suitable for packaging such as wafer level packaging (WLP) or panel level packaging (PLP), which may include, for example, chip-first or line packaging. Packaging methods such as RDL first, but the present disclosure is not limited thereto. It should be noted that the electronic device can be any combination of the above, but the present disclosure is not limited thereto. Each embodiment of the present disclosure illustrates a combination of one or more electronic units, bonding pads, insulating layers, and circuit layers located on a temporary carrier board. The electronic unit of the present disclosure takes a fan-out packaged semiconductor unit as an example. However, the present disclosure is not limited to this. In the following, a display device will be used as an example of an electronic device to illustrate the disclosure, but the disclosure is not limited thereto.

As shown in FIGS. 1 to 6 , a substrate 101 is provided. The substrate 101 may be a temporary support board used to temporarily support a combination of one or more electronic units, bonding pads, insulation layers, and circuit layers. For example, in some embodiments, the substrate 101 may include wafers, wafers, stainless steel, alloys, carbon fibers, glass fibers, or glass of organic materials, inorganic materials, or combinations thereof, but the present disclosure is not limited thereto.

As shown in FIGS. 1 to 6 , the substrate 101 may include at least a first electronic unit 110 , a second electronic unit 120 and a bonding pad 130 , but the disclosure is not limited thereto. At this time, due to the existence of the substrate 101 , the first electronic unit 110 , the second electronic unit 120 and the bonding pad 130 may be disposed on the upper surface 101S of the substrate 101 in a substantially co-planar manner. The first electronic unit 110 or the second electronic unit 120 may independently include passive components and active components, such as capacitors, resistors, inductors, inductors, diodes, transistors, semiconductor components, and integrated circuits (ICs). , printed circuit board (PCB), etc. Diodes may include light emitting diodes or photodiodes. The light emitting diodes may include, for example, organic light emitting diodes (OLEDs), sub-millimeter light emitting diodes (mini LEDs), micro light emitting diodes (micro LEDs) or quantum dot light emitting diodes (quantum dots). dot LED), but this disclosure is not limited to this. The first electronic unit 110, the second electronic unit 120 and the The order of the bonding pads 130 can be arranged as required by referring to the following.

FIG. 1 is a schematic top view of an implementation of a method of forming an electronic device 100 according to the present disclosure. For example, as shown in FIG. 1 , in some embodiments, at least one bonding pad 130 may be provided on the upper surface 101S of the substrate 101 . For convenience of explanation, the following disclosure will take as an example that a bonding pad 130 is first provided on the upper surface 101S of the substrate 101 . For example, as shown in the top view, a bonding pad 130 may be provided at a position of the substrate 101, and a first electronic unit (not shown) and a second electronic unit (not shown) may be reserved on the left and right sides of the bonding pad 130. ), but the disclosure is not limited thereto. Then, as shown in FIG. 2 , in the top view, the first electronic unit 110 and the second electronic unit 120 can be provided on the upper surface 101S of the substrate 101 in the presence of the bonding pad 130 , so that the bonding pad 130 is disposed on between the first electronic unit 110 and the second electronic unit 120 . The method of manufacturing the bonding pads 130 on the substrate 101 is first provided, for example, to facilitate the positioning reference of the first electronic unit (not shown) and the second electronic unit (not shown). The bonding pads 130 are first provided on the substrate 101, and then the first electronic unit and the second electronic unit are provided. The bonding pads 130 may be alignment marks, for example, but the disclosure is not limited thereto.

FIG. 1A is a schematic top view of a modified embodiment of a method of forming an electronic device 100 according to the present disclosure. Alternatively, as shown in FIG. 1A , in some embodiments, the first electronic unit 110 and the second electronic unit 120 may be provided on the substrate 101 . For example, in the top view, the first electronic unit 110 and the second electronic unit 120 may be provided on the substrate 101 The first electronic unit 110 and the second electronic unit 120 are first provided on the left and right upper surfaces 101S, and a space for bonding pads (not shown) is reserved in the middle of the substrate 101, but the disclosure is not limited thereto. Then, as shown in FIG. 2 , in the presence of the first electronic unit 110 and the second electronic unit 120 , a bonding pad 130 can be provided on the upper surface 101S of the substrate 101 , so that the bonding pad 130 is disposed on the first electronic unit 110 and the second electronic unit 120 . The manufacturing method of first providing the first electronic unit 110 and the second electronic unit 120 on the substrate 101 is beneficial to the flexible arrangement of the process. For example, during the process of transferring the electronic unit to the substrate, the transfer device is less likely to be interfered by other components. However, This disclosure is not limited to this.

θ<45°，但本揭露不以此為限。根據一些實施例，夾角θ可以大於等於0且小於15°，但本揭露不以此為限。舉例而言，可透過自動光學系統(Auto-Optical Inspection,AOI)檢測夾角θ，當夾角θ大於等於0且小於45°時，例如有利於提升電子單元之間的電性可靠度，但本揭露不以此為限。 When the first electronic unit 110 , the second electronic unit 120 and the bonding pad 130 are respectively disposed on the substrate 101 , there is a gap between the first electronic unit 110 and the bonding pad 130 or between the second electronic unit 120 and the bonding pad 130 . , may not be set parallel to each other. As shown in FIG. 2 , the bonding pad 130 may have an extending direction L1 along the long side 130L of the bonding pad 130 . Similarly, the first electronic unit 110 may have an extension direction L2 close to the edge 110L of the long side 130L of the bonding pad 130 . According to some embodiments of the present disclosure, there may be an included angle θ between the extension direction L1 and the extension direction L2. If the first electronic unit 110 and the bonding pad 130 are not parallel to each other, the included angle θ may not be equal to 0. In some embodiments, the included angle θ may be greater than or equal to 0. In some embodiments, the angle θ may be less than 45°, such that 0

θ<45°, but the present disclosure is not limited to this. According to some embodiments, the included angle θ may be greater than or equal to 0 and less than 15°, but the disclosure is not limited thereto. For example, the included angle θ can be detected through an automatic optical system (Auto-Optical Inspection, AOI). When the included angle θ is greater than or equal to 0 and less than 45°, for example, it is beneficial to improve the electrical reliability between electronic units. However, the present disclosure Not limited to this.

In some implementations, bond pad 130 may include conductor layer 131 (shown in Figure 5A). The conductor layer 131 may include a metal conductive material or a non-metal conductive material with low resistance, such as copper, nickel, gold, silver, tin, transparent conductive material, other suitable materials, or a combination of the above and other conductive materials that can be used for packaging, but This disclosure is not limited to this. The transparent conductive material may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO), but the present disclosure is not limited thereto. In some implementations, a suitable process may be used to form the conductor layer 131 . Suitable processes may include, for example, electroplating processes, coating processes, other suitable processes, or combinations thereof, but the disclosure is not limited thereto. The bonding pad 130 of the present disclosure can be used as an auxiliary conductive circuit in an area, so that two electronic units can be electrically connected through the bonding pad 130 used as a connecting component. The bonding pad 130 may include, for example, a quadrangular, circular or other shape, but the disclosure is not limited thereto. Viewed from a top view, the bonding pad 130 may, for example, include arcuate edges or arcuate corners, or may be in a grid shape, or in various other embodiments. By arranging the bonding pad 130 with an arc edge or an arc corner, for example, the tip discharge effect can be reduced, which is beneficial to improving the reliability of the electronic device, but the disclosure is not limited thereto.

Next, as shown in FIGS. 1 to 6 , an insulating layer 140 can be provided on the upper surface 101S of the substrate 101 . For example, in some embodiments, the insulating layer 140 may be provided such that the insulating layer 140 surrounds the first electronic unit 110 , the second electronic unit 120 and the bonding pad 130 . In other words, the insulating layer 140 may be disposed corresponding to the first electronic unit 110 , the second electronic unit 120 and the bonding pad 130 . According to some embodiments of the present disclosure, the above "corresponding... arrangement" may mean that the insulating layer 140 directly contacts at least part of the corresponding component, for example, in the top view, directly contacts the first electronic unit 110 or the second electronic unit 120 The way the setting is arranged on at least one side. According to some embodiments, the insulating layer 140 surrounds the first electronic unit 110 , the second electronic unit 120 and the bonding pad 130 . For example, in the cross-sectional view, the insulating layer 140 directly contacts the first electronic unit 110 , the second electronic unit 120 and the bonding pad 130 At least two sides of the setting are arranged in such a way. The insulating layer 140 may be a soft film, powder or liquid encapsulating material before being provided. For example, it may include a pre-polymerized epoxy encapsulating material, but the present disclosure is not limited thereto. After curing the pre-polymerized epoxy encapsulation material, the cured insulating layer 140 may be formed, but the present disclosure is not limited thereto. The insulating layer 140 that directly contacts the corresponding component can, for example, help prevent moisture or oxygen from contacting or penetrating the corresponding component, that is, it can improve the weather resistance of the electronic device, but the disclosure is not limited thereto.

Then, as shown in FIGS. 1 to 6 , the insulating layer 140 can be provided on the upper surface 101S of the substrate 101 and then the substrate 101 is turned over so that the upper surface 101S shown in FIG. 2 faces downward. The step of turning over the substrate 101 may also be combined with the step of removing the temporary substrate 101 . If necessary, the steps of turning over the substrate 101 and removing the substrate 101 may be performed separately. For example, in some embodiments, the step of turning over the substrate 101 may be performed first and then the step of removing the substrate 101 may be performed. Alternatively, in some embodiments, the step of removing the substrate 101 may be performed first and then the step of turning the substrate 101 over. After the step of removing the substrate 101 , the bonding terminals 110C of the first electronic unit 110 and the bonding terminals 120C of the second electronic unit 120 may be exposed respectively. According to some embodiments of the present disclosure, the bonding pad 130 may be provided to electrically connect the first electronic unit 110 or the second electronic unit 120. For example, in some embodiments, a bonding pad 130 may be provided. The bonding pads 130 are used to electrically connect the bonding terminals 110C of the first electronic unit 110 and the bonding terminals 120C of the second electronic unit 120 , so that the first electronic unit 110 can be electrically connected to the second electronic unit 120 via the bonding pads 130 .

As shown in FIGS. 1 to 6 , in the top view, a circuit layer 150 may be provided on the insulating layer 140 (shown in FIG. 3 ), so that the first electronic unit 110 can be bonded through the circuit layer 150 on the insulating layer 140 The pad 130 is electrically connected, and the bonding pad 130 can be electrically connected to the second electronic unit 120 through the circuit layer 150 on the insulating layer 140, for example, so that the bonding terminal 110C of the first electronic unit 110 can be electrically connected to the second electronic unit 110 through the bonding pad 130. The second electronic unit 120 engages the terminal 120C. According to some embodiments of the present disclosure, a suitable process may be used to provide the circuit layer 150 as an electrical conductor between the first electronic unit 110 and the second electronic unit 120 . In some embodiments, for example, the circuit layer 150 may be provided by a photolithography process combined with a photolithography process, an electroplating process, a coating process, other suitable processes, or a combination thereof, but the disclosure is not limited thereto.

According to some embodiments of the present disclosure, the circuit layer 150 may include a composite layer structure, for example, may include multiple conductive layers and multiple insulating layers, and the required circuit patterns and distribution, so the circuit layer 150 can be regarded as a circuit redistribution layer. Multi-layer conductive layers and multi-layer insulating layers can be staggered and stacked to form a fan-out panel level packaging (FOPLP). For example, it is beneficial for electronic devices to have higher input/output (I/O) density, or to reduce the number of electronic components. The size of the device. The conductive layer in the circuit layer 150 may include, for example, a first conductive layer 151, a second conductive layer 152 and a stud 153, but the disclosure is not limited thereto. The material of the conductive layer in the circuit layer 150 may include, for example, titanium, copper, electroplated copper, other suitable conductive materials, or combinations thereof, but the disclosure is not limited thereto. On the other hand, the circuit layer 150 may include multiple insulating layers. In FIG. 4 , an insulating layer 159 represents one or more insulating layers in the circuit layer 150 . The multi-layer insulating layer may include, for example, organic materials or inorganic materials. The organic materials or inorganic materials may include, for example, photosensitive polyimide (PSPI), build-up film (ABF), silicon oxide (SiOx), silicon nitride (SiNx), Nitrogen oxidation Silicon (SiOxNy), other suitable insulating materials, or combinations of the above, but the disclosure is not limited thereto. According to some embodiments of the present disclosure, the circuit layer 150 may include components such as transistors, capacitors, resistors, etc., but is not limited thereto. According to some embodiments of the present disclosure, the first electronic unit 110 can be electrically connected to the conductor layer 131 of the bonding pad 130 through the circuit layer 150 on the insulating layer 140 . According to some embodiments of the present disclosure, the conductor layer 131 of the bonding pad 130 can be electrically connected to the second electronic unit 120 through the second conductive layer 152 of the circuit layer 150 . Electronic units such as the first electronic unit 110 or the second electronic unit 120 may be disposed between the circuit layer 150 and the insulating layer 140 , for example.

As shown in FIGS. 1 to 6 , in the top view, a circuit layer 150 is provided so that the first electronic unit 110 can be electrically connected to the bonding pad 130 through the circuit layer 150 on the insulating layer 140 , and the bonding pad 130 can After the circuit layer 150 on the insulating layer 140 is electrically connected to the second electronic unit 120 , the bonding pad 130 may be further divided, so that the bonding pad 130 forms multiple bonding pad regions, for example, divided into independent bonding pads. Area 133, bonding pad area 134, bonding pad area 135. There may be dividing lines 136 between adjacent bond pad areas. According to some embodiments of the present disclosure, a suitable process may be used to separate the bonding pads 130 and form the separation lines 136 , which may include, for example, a laser cutting process, an etching process, other suitable processes, or a combination of the above, but this disclosure does not use this method. is limited.

After the above steps, an electronic device 100 according to some embodiments of the present disclosure can be provided. FIG. 5A illustrates a schematic cross-sectional view of the electronic device 100 according to some embodiments of the present disclosure along line A-A’ in FIG. 5 , where the Z direction is the normal direction of the electronic device 100 . Please refer to FIG. 5 and FIG. 5A together. The electronic device 100 according to some embodiments of the present disclosure may include a first electronic unit 110, a second electronic unit 120, a bonding pad 130, an insulating layer 140 (FIG. 5A) and a circuit layer 150.

The first electronic unit 110 or the second electronic unit 120 may include passive components and active components respectively. Please refer to the foregoing content for details. The bonding pad 130 may be disposed between the first electronic unit 110 and the second electronic unit 120 . According to some embodiments of the present disclosure, the bonding pad 130 may include a plurality of bonding pad areas that are not connected to each other or are electrically insulated from each other, for example, may include a plurality of bonding pad areas that are independently arranged from each other. 133. Bonding pad area 134, bonding pad area 135, but the present disclosure is not limited thereto. There may be a dividing line 136 between adjacent bonding pad areas so that adjacent bonding pad areas are not connected, but the disclosure is not limited thereto. In some embodiments, the bonding pad 130 may at least include a conductor layer 131, and the conductor layer 131 may include a metallic conductive material or a non-metal conductive material with low resistance, such as copper, aluminum, titanium, molybdenum, nickel, gold, silver, Tin, transparent conductive materials, other suitable materials, or combinations thereof may be used as conductive materials for packaging, but the disclosure is not limited thereto. The transparent conductive material may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO), but the present disclosure is not limited thereto. In some embodiments, the bonding pad 130 may further include a base layer 132 such that the conductor layer 131 may be disposed on the base layer 132 and the base layer 132 may be disposed between the conductor layer 131 and the insulating layer 140 . The base layer 132 may, for example, make the bottom layer of the bonding pad 130 close to the material properties of the insulating layer 140 so that the bonding pad 130 is easily integrated with the insulating layer 140 . The base layer 132 may include organic materials or inorganic materials, such as silicon, glass, ceramics, plastics, other suitable materials, or combinations thereof, but the disclosure is not limited thereto. In some embodiments, a suitable process may be used to form the conductor layer 131, which may include, for example, an electroplating process, a coating process, other suitable processes, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, in the schematic cross-sectional view, such as FIG. 5A , the base layer 132 may have at least one arc-shaped lead angle C, but it is not limited thereto. Through the design of the base layer 132 having an arc-shaped lead angle, the risk of cracking at the interface with the insulating layer 140 can be reduced, but is not limited to this. In some embodiments, the Young's coefficient of the base layer 132 may range from 1000 MPa to 20000 MPa, for example, but the present disclosure is not limited thereto. In some embodiments, the coefficient of thermal expansion (CTE) of the base layer 132 may range from 3 ppm/°K to 10 ppm/°K, for example, but the disclosure is not limited thereto. The base layer 132 having the above properties can make the bonding pad 130 including the base layer 132 have the advantage of having material properties close to those of the insulating layer 140, so that the bonding pad 130 can be easily integrated with the insulating layer 140. In other words, through the arrangement of the base layer 132 , the risk of cracking between the bonding pad 130 and the insulating layer 140 can be reduced.

θ<45°，但本揭露不以此為限。根據一些實施例，夾角θ可以大於等於0且小於15°，但本揭露不以此為限。舉例而言，可透過自動光學系統(Auto-Optical Inspection,AOI)檢測夾角θ，當夾角θ大於等於0且小於45°時，將有利於提升電子單元之間的電性可靠度。其中，接合墊區域133的側邊、接合墊區域134的側邊、接合墊區域135的側邊與接合墊130的長邊130L具有相同延伸方向。透過接合墊130具有弧形邊緣或弧形轉角的設置，例如可降低尖端放電效應，有利於提升電子裝置可靠度，但本揭露不以此為限。 As shown in FIGS. 1 to 6 , the bonding pad 130 includes a bonding pad area 133 , a bonding pad area 134 , and a bonding pad area 135 . The extension line L1 passes through one side of the bonding pad area 133 , the bonding pad area 134 , and the bonding pad area 135 . , the edge 110L on the side of the first electronic unit 110 close to the bonding pad areas 133 , 134 , and 135 may have an extension line L2 . There may be an included angle θ between the extension line L1 and the extension line L2. If the first electronic unit 110 and the bonding pad 130 are not parallel to each other, the included angle θ may not be equal to 0. According to some embodiments of the present disclosure, the included angle θ may be greater than or equal to 0. In some embodiments, in consideration of reliability, the included angle θ may be less than 45°, for example, such that 0

θ<45°, but the present disclosure is not limited to this. According to some embodiments, the included angle θ may be greater than or equal to 0 and less than 15°, but the disclosure is not limited thereto. For example, the included angle θ can be detected through an automatic optical system (Auto-Optical Inspection, AOI). When the included angle θ is greater than or equal to 0 and less than 45°, it will help improve the electrical reliability between electronic units. The sides of the bonding pad region 133 , the sides of the bonding pad region 134 , and the sides of the bonding pad region 135 have the same extending direction as the long side 130L of the bonding pad 130 . By arranging the bonding pad 130 with an arc edge or an arc corner, for example, the tip discharge effect can be reduced, which is beneficial to improving the reliability of the electronic device, but the disclosure is not limited thereto.

The bonding pad 130 of the present disclosure may be implemented in a variety of different ways. 6, 6A, and 6B respectively illustrate partial top views of different embodiments of the bonding pad 130 of FIG. 5 according to the present disclosure, in which the extension line L1 is parallel to the Y direction, the X direction is perpendicular to the Y direction, and the X direction is perpendicular to the Y direction. The direction and the Y direction are respectively perpendicular to the Z direction shown in Figure 5A. As shown in FIG. 6 , in some embodiments, the bonding pad 130 of the present disclosure may have the shape of a solid structure. That is to say, the bonding pad 130 of the present disclosure may be a whole piece of linear pattern or a whole piece of rectangular conductive material. Have generally smooth sides or curved corners. Multiple bonding pad areas can be patterned according to requirements, but the present disclosure is not limited to this. Or as shown in FIG. 6A , in some embodiments, the bonding pad 130 of the present disclosure may have the shape of a hollow structure, that is to say, the bonding pad 130 of the present disclosure may be provided with a grid pattern. For example, the bonding pad 130 may be composed of multiple parts, such as a nearly rectangular or square rim part P1, a strip-shaped part P2 with a first oblique direction, and a long part P2 with a second oblique direction R. Bar-shaped part P3. The first diagonal direction and the second diagonal direction The direction R is substantially orthogonal but not parallel to the extension direction L1 of the bonding pad 130 , so that the portion P2 and the portion P3 can be interspersed and an opening 137 is formed between the portion P2 and the portion P3 . The opening 137 may expose the base layer 132 (see FIG. 5A ) located below the conductor layer 131 , or expose the insulating layer 140 (see FIG. 5A ) located below the base layer 132 (see FIG. 5A ). Or as shown in FIG. 6B , in some embodiments, the bonding pad 130 of the present disclosure may have a striped shape. That is to say, the bonding pad 130 of the present disclosure may be provided with alternately arranged bonding pad areas 133 and bonding pads. The area 134, the bonding pad area 135 and the dividing line 136 are such that adjacent bonding pad areas are separated by the dividing line 136 and are aligned in front of the extension direction L1. Bond pad 130 may include electrically controllable disconnection. For example, the bonding pad 130 of the controlled current fuse portion may be formed into a plurality of bonding pad areas separated by the dividing lines 136 . A single bonding pad area can be used as a bonding terminal (see Figure 5 ) corresponding to the first electronic unit 110 (see Figure 5 ) and a bonding terminal (see Figure 5 ) of the second electronic unit 120 (see Figure 5 ). island of single electrical connection.

T2。透過上述設置，可降低因厚度差異過大時，電路層轉層的風險，但不以此為限。 As shown in FIG. 5A , the first electronic unit 110 or the second electronic unit 120 may respectively have an appropriate electronic unit thickness. The electronic unit thickness of the first electronic unit 110 may be calculated from the top surface 110T of the first electronic unit 110 to the bottom surface 110S of the first electronic unit 110 along the normal direction (Z direction) of the electronic device 100 vertical distance. Similarly, the electronic unit thickness of the second electronic unit 120 may be calculated as the vertical distance from the top surface 120T of the second electronic unit 120 to the bottom surface 120S of the second electronic unit 120 along the normal direction of the electronic device 100 . The thickness of the bonding pad 130 may be calculated as the vertical distance from the surface 131S of the bonding pad 130 , which may be a top surface, along its normal direction to the bottom surface of the bonding pad 130 . If the electronic unit thickness of the first electronic unit 110 and the electronic unit thickness of the second electronic unit 120 are different, the maximum electronic unit thickness of the first electronic unit 110 and the second electronic unit 120 is called the maximum thickness T1 (the first electronic unit is shown in the figure) The unit 110 has a maximum thickness T1 (but the present disclosure is not limited thereto), and the thickness of the bonding pad is T2. According to some embodiments of the present disclosure, the thickness of the electronic unit and the thickness of the bonding pad 130 can satisfy T1

T2. Through the above settings, the risk of circuit layer transfer when the thickness difference is too large can be reduced, but it is not limited to this.

(H1/H2)

1.1。 The insulation layer 140 may include a first part 1401, a second part 1402, and a third part 1403. The first part 1401 corresponds to the first electronic unit 110, the second part 1402 corresponds to the second electronic unit 120, and the third part 1403 corresponds to the bonding pad 130. The first part 1401, the second part 1402, and the third part 1403 may have appropriate heights respectively. The height corresponding to the first part 1401 of the first electronic unit 110 may be calculated from the top surface 110T of the first electronic unit 110 to the bottom surface 140B of the insulating layer 140 along the normal direction (Z direction) of the electronic device 100 vertical distance. The height of the second portion 1402 corresponding to the second electronic unit 120 may be a vertical direction from the top surface 120T of the second electronic unit 120 to the bottom surface 140B of the insulating layer 140 along the normal direction (Z direction) of the electronic device 100 distance. The height of the third portion 1403 corresponding to the bonding pad 130 may be a vertical distance from the surface 131S of the bonding pad 130 to the bottom surface 140B of the insulating layer 140 along the normal direction (Z direction) of the electronic device 100 . The height corresponding to the third portion 1403 of the bonding pad 130 is H1. If the height of the first part 1401 corresponding to the first electronic unit 110 and the height of the second part 1402 corresponding to the second electronic unit 120 are different, then the maximum height of the first part 1401 and the second part 1402 is called the maximum height H2. For example, in some embodiments, the height of the third portion 1403 is not significantly different from the maximum height of the first portion 1401 or the second portion 1402. According to some embodiments of the present disclosure, the height H1 of the third part 1403 and the maximum height H2 of the first part 1401 or the second part 1402 may satisfy 0.9

(H1/H2)

1.1.

A circuit layer 150 is disposed on the insulating layer 140 so that the first electronic unit 110 can be electrically connected to the bonding pad 130 through the circuit layer 150 on the insulating layer 140 . In addition, the bonding pad 130 can be electrically connected to the second electronic unit 120 through the circuit layer 150 on the insulating layer 140 . Circuit layer 150 may include a composite layer structure. The circuit layer 150 of the composite layer structure may include multiple conductive layers and multiple insulating layers (represented by the insulating layer 159), wherein the circuit layer 150 may include at least a first conductive layer 151, a second conductive layer 152, and an end shaft 153 (stud). , but this disclosure is not limited to this. Multi-layer conductive layers and multi-layer insulating layers can be staggered and stacked to form fan-out panel level packaging (FOPLP), which is beneficial to electronic devices with higher input/output (I/O) density, or can reduce the number of electronic components. The size of the device.

(W/2)，有利於電子裝置100的電性絕緣。 The distance between the first conductive layer 151 and the second conductive layer 152 is d. The distance d can be calculated as the minimum distance between the first conductive layer 151 and the second conductive layer 152 that are in contact with the same bonding pad 130 . For example, in a top view, the distance d is the minimum distance between an end point of the first conductive layer 151 and an end point of the second conductive layer 152 . The first conductive layer 151 or the second conductive layer 152 may respectively have an appropriate conductive layer width. The conductive layer width of the first conductive layer 151 may be calculated as the minimum distance in the vertical direction along the extension direction of the first conductive layer 151 itself. For the calculation method of the conductive layer width of the second conductive layer 152, please refer to the calculation method of the conductive layer width of the first conductive layer 151 mentioned above. If the conductive layer width of the first conductive layer 151 and the second conductive layer 152 are different, the maximum conductive layer width of the first conductive layer 151 and the second conductive layer 152 is called the maximum width W. For example, in some embodiments, for the sake of electrical insulation, there may be an appropriate distance d between the first conductive layer 151 and the second conductive layer 152 . According to some embodiments of the present disclosure, the maximum width W and spacing d can satisfy d

(W/2), which is beneficial to the electrical insulation of the electronic device 100 .

According to some embodiments of the present disclosure, the first conductive layer 151 of the circuit layer 150 may simultaneously contact at least a portion of the top surface 110T of the first electronic unit 110 , at least a portion of the surface 140S of the insulating layer 140 , and the surface 131S of the conductor layer 131 At least part of it allows the first electronic unit 110 to be electrically connected to the conductor layer 131 of the bonding pad 130 through the circuit layer 150 on the insulating layer 140 . According to some embodiments of the present disclosure, the second conductive layer 152 of the circuit layer 150 may simultaneously contact at least a portion of the top surface 120T of the second electronic unit 120, at least another portion of the surface 140S of the insulating layer 140, and the surface 131S of the conductor layer 131. At least another part of the conductor layer 131 of the bonding pad 130 can be electrically connected to the second electronic unit 120 through the second conductive layer 152 of the circuit layer 150 . In other words, the first electronic unit 110 may be bonded to the second electronic unit 120 via electrical connection to the bonding pad 130 .

According to the manufacturing method of the semiconductor device according to the embodiment of the present disclosure, a connection component (such as the bonding pad in the above embodiment) can be disposed between two adjacent semiconductor units of the electronic device. To reduce the electrical reliability problem of difficulty in normal mutual electrical connection due to positional deviation of semiconductor units. This connection component has the advantage of improving the reliability of the electronic device, for example, improving the electrical reliability of the electronic device.

The above are only embodiments of the present disclosure, and all equivalent changes and modifications made based on the patent scope of the present disclosure shall be within the scope of the present disclosure.

100: Electronic devices

110:First electronic unit

110S: Bottom surface

110T: Top surface

120: Second electronic unit

120S: Bottom surface

120T:Top surface

130:Joining pad

131: Conductor layer

131S:Surface

132: Basal layer

140:Insulation layer

1401:Part 1

1402:Part 2

1403:Part 3

140B: Bottom surface

140S: Surface

150:Circuit layer

151: First conductive layer

152: Second conductive layer

153: End shaft

159:Insulation layer

H1: height

H2: Maximum height

C: Arc lead angle

Claims (19)

An electronic device includes: a first electronic unit and a second electronic unit; a bonding pad disposed between the first electronic unit and the second electronic unit. In a top view, an extension of the bonding pad The direction has an included angle θ with an extending direction of an edge of the first electronic unit close to the bonding pad, and 0

θ<45°; an insulating layer corresponding to the first electronic unit, the second electronic unit and the bonding pad; and a circuit layer; wherein the first electronic unit is electrically connected to the bonding pad through the circuit layer the second electronic unit. As in the electronic device of claim 1, the bonding pad further includes: a base layer; and a conductor layer disposed on the base layer. The electronic device of claim 2, wherein the circuit layer includes a first conductive layer that contacts at least a portion of a surface of the first electronic unit, at least a portion of a surface of the insulating layer and the conductor layer at least part of a surface. The electronic device of claim 3, wherein the circuit layer includes a second conductive layer that contacts at least a portion of a surface of the second electronic unit, at least another portion of the surface of the insulating layer and the conductor at least another portion of the surface of the layer. The electronic device of claim 2, wherein the base layer includes at least one arc-shaped lead angle. The electronic device of claim 1, wherein the circuit layer includes a first conductive layer and a second conductive layer, the distance between the first conductive layer and the second conductive layer is d, and the first conductive layer and the second conductive layer The maximum width of one of the second conductive layers is W, and d

(W/2). The electronic device of claim 1, wherein the maximum thickness of one of the first electronic unit and the second electronic unit is T1, the thickness of the bonding pad is T2, and T1

T2. The electronic device of claim 1, wherein the insulating layer includes a first part, a second part and a third part, the first part corresponds to the first electronic unit, the second part corresponds to the second electronic unit, and the third part Three parts correspond to the bonding pad, the height of the third part is H1, the maximum height of one of the first part and the second part is H2, and 0.9

(H1/H2)

1.1. The electronic device of claim 1, wherein the bonding pad includes a plurality of bonding pad areas that are not connected to each other. A method of forming an electronic device, including: providing a substrate including a bonding pad, a first electronic unit and a second electronic unit; and providing an insulating layer on the substrate, wherein the insulating layer is configured to correspond to the bonding pad, the first electronic unit and the second electronic unit; wherein, the bonding pad is disposed between the first electronic unit and the second electronic unit, and the bonding pad electrically connects the first electronic unit and the third electronic unit. Two electronic units. The method of forming an electronic device according to claim 10, wherein the bonding pad is first provided on the base On the board, the first electronic unit and the second electronic unit are provided on the substrate. As in the method of forming an electronic device of claim 10, the first electronic unit and the second electronic unit are first provided on the substrate, and then the bonding pad is provided on the substrate. The method of forming an electronic device of claim 10 further includes: laser cutting the bonding pad to form a plurality of bonding pad regions. The method of forming an electronic device according to claim 10, wherein an extending direction of the bonding pad and an extending direction of an edge of the first electronic unit close to the bonding pad have an included angle θ, and 0

θ<45°. The method of forming an electronic device according to claim 10 further includes: providing a circuit layer on the insulating layer, and the first electronic unit is electrically connected to the second electronic unit through the circuit layer and the bonding pad. The method of forming an electronic device as claimed in claim 15, wherein the bonding pad includes a conductor layer, the circuit layer includes a first conductive layer, the first conductive layer contacts at least a portion of a surface of the first electronic unit, the insulation At least a portion of a surface of the layer and at least a portion of a surface of the conductive layer. The method of forming an electronic device according to claim 15, wherein the circuit layer includes a first conductive layer and a second conductive layer, the distance between the first conductive layer and the second conductive layer is d, and the first conductive layer The maximum width of one of the layer and the second conductive layer is W, and d

(W/2). The method of forming an electronic device of claim 10, wherein the maximum thickness of one of the first electronic unit and the second electronic unit is T1, the thickness of the bonding pad is T2, and T1

T2. The method of forming an electronic device as claimed in claim 10, wherein the insulating layer includes a first part, a second part and a third part, the first part corresponding to the first electronic unit, and the second part corresponding to the second electronic unit , the third part corresponds to the bonding pad, the height of the third part is H1, the maximum height of one of the first part and the second part is H2, and 0.9

(H1/H2)

1.1.