[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

TWI623058B - 具有複數個接觸插塞的裝置及其製造方法 - Google Patents

具有複數個接觸插塞的裝置及其製造方法 Download PDF

Info

Publication number
TWI623058B
TWI623058B TW106119513A TW106119513A TWI623058B TW I623058 B TWI623058 B TW I623058B TW 106119513 A TW106119513 A TW 106119513A TW 106119513 A TW106119513 A TW 106119513A TW I623058 B TWI623058 B TW I623058B
Authority
TW
Taiwan
Prior art keywords
contact plug
source
dielectric layer
gate
interlayer dielectric
Prior art date
Application number
TW106119513A
Other languages
English (en)
Other versions
TW201839906A (zh
Inventor
王朝勳
楊復凱
王美勻
趙高毅
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Application granted granted Critical
Publication of TWI623058B publication Critical patent/TWI623058B/zh
Publication of TW201839906A publication Critical patent/TW201839906A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Geometry (AREA)

Abstract

複數個接觸插塞的製造方法包括形成電晶體，其包含形成源極/汲極區於虛擬閘極堆疊的一側，形成第一層間介電層覆蓋源極/汲極區，以及以取代閘極堆疊取代虛擬閘極堆疊。方法包括形成第二層間介電層於第一層間介電層以及取代閘極堆疊上方，以及形成電性耦合至源極/汲極區的下源極/汲極接觸插塞。第三層間介電層形成於第二層間介電層上方。閘極接觸插塞形成於第二層間介電層和第三層間介電層中。上源極/汲極接觸插塞被形成以重疊並接觸下源極/汲極接觸插塞。上源極/汲極接觸插塞和閘極接觸插塞係由不同材料所形成。

Description

具有複數個接觸插塞的裝置及其製造方 法
本揭露是有關於一種複數個接觸插塞的製造方法，且特別是有關於一種根據各個接觸插塞的需求，例如：深寬比或電阻率，製造複數個接觸插塞的方法。
在電晶體製造中，金屬被用以形成接觸插塞和金屬閘極。接觸插塞被用來連接至電晶體的源極和汲極區以及閘極。
在形成接觸插塞的一般製造製程中，第一源極/汲極接觸插塞係形成於第一層間介電層中，且第一源極/汲極接觸插塞電性連接至源極/汲極區。然後，形成接觸蝕刻停止層和第二層間介電層，以及形成閘極接觸開口並延伸至第二層間介電層、接觸蝕刻停止層和第一層間介電層中，以暴露出下方的金屬閘極。源極/汲極接觸開口也形成並延伸至第二層間介電層和接觸蝕刻停止層中，以暴露出第一源極/汲極接觸插塞。然後，以導電材料填充閘極接觸開口和源極/汲極接觸開口，以形成閘極接觸插塞和第二源極/汲極接 觸插塞。在此製程中所形成的接觸插塞可能有空洞形成於其中的困擾，特別是具有高深寬比的閘極接觸插塞。
根據本揭露之一些實施例，方法包括形成電晶體，其包含形成源極/汲極區於虛擬閘極堆疊的一側，形成第一層間介電層覆蓋源極/汲極區，以及以取代閘極堆疊取代虛擬閘極堆疊。上述方法更包括形成第二層間介電層於第一層間介電層以及取代閘極堆疊上方，以及形成下源極/汲極接觸插塞，所述下源極/汲極接觸插塞電性耦合至源極/汲極區。下源極/汲極接觸插塞穿過第一層間介電層和第二層間介電層。第三層間介電層形成於第二層間介電層上方。閘極接觸插塞形成於第二層間介電層和第三層間介電層中。上源極/汲極接觸插塞被形成以重疊並接觸下源極/汲極接觸插塞。上源極/汲極接觸插塞穿過第三層間介電層。上源極/汲極接觸插塞和閘極接觸插塞係由不同材料所形成。
根據本揭露之一些實施例，方法包括形成具有閘極堆疊以及位於閘極堆疊之一側的源極/汲極區之電晶體，其中閘極堆疊位於第一層間介電層中；以及，形成下源極/汲極接觸插塞，所述下源極/汲極接觸插塞電性耦合至源極/汲極區。在第一製程操作中，閘極接觸插塞被形成於閘極堆疊上方並接觸閘極堆疊。在第二製程操作中，上源極/汲極接觸插塞被形成以重疊並接觸下源極/汲極接觸插塞。蝕刻停止層係形成於上源極/汲極接觸插塞和閘極接觸插塞 上方，並接觸上源極/汲極接觸插塞和閘極接觸插塞。
根據本揭露之一些實施例，裝置包括第一層間介電層、於第一層間介電層中的閘極堆疊、於第一層間介電層上方的第二層間介電層、相鄰於閘極堆疊的源極/汲極區域，以及位於源極/汲極區域上方並耦合至源極/汲極區域的下源極/汲極接觸插塞。下源極/汲極接觸插塞穿過第一層間介電層和第二層間介電層。上源極/汲極接觸插塞位於下源極/汲極接觸插塞上方並接觸下源極/汲極接觸插塞。閘極接觸插塞位於閘極堆疊上方並接觸閘極堆疊。上源極/汲極接觸插塞以及閘極接觸插塞係由不同材料所形成。
10‧‧‧晶圓
20‧‧‧基材
22‧‧‧淺溝渠隔離區
22A‧‧‧頂表面(等高線)
24‧‧‧半導體條
24’‧‧‧突出鰭
30‧‧‧虛擬閘極堆疊
32‧‧‧虛擬閘極介電層
34‧‧‧虛擬閘極電極
36‧‧‧硬式罩幕層
38、50‧‧‧閘極間隙壁
38A‧‧‧低介電常數介電層
38B‧‧‧非低介電常數介電層
40‧‧‧凹陷
41‧‧‧磊晶區
42‧‧‧源極/汲極區
46、68、96‧‧‧層間介電層
47‧‧‧接觸蝕刻停止層
48‧‧‧溝渠
50A、50B‧‧‧子層
52‧‧‧閘極介電層
54‧‧‧界面層
56‧‧‧高介電常數層
58‧‧‧堆疊層
60‧‧‧金屬材料
62‧‧‧金屬閘極電極
64‧‧‧取代閘極堆疊
70‧‧‧金屬硬式罩幕
72‧‧‧墊氧化層
74‧‧‧光阻
76、78、98、108‧‧‧開口
80‧‧‧介電層
82‧‧‧接觸間隙壁
84‧‧‧金屬層
86、102A、110‧‧‧阻障層
88‧‧‧矽化物區
90‧‧‧金屬性材料
92、114‧‧‧源極/汲極接觸插塞
94、122‧‧‧蝕刻停止層
102‧‧‧導電材料
102B‧‧‧金屬性材料
104‧‧‧閘極接觸插塞
106‧‧‧虛線
112‧‧‧含金屬材料
124‧‧‧金屬間介電層
126、130‧‧‧金屬線
128、132‧‧‧接觸窗
200‧‧‧方法
202、204、206、208、210、212、214、216、218、220、222‧‧‧操作
W1、W2、W3‧‧‧寬度
A-A‧‧‧線段
藉由以下詳細說明並配合圖式閱讀，可更容易理解本揭露。在此強調的是，按照產業界的標準做法，各種特徵並未按比例繪製，僅為說明之用。事實上，為了清楚的討論，各種特徵的尺寸可任意放大或縮小。
[圖1]至[圖26]為根據一些實施例之形成電晶體的中間製程的立體圖和剖面圖。
[圖27]係根據一些實施例繪示形成電晶體和接觸插塞的製程流程圖。
下面的揭露提供了許多不同的實施例或例示，用於實現本揭露的不同特徵。部件和安排的具體實例描述如 下，以簡化本揭露之揭露。當然，這些是僅僅是例示並且不意在進行限制。例如，在接著的說明中敘述在第二特徵上方或上形成第一特徵可以包括在第一和第二特徵形成直接接觸的實施例，並且還可以包括一附加特徵可以形成第一特徵的形成第一和第二特徵之間的實施例，從而使得第一和第二特徵可以不直接接觸。此外，本公開可以在各種例示重複元件符號和/或字母。這種重複是為了簡化和清楚的目的，並不在本身決定所討論的各種實施例和/或配置之間的關係。
此外，空間相對術語，如“之下”、“下方”、“低於”、“上方”、“高於”等，在本文中可以用於簡單說明如圖中所示元件或特徵對另一元件(多個)或特徵(多個特徵)的關係。除了在圖式中描述的位向，空間相對術語意欲包含元件使用或步驟時的不同位向。元件可以其他方式定位(旋轉90度或者在其它方位)，並且本文中所使用的相對的空間描述，同樣可以相應地進行解釋。
根據許多示範的實施例提供電晶體及其製造方法。根據許多實施例繪示製造電晶體的中間製程。一些實施例的一些變化將於下述討論。在許多圖式和繪示的實施例中，相似的元件符號係用來指定相似的元件。在所繪示的示範實施例中，鰭狀場效電晶體(FinFET)的形成係用以說明本揭露之概念。然而，平面電晶體也可採用本揭露之概念。
圖1至圖26根據本揭露之一些實施例繪示形成鰭狀場效電晶體之中間製程的立體圖和剖面圖。圖1至圖26的操作也可示意地反映於圖27的製程流程圖中。
圖1繪示初始結構的立體圖。初始結構包括晶圓10，其更包括基材20。基材20可為半導體基材，其可為矽基材、矽鍺基材或其他半導體材料所形成之基材。基材20可被p型雜質或n型雜質所摻雜。可形成如淺溝渠隔離區(STI)之隔離區22，並從基材20的頂面延伸至基材20中。於相鄰淺溝渠隔離區22之間的部分基材20可視為半導體條24。在一些示範的實施例中，半導體條24的頂面和淺溝渠隔離區22的頂面可實質為彼此等高。
淺溝渠隔離區22可包括襯氧化層(liner oxide；未繪示)，其可為基材20之表面層經熱氧化後所形成的熱氧化物。襯氧化層也可為沉積的氧化矽層，其例如使用原子層沉積、高密度電漿化學氣相沉積或化學氣相沉積來形成。淺溝渠隔離區22也可包括位於襯氧化層上方的介電材料，其中所述介電材料可使用可流動化學氣相沉積、旋轉塗佈或類似製程來形成。
請參考圖2，淺溝渠隔離區22被凹陷，使得半導體條24的上部分突出，並高於淺溝渠隔離區22的頂面，以形成突出鰭24’。位於淺溝渠隔離區22中的半導體條24之一部分仍視為半導體條。可使用乾式蝕刻製程進行上述蝕刻，其中氟化氫(HF3)和氨氣(NH3)可做為蝕刻氣體。在蝕刻製程中，可產生電漿。氬氣也可包括於其中。根據本揭露一些其他的實施例，凹陷淺溝渠隔離區22可使用濕式蝕刻製程來進行。而蝕刻化學物質可例如包括氫氟酸(HF)。
請參考圖3，虛擬閘極堆疊30形成於突出鰭24’ 的頂表面和側壁上。需明白的是，雖然為清楚說明而繪示二個虛擬閘極堆疊30，但可形成單一個或多於二個的虛擬閘極堆疊，每個虛擬閘極堆疊彼此平行，而複數個虛擬閘極堆疊與相同的一或多個半導體鰭24’相交。虛擬閘極堆疊30可包括虛擬閘極介電層32和位於虛擬閘極介電層32上方的虛擬閘極電極34。虛擬閘極電極34可例如由多晶矽形成，且也可使用其他材料來形成。每個虛擬閘極堆疊30也可包括一(或複數個)硬式罩幕層36，所述硬式罩幕層36位於個別的虛擬閘極電極34上方。硬式罩幕層36可由氮化矽、碳氮化矽(silicon carbo-nitride)或其類似物所形成。虛擬閘極堆疊30也具有垂直於縱向之突出鰭24’的縱向方向。
接下來，閘極間隙壁38形成於虛擬閘極堆疊30的側壁上。根據本揭露的一些實施例，閘極間隙壁38由如碳氮化矽(SiCN)、氮化矽或其類似物之介電材料所形成，且閘極間隙壁38可具有單層結構或包含複數個介電層的多層結構。
根據一些實施例，每個閘極間隙壁38包括低介電常數介電層38A和非低介電常數介電層38B，每個低介電常數介電層38A和非低介電常數介電層38B之形成是透過毯覆式沉積操作與之後的非等向性蝕刻操作。低介電常數介電層38A可由具有介電常數(k值)低於約3.5的低介電常數材料形成，並可藉由形成具有孔洞形成於其中的氮氧化矽(SiON)或氧碳氮化矽(SiOCN)，減少低介電常數介電層38A的k值，以達到預定的低介電常數值。非低介電常數介 電層38B可例如由氮化矽形成。
接下來進行蝕刻操作(相當於後述凹陷源極/汲極之操作)，以蝕刻未被虛擬閘極堆疊30和閘極間隙壁38覆蓋的突出鰭24’之一部分，而造成如圖4所示之結構。凹陷可為非等向性，因此位於虛擬閘極堆疊30和閘極間隙壁38正下方之突出鰭24’的一部分被保護而不被蝕刻。根據一些實施例，凹陷的半導體條24的頂表面可低於淺溝渠隔離區22的頂表面22A。凹陷40因此形成於淺溝渠隔離區22之間。凹陷40位於虛擬閘極堆疊30之相對側。
接下來，在磊晶操作中藉由選擇性地成長半導體材料於凹陷40中，以形成源極/汲極區，造成如圖5A所示之結構。根據一些示範的實施例，源極/汲極區42包括矽鍺或矽。視所得之鰭狀場效電晶體為p型鰭狀場效電晶體或n型鰭狀場效電晶體，可在磊晶操作進行中原位摻雜p型雜質或n型雜質。例如：當所得之鰭狀場效電晶體為p型鰭狀場效電晶體，可生長矽鍺硼(SiGeB)。相反地，當所得之鰭狀場效電晶體為n型鰭狀場效電晶體，可生長磷化矽(SiP)或碳磷化矽(SiCP)。根據本揭露之其他實施例，磊晶區42可由第III族-第V族之化合物半導體形成，例如砷化鎵(GaAs)、磷化銦(InP)、氮化鎵(GaN)、砷化銦鎵(InGaAs)、砷化銦鋁(InAlAs)、鎵銻(GaSb)、鋁銻(AlSb)、砷化鋁(AlAs)、磷化鋁(AlP)、磷化鎵(GaP)、上述之組合或多層。在源極/汲極區42填滿凹陷40後，源極/汲極區42開始水平地擴張，從而可形成多個小平面 (Facet)。
在磊晶操作後，源極/汲極區42可被進一步地植入p型或n型雜質，以增加源極/汲極區42的雜質濃度。根據本揭露的一些其他實施例，當源極/汲極區42在磊晶製程過程中被原位地摻雜p型或n型雜質時，則可跳過植入操作。源極/汲極區42可包括形成於淺溝渠隔離區22中的下部分，以及形成於淺溝渠隔離區22之頂表面22A上方的上部分。
圖5B根據其他實施例繪示源極/汲極區42之形成，其中突出鰭24’未被凹陷，且磊晶區41磊晶地成長於暴露出的突出鰭24’上。因此，源極/汲極區(其也使用元件符號42來代表)包括磊晶區41以及相對應之突出鰭24’的一部分，上述磊晶區41和突出鰭24’的一部分皆經植入以增加其雜質濃度。
圖6A繪示接觸蝕刻停止層(Contact Etch Stop Layer；CESL)47和層間介電層(Inter-Layer Dielectric；ILD)46被形成時之結構的立體圖。根據本揭露的一些實施例，緩衝氧化層(未繪示)以及接觸蝕刻停止層47被形成於源極/汲極區42上。緩衝氧化層可由氧化矽形成，以及接觸蝕刻停止層47可由氮化矽、碳氮化矽或其類似物來形成。緩衝氧化層和接觸蝕刻停止層47可例如使用原子層沉積之共形沉積方法來形成。層間介電層46可包括使用如可流動式化學氣相沉積、旋轉塗佈、化學氣相沉積或其他適合的沉積方法所形成之介電材料。層間介電層46可 由四乙基正矽酸鹽(Tetra Ethyl Ortho Silicate；TEOS)氧化物、電漿加強化學氣相沉積氧化物(例如SiO2)、磷矽酸玻璃、硼矽酸玻璃、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate glass；BPSG)或其類似物來形成。可進行如化學機械研磨(Chemical Mechanical Polish；CMP)或機械研磨(Mechanical Grinding)之平坦化操作，以使層間介電層46、接觸蝕刻停止層47、虛擬閘極堆疊30以及閘極間隙壁38之頂表面彼此等高。
圖6A所示之結構的剖面圖係繪示於圖6B中，其中剖面圖從包含圖6A之線段A-A的垂直平面所得。在剖面圖中，繪示有複數個虛擬閘極堆疊30中的二個虛擬閘極堆疊，且繪示有形成於相鄰的虛擬閘極堆疊30之間的源極/汲極區42。需說明的是，可形成更多的虛擬閘極堆疊30和源極/汲極區42。此外，根據一些實施例，源極/汲極區42的頂表面可高於虛擬閘極堆疊30的底表面。
接著，以取代閘極堆疊來取代虛擬閘極堆疊30，取代閘極堆疊包括金屬閘極和取代閘極介電層，如圖7至圖10所示。圖7至圖10以及後述圖11至圖26所示之剖面圖都是從圖6A中包含線段A-A之相同的垂直平面所獲得。在圖7至圖26中繪示有淺溝渠隔離區22的頂表面之等高線22A，且半導體鰭24’位於等高線22A上方。
當圖6A和圖6B所示之取代閘極堆疊、硬式罩幕層36、虛擬閘極電極34以及虛擬閘極介電層32先在一或複數個蝕刻操作中被移除，造成圖7中的溝渠/開口48。個 別的操作係繪示如圖27之製程流程圖的操作202。突出半導體鰭24’的頂表面和側壁(未位於所繪示的平面)暴露至溝渠48。
圖8根據一些實施例繪示閘極間隙壁50之形成。個別的操作係繪示如圖27之製程流程圖的操作204。根據其他的實施例，閘極間隙壁50未被形成。為了形成閘極間隙壁50，例如：使用如原子層沉積或化學氣相沉積之沉積方法，來形成一或多個毯覆閘極間隙壁層。毯覆閘極間隙壁層為共形的。根據本揭露的一些實施例，閘極間隙壁係由氮化矽(SiN)、碳化矽(SiC)、氮氧化矽(SiON)、氧碳氮化矽或其他介電材料所形成。毯覆閘極間隙壁層在非等向性蝕刻中被蝕刻以移除水平部分，且剩餘的垂直部分形成閘極間隙壁50。閘極間隙壁50將後續形成的金屬閘極和源極/汲極區更遠地隔開，使得金屬閘極和源極/汲極區之間漏電和電性短路的可能減少。
根據一些實施例，閘極間隙壁50係由低介電常數材料形成，其可具有低於約3.5或3.0之介電常數(k值)。在本說明書中，k值約為3.9的氧化矽(SiO2)被用來區分低k值和高k值。因此，低於3.8的k值被視為低k值，以及個別的介電材料被視為低介電常數材料。相反地，高於3.9的k值被視為高k值，以及個別的介電材料被視為高介電常數材料。例如：閘極間隙壁50可由形成多孔的氮氧化矽(SiON)或氧碳氮化矽(SiOCN)來形成，以具有預定的低k值。低介電常數材料間隙壁50之形成有利於減少後續形成之金屬閘 極和源極/汲極區42之間的寄生電容(Parasitic Capacitance)。
每個閘極間隙壁50可由具有均相介電材料之單一層所形成，或由不同介電材料形成之複數個介電層所形成。例如：閘極間隙壁50可包括由低介電常數材料所形成之子層50A以及由氧化矽或高介電常數材料所形成之子層50B。形成製程包括沉積共形介電層並進行非等向性蝕刻以形成子層50A，然後沉積另一共形介電層並進行另一非等向性蝕刻以形成子層50B。
接下來，請參考圖9，形成(取代)閘極介電層52，其係延伸至溝渠48(圖8)。個別的操作係繪示如圖27之製程流程圖的操作206。根據本揭露的一些實施例，閘極介電層52包括界面層(Interfacial Layer；IL)54做為閘極介電層52的下部分。界面層54形成於突出鰭24’暴露出的表面上。界面層54可包括如氧化矽層之氧化層，其可透過熱氧化突出鰭24’、化學氧化製程或沉積製程來形成。閘極介電層52也可包括形成於界面層54上方的高介電常數層56。高介電常數層56包括如氧化鉿、氧化鑭、氧化鋁、氧化鋯或其類似物之高介電常數材料。高介電常數材料之介電常數(k值)高於3.9，且可高於約7.0。高介電常數層56係位於界面層54上方並可接觸界面層54。高介電常數層56可形成為共形層，並在突出鰭24’的側壁以及閘極間隙壁38/50之頂表面和側壁上延伸。根據本揭露的一些實施例，高介電常數層56使用原子層沉積或化學氣相沉積來形成。
再參考圖9，堆疊層58被沉積。個別的操作係繪示如圖27之製程流程圖的操作208。堆疊層58中的子層並未分開繪示，然而上述子層是可彼此分明的。可使用如原子層沉積或化學氣相沉積之共形沉積方法來進行沉積，使得堆疊層58(以及每個子層)之垂直部分的厚度和水平部分的厚度實質為彼此相同。堆疊層58延伸至溝渠48(圖8)中，且堆疊層58包括位於層間介電層46上方的一些部分。
堆疊層58可包括擴散阻障層和位於上述阻障層上方的一(或多個)功函數層。擴散阻障層可由氮化鈦(TiN)形成，氮化鈦可或可不被矽摻雜。功函數層決定閘極的功函數，且功函數層包括至少一層或不同材料形成的複數層。根據個別的鰭狀場效電晶體為n型鰭狀場效電晶體或p型鰭狀場效電晶體，選擇功函數層的材料。例如：當鰭狀場效電晶體為n型鰭狀場效電晶體時，功函數層可包括氮化鉭(TaN)層和氮化鉭層上方的鈦鋁(TiAl)層。當鰭狀場效電晶體為p型鰭狀場效電晶體時，功函數層可包括氮化鉭層、位於氮化鉭層上方的氮化鈦層以及位於氮化鈦層上方的鈦鋁層。在沉積一或多個功函數層後，形成另一個阻障層，阻障層可為另一層氮化鈦層。
接下來，金屬材料60被沉積，其可例如由鎢或鈷所形成。金屬材料60填滿剩餘的溝渠48(圖8)。在圖10所示之後續操作中，可進行如化學機械研磨或機械研磨之平坦化操作，使得位於層間介電層46上方的高介電常數層56、堆疊層58和金屬材料層60之一部分可被移除。個別的 操作係繪示如圖27之製程流程圖的操作210。因此，金屬閘極電極62被形成，其可包括剩餘部分的堆疊層58和金屬材料層60。剩餘部分的閘極介電層52、堆疊層58和金屬材料層60此後被視為取代閘極堆疊64。如圖10所示，金屬閘極62、間隙壁38/50、接觸蝕刻停止層47和層間介電層46的頂表面在此時可實質為共平面。
根據其他實施例，凹陷閘極堆疊64以形成位於閘極間隙壁38/50之相對部分之間的凹陷，且介電硬式罩幕(如氮化矽，未繪示)填入上述凹陷中，並接著進行平坦化操作，使得介電硬式罩幕、間隙壁38/50、接觸蝕刻停止層47和層間介電層46在此時實質為共平面。
在圖10中，虛線(以64/50標示)繪示為對齊閘極間隙壁50的外緣，以表示閘極間隙壁50和取代閘極堆疊64延伸在所繪示的半導體鰭24’的頂表面下，並延伸在半導體鰭24’的側壁上。虛線代表閘極間隙壁50和取代閘極堆疊64的這些部分並未位於所繪示的平面。此外，雖然未繪示，但閘極間隙壁38也可延伸在半導體鰭24’的側壁上，如圖3所示。
圖11至圖26繪示源極/汲極接觸插塞和閘極接觸插塞之形成。在所繪示的例子中，顯示三個源極/汲極區42，且所繪示的製程中揭露連接至最左邊源極/汲極區域42的源極/汲極接觸插塞之形成。在實際製程中，也可形成連接至中央和最右邊源極/汲極區42的源極/汲極接觸插塞。然而，這些源極/汲極接觸插塞形成於與所繪示之平面不同的 平面，因此不可見。類似地，雖然繪示位於右邊閘極堆疊64的正上方的單一個閘極接觸插塞，但也可有位於左邊閘極堆疊64正上方並連接至左邊閘極堆疊64的閘極接觸插塞，其位於與所繪示的平面不同的平面，因此未顯示於圖中。
請參考圖11，層間介電層68形成於介電罩幕(未繪示)的上方。層間介電層68的材料可選自於與形成層間介電層46相同的候選材料(和方法)，且層間介電層46和層間介電層68可由相同或不同介電材料所形成。例如：層間介電層68可使用電漿加強化學氣相沉積來形成，並可包括氧化矽(SiO2)。層間介電層46和層間介電層68之間可或可不具有可分辨之界面。層間介電層68的厚度可為約700Å至約800Å。
然後，在後續蝕刻中做為蝕刻罩幕的金屬硬式罩幕70形成於層間介電層68上方。金屬硬式罩幕70可由如氮化鈦之金屬氮化物所形成。之後，由氧化矽所形成之墊氧化層72形成於硬式罩幕層70上方。而後，施加並圖案化光阻74，從而形成開口76。
然後，圖案化後的光阻74被用來蝕刻下面的墊氧化層72和金屬硬式罩幕70，使得開口76延伸至金屬硬式罩幕70中。接著，例如於灰化製程中，移除光阻74。然後，剩餘的墊氧化層72和金屬硬式罩幕70被用做蝕刻罩幕，以蝕刻層間介電層68、層間介電層46和接觸蝕刻停止層47，以形成源極/汲極接觸開口78，如圖12所示。個別的操作係繪示如圖27之製程流程圖的操作212。在蝕刻層間介電層68 和層間介電層46中，接觸蝕刻停止層47被用做蝕刻停止層，且接觸蝕刻停止層47接著被蝕刻，以暴露出下面的源極/汲極區42。
請參考圖13，形成介電層80，例如：使用如化學氣相沉積或原子層沉積的共形沉積方法。介電層80可為具有大於3.9之k值的高介電常數層，使得介電層80具有良好的隔離性能。候選材料包括鋁氧化物(AlxOy)、氧化鉿(HfO2)、氮化矽(SiN)以及氧碳氮化矽(SiOCN)(不具有孔洞或內側實質未有孔洞)。介電層80的厚度可為約2nm至約4nm。
之後，進行非等向性蝕刻使得介電層80的水平部分被移除，且在開口78之側壁上剩下的垂直部分形成接觸間隙壁82，當從晶圓10之上方觀察時，接觸間隙壁82形成環。所造成的結構如圖14所示。個別的操作係繪示如圖27之製程流程圖的操作214。根據一些其他實施例，可略過接觸間隙壁82之形成。
圖15至圖18繪示下源極/汲極接觸插塞的形成。個別的操作係繪示如圖27之製程流程圖的操作216。請參考圖15，金屬層84(如鈦層或鈷層)被沉積，例如：使用物理氣相沉積。然後，阻障層86形成於金屬層84上方，阻障層86可為如氮化鈦層或氮化鉭層之金屬氮化物層。可藉由氮化金屬層84之頂層，但保留金屬層84的下層未被氮化而形成阻障層86，或可藉由使用如化學氣相沉積之沉積方法來形成阻障層86。金屬層84和阻障層86都是共形的，並 延伸至開口78中。
然後，進行退火以形成源極/汲極矽化物區88如圖16所示。可透過快速熱退火、加熱爐退火或其類似製程來進行上述退火。因此，金屬層84的下部分與源極/汲極區42反應，以形成矽化物區88。在矽化製程後，金屬層84的側壁部分仍保留。根據本揭露之一些實施例，矽化物區88的頂表面接觸阻障層86的底表面。
接著，如圖17所示，金屬性材料90被沉積於阻障層86上方並與阻障層86接觸。金屬性材料90可選自於與含金屬材料60之候選材料相同的群組，且可包括鎢或鈷。然後進行如化學機械研磨或機械研磨之平坦化製程，以移除位於層間介電層68上方的金屬層84、阻障層86和金屬性材料層90之一部分。所造成的結構如圖18所示，所述結構可包括源極/汲極接觸插塞92。
圖19繪示蝕刻停止層94和層間介電層96的形成。個別的操作係繪示如圖27之製程流程圖的操作218。蝕刻停止層94可由氮化矽、碳化矽、氮氧化矽、碳氮化矽或其類似物所形成，並可使用如化學氣相沉積之沉積方法來形成蝕刻停止層94。層間介電層96可包括選自於磷矽酸玻璃、硼矽酸玻璃、硼摻雜磷矽酸鹽玻璃(BPSG)、氟摻雜矽酸玻璃、四乙基正矽酸鹽氧化物或電漿加強化學氣相沉積氧化物(氧化矽(SiO2))之材料。可使用旋轉塗佈、可流動式化學氣相沉積或其類似方法來形成層間介電層96，或使用如電漿加強化學氣相沉積或低壓化學氣相沉積之沉積方法來 形成層間介電層96。
請參考圖20，層間介電層96和蝕刻停止層94被蝕刻以形成開口98。根據本揭露之一些實施例，開口98具有高深寬比(高度對寬度的比值)，其可大於約4.0或更高。開口可為窄的，使得金屬閘極電極62的表面之第一部分被暴露出來，且金屬閘極電極62的第二部分仍被層間介電層68所覆蓋。在所製得的電晶體之操作過程中，因為金屬閘極電極62被施加電壓，但其不具有電流流經，故金屬閘極電極62和上面的閘極接觸插塞之間的接觸面積可能小而不顯著地影響電晶體的效能。因此，將開口98做窄有利於減少電晶體的尺寸但不犧牲電性效能。
在後續操作中，開口98被填入一或多個導電材料102，如圖21所示。導電材料102具有良好的空隙填充能力，因此導電材料102中不會有空洞(Void)產生。根據一些實施例，導電材料102可由如氮化鈦之金屬氮化物形成，且形成方法可例如包括物理氣相沉積。雖然氮化鈦具有高電阻率(高於金屬)，但高電阻率不顯著地影響電晶體的效能，因為所述電晶體係用來施加電壓而非電流。根據其他的實施例，導電材料102可由如鎢之其他材料所形成。
導電材料102可為均相，且整體導電材料102具有相同組成，且可由均相氮化鈦或均相鎢所形成。在其他實施例中，導電材料102具有複合結構，例如包括：阻障層102A和金屬性材料102B。例如：阻障層102A可由氮化鈦所形成，以及金屬性材料102B可由鎢所形成。導電材料102 不含鈷，因為鈷的空隙填充能力不足，且若以鈷填入開口98(圖20)中，因為個別的開口之高深寬比而使其中可能產生空洞。
根據一些實施例，進行如化學機械研磨或機械研磨的平坦化操作，以移除過多的導電材料102，以形成閘極接觸插塞104，如圖22所示。個別的操作係繪示如圖27之製程流程圖的操作220。閘極接觸插塞104的頂表面因此與介電層96的頂表面共平面。根據一些其他的實施例，進行回蝕製程以移除過多的導電材料102。所得的閘極接觸插塞104之頂表面可因此高於、等高於或低於層間介電層96的頂表面。虛線106示意地繪示當閘極接觸插塞104的頂表面不與層間介電層96之頂表面等高時，閘極接觸插塞104的頂表面之位置。
請參考圖23，層間介電層96和蝕刻停止層94被蝕刻以形成源極/汲極接觸開口108。上述蝕刻操作係藉由進行停止於蝕刻停止層94上的第一階段蝕刻以及停止於源極/汲極接觸插塞92和層間介電層68上的第二階段蝕刻。開口108可具有寬度W1，寬度W1大於下方之源極/汲極接觸插塞92的寬度W2。因此，源極/汲極接觸插塞92的整個頂表面被用來接觸上方的源極/汲極接觸插塞114(圖25)，因此源極/汲極接觸插塞92和源極/汲極接觸插塞114之間的接觸阻抗減少。再者，寬度W1大於閘極接觸插塞104的寬度W3，且寬度W1可為大於寬度W3約1.2倍。W1/W3比值也可為約1.2至2.0。
接著，沉積一或多個導電材料至開口108中，如圖24所示。導電材料110/112與形成閘極接觸插塞104之材料不同。因為開口108具有低深寬比，開口108的空隙填充是簡單的，且導電材料110/112不必具有良好的空隙填充能力。然而，導電材料110/112的電阻率ρ2較佳為低的，以導通源極/汲極電流。電阻率ρ2低於閘極接觸插塞104的電阻率ρ1。
根據形成導電材料110/112的一些實施例，先沉積毯覆阻障層110，接著沉積含金屬材料112於毯覆阻障層110上方。阻障層110可由如氮化鈦或氮化鉭之金屬氮化物形成。含金屬材料112係由選自於鎢、釕、鈷、銅或上述之合金的材料所形成。形成含金屬材料112的方法可選自於化學氣相沉積、物理氣相沉積或其類似製程。根據一些實施例，其中含金屬材料112包含鈷，導電材料102較佳不包括鎢，且導電材料102可由均相氮化鈦所形成。這是因為在如圖25所示之後續的平坦化中，閘極接觸插塞104也被平坦化，例如：使用化學機械研磨。用於鈷之化學機械研磨的漿液可能造成鎢(若使用於閘極接觸插塞104中)的非預定之過度凹陷。
接著，請參考圖25，進行如化學機械研磨或機械研磨之平坦化操作以移除過多的導電阻障層110和含金屬材料112，以形成源極/汲極接觸插塞114。個別的操作係繪示如圖27之製程流程圖的操作222。在本說明書中，源極/汲極接觸插塞92和源極/汲極接觸插塞114分別被視為下 源極/汲極接觸插塞和上源極/汲極接觸插塞。鰭狀場效電晶體120之製造遂完成。
在一些實施例中，其中閘極接觸插塞104(圖22)被凹陷，如虛線106所示，阻障層110的一部分被填入接觸插塞104的凹陷中。含金屬材料112可或可不填入接觸插塞104的凹陷中，其中阻障層110(有或無含金屬材料112)被留下來做為鰭狀場效電晶體120的一部分。
在接續的操作中，形成內連結構。例如：如圖26所示，形成蝕刻停止層122和金屬間介電層(Inter-Metal Dielectric；IMD)124。金屬間介電層124可由低介電常數材料形成。金屬線126和金屬線130可形成於金屬間介電層124中，且金屬線126和金屬線130分別透過接觸窗128和接觸窗132，連接至源極/汲極接觸插塞114和閘極接觸插塞104。
本揭露之實施例具有一些有利的特徵。閘極接觸插塞(104)可具有高於源極/汲極接觸插塞(114)的深寬比，因此在進行閘極接觸插塞92的空隙填充時難以避免空洞。據此，閘極接觸插塞使用具有良好空隙填充能力的材料來形成。然而，閘極接觸插塞的電阻率並非十分限制，因為閘極接觸插塞是用以施加電壓而非用來導通電流。相反地，源極/汲極接觸插塞較佳為低電阻率，因為其係用以導通電流。然而，源極/汲極接觸插塞的空隙填充能力不需十分要求，因為根據本揭露之一些實施例的源極/汲極接觸插塞具有低深寬比。據此，具有低電阻率值的材料被選用來形成源 極/汲極接觸插塞，但源極/汲極接觸插塞之材料的孔隙填充能力並不十分受限。根據本揭露之一些實施例，閘極接觸插塞和源極/汲極接觸插塞係在不同的製程中形成，且係使用不同的材料來形成，以達到其不同的需求。
根據本揭露之一些實施例，方法包括形成電晶體，其包含形成源極/汲極區於虛擬閘極堆疊的一側，形成第一層間介電層覆蓋源極/汲極區，以及以取代閘極堆疊取代虛擬閘極堆疊。上述方法更包括形成第二層間介電層於第一層間介電層以及取代閘極堆疊上方，以及形成下源極/汲極接觸插塞，所述下源極/汲極接觸插塞電性耦合至源極/汲極區。下源極/汲極接觸插塞穿過第一層間介電層和第二層間介電層。第三層間介電層形成於第二層間介電層上方。閘極接觸插塞形成於第二層間介電層和第三層間介電層中。上源極/汲極接觸插塞被形成以重疊並接觸下源極/汲極接觸插塞。上源極/汲極接觸插塞穿過第三層間介電層。上源極/汲極接觸插塞和閘極接觸插塞係由不同材料所形成。
根據本揭露之一些實施例，方法包括形成具有閘極堆疊以及位於閘極堆疊之一側的源極/汲極區之電晶體，其中閘極堆疊位於第一層間介電層中；以及，形成下源極/汲極接觸插塞，所述下源極/汲極接觸插塞電性耦合至源極/汲極區。在第一製程操作中，閘極接觸插塞被形成於閘極堆疊上方並接觸閘極堆疊。在第二製程操作中，上源極/汲極接觸插塞被形成以重疊並接觸下源極/汲極接觸插塞。蝕刻停止層係形成於上源極/汲極接觸插塞和閘極接觸插塞 上方，並接觸上源極/汲極接觸插塞和閘極接觸插塞。
根據本揭露之一些實施例，裝置包括第一層間介電層、於第一層間介電層中的閘極堆疊、於第一層間介電層上方的第二層間介電層、相鄰於閘極堆疊的源極/汲極區域，以及位於源極/汲極區域上方並耦合至源極/汲極區域的下源極/汲極接觸插塞。下源極/汲極接觸插塞穿過第一層間介電層和第二層間介電層。上源極/汲極接觸插塞位於下源極/汲極接觸插塞上方並接觸下源極/汲極接觸插塞。閘極接觸插塞位於閘極堆疊上方並接觸閘極堆疊。上源極/汲極接觸插塞以及閘極接觸插塞係由不同材料所形成。
前述內容概述多個實施例之特徵，以使於本技術領域具有通常知識者可進一步了解本揭露之態樣。本技術領域具通常知識者應可輕易利用本揭露作為基礎，設計或潤飾其他製程及結構，藉以執行此處所描述之實施例的相同的目的及/或達到相同的優點。本技術領域具有通常知識者亦應可了解，上述相等的結構並未脫離本揭露之精神和範圍，且在不脫離本揭露之精神及範圍下，其可經潤飾、取代或替換。

Claims (10)

  1. 一種具有複數個接觸插塞的裝置之製造方法，包含：形成一電晶體，包含：形成一源極/汲極區於一虛擬閘極堆疊的一側；形成一第一層間介電層，其中該第一層間介電層覆蓋該源極/汲極區；以及以一取代閘極堆疊取代該虛擬閘極堆疊，其中該取代閘極堆疊包含一金屬閘極電極；形成一第二層間介電層於該第一層間介電層及該取代閘極堆疊上方；形成一下源極/汲極接觸插塞，其中該下源極/汲極接觸插塞電性耦合至該源極/汲極區，其中該下源極/汲極接觸插塞穿過該第一層間介電層和該第二層間介電層；形成一第三層間介電層於該第二層間介電層上方；形成一閘極接觸插塞於該第二層間介電層和該第三層間介電層中，其中該閘極接觸插塞覆蓋該金屬閘極電極的表面之一第一部分，該金屬閘極電極的表面之一第二部分由該第二層間介電層覆蓋；以及形成一上源極/汲極接觸插塞，其中該上源極/汲極接觸插塞重疊並接觸該下源極/汲極接觸插塞，該上源極/汲極接觸插塞穿過該第三層間介電層，該上源極/汲極接觸插塞的寬度分別大於該下源極/汲極接觸插塞的寬度及該閘極接觸插塞的寬度，且該上源極/汲極接觸插塞和該閘極接觸插塞係由不同材料所形成。
  2. 如申請專利範圍第1項所述之具有複數個接觸插塞的裝置之製造方法，其中該閘極接觸插塞之一深寬比大於該上源極/汲極接觸插塞之一深寬比，且該閘極接觸插塞具有高於該上源極/汲極接觸插塞的一電阻率。
  3. 如申請專利範圍第1項所述之具有複數個接觸插塞的裝置之製造方法，其中該上源極/汲極接觸插塞及該閘極接觸插塞係藉由分開的製程所形成；該閘極接觸插塞之一整體係由沉積一均相材料所形成，該上源極/汲極接觸插塞係藉由沉積一複合結構所形成，且該複合結構包含一下層和位於該下層上方的一上層；該均相材料為金屬氮化物；或該金屬氮化物為氮化鈦。
  4. 如申請專利範圍第1項所述之具有複數個接觸插塞的裝置之製造方法，其中以該取代閘極堆疊取代該虛擬閘極堆疊之操作包含：移除該虛擬閘極堆疊，以形成一溝渠於該第一層間介電層中；形成一閘極間隙壁於該溝渠中；以及形成該取代閘極堆疊於該溝渠中，或其中形成該下源極/汲極接觸插塞的操作包含：蝕刻該第二層間介電層及該第一層間介電層，以形成一源極/汲極接觸開口；形成一接觸間隙壁於該源極/汲極開口中，包含形成一高介電常數間隙壁；以及將一金屬材料填充至該源極/汲極開口中，以形成該下源極/汲極接觸插塞。
  5. 一種具有複數個接觸插塞的裝置之製造方法，包含：形成包含一閘極堆疊及位於該閘極堆疊之一側的一源極/汲極區之一電晶體，其中該閘極堆疊位於一第一層間介電層中；形成一下源極/汲極接觸插塞，其中該下源極/汲極接觸插塞電性耦合至該源極/汲極區；形成一閘極接觸插塞於該閘極堆疊上方，並接觸該閘極堆疊；形成一上源極/汲極接觸插塞，其中該上源極/汲極接觸插塞重疊並接觸該下源極/汲極接觸插塞；以及形成一蝕刻停止層於該上源極/汲極接觸插塞和該閘極接觸插塞上方，其中該蝕刻停止層接觸該上源極/汲極接觸插塞和該閘極接觸插塞。
  6. 如申請專利範圍第5項所述之具有複數個接觸插塞的裝置之製造方法，更包含：於該上源極/汲極接觸插塞和該閘極接觸插塞形成前，沉積一第二層間介電層於該第一層間介電層上方；以及沉積一第三層間介電層於該第二層間介電層上方，其中該下源極/汲極接觸插塞穿過該第一層間介電層和該第二層間介電層，該閘極接觸插塞穿過該第二層間介電層和該第三層間介電層，且該上源極/汲極接觸插塞穿過該第三層間介電層。
  7. 如申請專利範圍第5項所述之具有複數個接觸插塞的裝置之製造方法，其中該閘極接觸插塞之一深寬比大於該上源極/汲極接觸插塞的一深寬比，且該閘極接觸插塞具有高於該上源極/汲極接觸插塞之一電阻率；該閘極接觸插塞之一整體係由一均相材料所形成，該上源極/汲極接觸插塞具有一複合結構，且該複合結構包含一下層和位於該下層上方的一上層；或該均相材料為金屬氮化物。
  8. 如申請專利範圍第5項所述之具有複數個接觸插塞的裝置之製造方法，其中形成該下源極/汲極接觸插塞的操作包含：蝕刻該第一層間介電層，以形成一源極/汲極接觸開口；形成一接觸間隙壁於該源極/汲極接觸開口，包含形成一高介電常數間隙壁；以及以一金屬材料填充該源極/汲極接觸開口。
  9. 一種具有複數個接觸插塞的裝置，包含：一第一層間介電層；一閘極堆疊，位於該第一層間介電層中，其中該閘極堆疊包含一金屬閘極電極；一第二層間介電層，位於該第一層間介電層上方；一源極/汲極區域，相鄰於該閘極堆疊；一下源極/汲極接觸插塞，位於該源極/汲極區域上方並電性耦合至該源極/汲極區域，其中該下源極/汲極接觸插塞穿過該第一層間介電層和該第二層間介電層；一上源極/汲極接觸插塞，位於該下源極/汲極接觸插塞上方並接觸該下源極/汲極接觸插塞；以及一閘極接觸插塞，位於該閘極堆疊上方並接觸該閘極堆疊，其中該閘極接觸插塞覆蓋該金屬閘極電極的表面之一第一部分，該金屬閘極電極的表面之一第二部分由該第二層間介電層覆蓋，該上源極/汲極接觸插塞的寬度分別大於該下源極/汲極接觸插塞的寬度及該閘極接觸插塞的寬度，且該上源極/汲極接觸插塞以及該閘極接觸插塞係由不同材料所形成。
  10. 如申請專利範圍第9項所述之具有複數個接觸插塞的裝置，其中該上源極/汲極接觸插塞以及該閘極接觸插塞具有不同的電阻值，該閘極接觸插塞之一整體係由一均相材料所形成，或該具有複數個接觸插塞的裝置更包含環繞該下源極/汲極接觸插塞之一介電接觸間隙壁。
TW106119513A 2017-04-18 2017-06-12 具有複數個接觸插塞的裝置及其製造方法 TWI623058B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/490,439 2017-04-18
US15/490,439 US10269621B2 (en) 2017-04-18 2017-04-18 Contact plugs and methods forming same

Publications (2)

Publication Number Publication Date
TWI623058B true TWI623058B (zh) 2018-05-01
TW201839906A TW201839906A (zh) 2018-11-01

Family

ID=62951661

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106119513A TWI623058B (zh) 2017-04-18 2017-06-12 具有複數個接觸插塞的裝置及其製造方法

Country Status (5)

Country Link
US (2) US10269621B2 (zh)
KR (1) KR101967541B1 (zh)
CN (2) CN108735656B (zh)
DE (1) DE102017112820B4 (zh)
TW (1) TWI623058B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571188A (zh) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 接触插塞、半导体器件及其制造方法
CN110571189A (zh) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 导电插塞及其形成方法、集成电路
TWI714273B (zh) * 2018-10-24 2020-12-21 美商格芯（美國）集成電路科技有限公司 比例化閘極接觸與源極／汲極蓋
TWI804594B (zh) * 2018-07-16 2023-06-11 台灣積體電路製造股份有限公司 半導體結構及其形成方法

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269636B2 (en) * 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US10312160B2 (en) * 2017-05-26 2019-06-04 International Business Machines Corporation Gate-last semiconductor fabrication with negative-tone resolution enhancement
US10483372B2 (en) 2017-09-29 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Spacer structure with high plasma resistance for semiconductor devices
US10763116B2 (en) * 2017-10-30 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Contact structure
US10529624B2 (en) * 2017-11-21 2020-01-07 International Business Machines Corporation Simple contact over gate on active area
US10943983B2 (en) * 2018-10-29 2021-03-09 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits having protruding interconnect conductors
US10943818B2 (en) 2018-10-31 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US11211243B2 (en) 2018-11-21 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of filling gaps with carbon and nitrogen doped film
KR102491555B1 (ko) 2018-11-30 2023-01-20 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11114336B2 (en) 2018-11-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11158719B2 (en) 2018-11-30 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices and semiconductor devices
US20200181770A1 (en) * 2018-12-05 2020-06-11 Asm Ip Holding B.V. Method of forming a structure including silicon nitride on titanium nitride and structure formed using the method
US11164866B2 (en) 2019-02-20 2021-11-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method for manufacturing the same
WO2020176814A1 (en) * 2019-02-28 2020-09-03 Tokyo Electron Limited Dual silicide wrap-around contacts for semiconductor devices
US10991828B2 (en) 2019-03-20 2021-04-27 Nanya Technology Corporation Semiconductor structure and method of forming the same
US11069784B2 (en) * 2019-05-17 2021-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11239114B2 (en) * 2019-09-16 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with reduced contact resistance and methods of forming the same
US11532561B2 (en) * 2019-09-30 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Different via configurations for different via interface requirements
US10964792B1 (en) * 2019-11-22 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Dual metal capped via contact structures for semiconductor devices
US11276571B2 (en) 2019-12-26 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method of breaking through etch stop layer
TWI762112B (zh) * 2019-12-26 2022-04-21 台灣積體電路製造股份有限公司 半導體裝置的形成方法
CN113497186A (zh) 2020-04-01 2021-10-12 联华电子股份有限公司 并联的电容结构及其制作方法
CN113140565A (zh) 2020-04-28 2021-07-20 台湾积体电路制造股份有限公司 半导体器件和制造方法
US11410930B2 (en) * 2020-04-28 2022-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
DE102020130401A1 (de) 2020-05-28 2021-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dipolig-gefertigtes high-k-gate-dielektrikum und verfahren zu dessen bildung desselben
US11784052B2 (en) * 2020-05-28 2023-10-10 Taiwan Semiconductor Manufacturing Co., Ltd. Dipole-engineered high-k gate dielectric and method forming same
US11710657B2 (en) * 2020-09-29 2023-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Middle-of-line interconnect structure having air gap and method of fabrication thereof
US11837603B2 (en) * 2021-01-22 2023-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Extended side contacts for transistors and methods forming same
US11855153B2 (en) * 2021-03-10 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US12107007B2 (en) * 2021-05-05 2024-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Recessed contacts at line end and methods forming same
US20230155001A1 (en) * 2021-11-12 2023-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dual Damascene Structure in Forming Source/Drain Contacts

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140199837A1 (en) * 2013-01-14 2014-07-17 United Microelectronics Corp. Method of forming semiconductor structure having contact plug

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004172179A (ja) * 2002-11-18 2004-06-17 Fujitsu Ltd 半導体装置及びその製造方法
JP4501965B2 (ja) * 2006-10-16 2010-07-14 ソニー株式会社 半導体装置の製造方法
US7964491B2 (en) * 2008-01-21 2011-06-21 Hynix Semiconductor Inc. Method of forming metal wiring of nonvolatile memory device
US7754559B2 (en) * 2008-03-19 2010-07-13 Tower Semiconductor Ltd. Method for fabricating capacitor structures using the first contact metal
CN102576727B (zh) * 2010-06-23 2016-01-27 康奈尔大学 门控iii-v半导体结构和方法
US8420469B2 (en) 2010-07-12 2013-04-16 International Business Machines Corporation Schottky FET fabricated with gate last process
US8765600B2 (en) 2010-10-28 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure for reducing gate resistance and method of making the same
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US8569129B2 (en) 2011-05-31 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics
US8685850B2 (en) * 2011-06-13 2014-04-01 Stmicroelectronics, Inc. System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US8624324B1 (en) 2012-08-10 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Connecting through vias to devices
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9396950B2 (en) * 2013-03-15 2016-07-19 Globalfoundries Inc. Low thermal budget schemes in semiconductor device fabrication
US9076823B2 (en) * 2013-09-11 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bi-layer metal deposition in silicide formation
US9209252B2 (en) * 2013-12-18 2015-12-08 Taiwan Semiconductor Manufacturing Company Limited Formation of nickel silicon and nickel germanium structure at staggered times
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9356104B2 (en) * 2014-08-13 2016-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with gate stack
US9449970B2 (en) * 2014-08-22 2016-09-20 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
US9461145B2 (en) * 2014-10-01 2016-10-04 Globalfoundries Inc. OPC enlarged dummy electrode to eliminate ski slope at eSiGe
KR102235578B1 (ko) 2014-11-19 2021-04-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN105762108B (zh) * 2014-12-19 2019-03-29 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10090360B2 (en) * 2015-02-13 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor structure including a plurality of trenches
US9484431B1 (en) 2015-07-29 2016-11-01 International Business Machines Corporation Pure boron for silicide contact
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US20170162444A1 (en) * 2015-12-02 2017-06-08 International Business Machines Corporation Contact resistance reduction for advanced technology nodes
US10916542B2 (en) * 2015-12-30 2021-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed STI as the gate dielectric of HV device
US9711607B1 (en) * 2016-04-15 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. One-dimensional nanostructure growth on graphene and devices thereof
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
US10516030B2 (en) * 2017-01-09 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs and methods forming same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140199837A1 (en) * 2013-01-14 2014-07-17 United Microelectronics Corp. Method of forming semiconductor structure having contact plug

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110571188A (zh) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 接触插塞、半导体器件及其制造方法
CN110571189A (zh) * 2018-06-05 2019-12-13 中芯国际集成电路制造(上海)有限公司 导电插塞及其形成方法、集成电路
CN110571189B (zh) * 2018-06-05 2022-04-29 中芯国际集成电路制造(上海)有限公司 导电插塞及其形成方法、集成电路
TWI804594B (zh) * 2018-07-16 2023-06-11 台灣積體電路製造股份有限公司 半導體結構及其形成方法
TWI714273B (zh) * 2018-10-24 2020-12-21 美商格芯（美國）集成電路科技有限公司 比例化閘極接觸與源極／汲極蓋
US10892338B2 (en) 2018-10-24 2021-01-12 Globalfoundries Inc. Scaled gate contact and source/drain cap
US11569356B2 (en) 2018-10-24 2023-01-31 Globalfoundries U.S. Inc. Scaled gate contact and source/drain cap

Also Published As

Publication number Publication date
DE102017112820B4 (de) 2024-07-18
KR20180117018A (ko) 2018-10-26
DE102017112820A1 (de) 2018-10-18
US10535555B2 (en) 2020-01-14
CN112289741A (zh) 2021-01-29
CN108735656A (zh) 2018-11-02
KR101967541B1 (ko) 2019-04-09
US20190109041A1 (en) 2019-04-11
TW201839906A (zh) 2018-11-01
US10269621B2 (en) 2019-04-23
US20180301371A1 (en) 2018-10-18
CN108735656B (zh) 2020-12-08

Similar Documents

Publication Publication Date Title
TWI623058B (zh) 具有複數個接觸插塞的裝置及其製造方法
US11862708B2 (en) Contact plugs and methods forming same
TWI677924B (zh) 半導體裝置及其製造方法
US20240371868A1 (en) Buried metal track and methods forming same
CN108695240B (zh) 低阻抗接触窗插塞的形成方法
TWI668744B (zh) 半導體裝置及其形成方法
TWI651761B (zh) 半導體裝置及其製造方法
TWI808130B (zh) 半導體裝置及其製造方法
TW202002280A (zh) 半導體裝置及其形成方法
TWI662652B (zh) 形成積體電路的方法
TWI767293B (zh) 半導體元件及其形成方法
US20230378182A1 (en) Extended Side Contacts for Transistors and Methods Forming Same
US20240072155A1 (en) Contact plugs and methods forming same
US20230114191A1 (en) Forming Seams with Desirable Dimensions in Isolation Regions
TWI813252B (zh) 半導體結構及其製造方法
US20230163194A1 (en) Dummy Hybrid Film for Self-Alignment Contact Formation
US20240379815A1 (en) Dummy hybrid film for self alignment contact formation