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TWI695384B - Memory device and error detection method thereof - Google Patents

Memory device and error detection method thereof Download PDF

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TWI695384B
TWI695384B TW108110905A TW108110905A TWI695384B TW I695384 B TWI695384 B TW I695384B TW 108110905 A TW108110905 A TW 108110905A TW 108110905 A TW108110905 A TW 108110905A TW I695384 B TWI695384 B TW I695384B
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memory
data
clone
target
memory array
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TW108110905A
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TW202036578A (en
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朴山河
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華邦電子股份有限公司
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Abstract

A memory device includes a memory array having at least one memory bank, where the at least one memory bank includes a target memory array and a clone memory array. The clone memory array corresponds to the target memory array and is configured to store the same data as in the target memory array. When a command that is applied to the target memory array to perform an operation, the command is also applied to the clone memory array. An error detection method adapted to a memory device having at least one memory bank that comprises a target memory array and a clone memory array is also introduced.

Description

記憶體裝置及其錯誤檢測方法Memory device and its error detection method

本發明是有關於一種記憶體裝置及用於檢測記憶體裝置上的錯誤或故障的錯誤檢測方法。 The invention relates to a memory device and an error detection method for detecting errors or malfunctions on the memory device.

記憶體裝置,尤其是隨機存取記憶體(Random Access Memory,RAM)及動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)的裝置應用於廣泛的用途,例如:機動車輛、電腦、數位相機、智慧型手機等。對於高可靠性系統,它需要高度可靠的記憶體裝置,高度可靠的記憶體裝置可以檢測記憶體裝置可能發生的錯誤或故障。一般而言,錯誤更正碼(Error Correction Code,ECC)用於檢測錯誤位元並糾正檢測到的錯誤位元。然而,ECC不能妥善地處理可能由多個故障引起的多錯誤位元,例如:字元線故障(Word Line Failure)、單元到單元故障(Cell-to-cell Failure)、集總顆粒故障(Lumped Particle Failure)、字位線到字位線短路(Bitline-to-bitline Short)等。在這種情況下,ECC無法更正錯誤或故障,且系統無法識別故障的存在。結果,降低了記 憶體裝置的可靠性。 Memory devices, especially random access memory (Random Access Memory, RAM) and dynamic random access memory (Dynamic Random Access Memory, DRAM) devices are used in a wide range of applications, such as: motor vehicles, computers, digital cameras , Smart phones, etc. For a high-reliability system, it requires a highly reliable memory device. The highly reliable memory device can detect errors or failures that may occur in the memory device. Generally speaking, Error Correction Code (ECC) is used to detect erroneous bits and correct the detected erroneous bits. However, ECC cannot properly handle multiple erroneous bits that may be caused by multiple failures, such as: Word Line Failure, Cell-to-cell Failure, Lumped Particle Failure Particle Failure), word bit line to word bit line short (Bitline-to-bitline Short), etc. In this case, ECC cannot correct the error or failure, and the system cannot recognize the existence of the failure. As a result, the Reliability of memory device.

隨著記憶體裝置的普及,取得一種具有可靠性的錯誤檢測方案從而提高記憶體裝置的性能及可靠性有其必要性。 With the popularity of memory devices, it is necessary to obtain a reliable error detection scheme to improve the performance and reliability of memory devices.

本發明介紹了一種記憶體裝置及用於檢測記憶體裝置上的錯誤或故障的錯誤檢測方法。 The invention introduces a memory device and an error detection method for detecting errors or malfunctions on the memory device.

本發明提供一種記憶體裝置包括具有至少一記憶體組的記憶體陣列,其中至少一記憶體組包括目標記憶體陣列及對應於目標記憶體陣列的克隆記憶體陣列。目標記憶體陣列用以儲存資料,且克隆記憶體陣列被用以儲存與目標記憶體陣列的資料相同的資料。應用於目標記憶體陣列以執行操作的命令應用於克隆記憶體陣列。 The present invention provides a memory device including a memory array having at least one memory group, wherein the at least one memory group includes a target memory array and a clone memory array corresponding to the target memory array. The target memory array is used to store data, and the clone memory array is used to store the same data as the target memory array. Commands applied to the target memory array to perform operations are applied to the clone memory array.

本發明提供一種錯誤檢測方法適用於具有至少一記憶體組的記憶體裝置,其中記憶體組包括目標記憶體陣列和克隆記憶體陣列。讀取錯誤檢測包括讀取目標記憶體陣列的目標記憶體單元以獲得目標記憶體資料的步驟:讀取克隆記憶體陣列的克隆記憶體單元以獲得克隆記憶體資料,其中克隆記憶體陣列的克隆記憶體單元對應於目標記憶體陣列的目標記憶體單元;將目標記憶體資料與克隆記憶體資料進行比較以輸出比較訊號;以及依據比較訊號判斷目標記憶體資料是否包括錯誤。 The invention provides an error detection method suitable for a memory device having at least one memory group, wherein the memory group includes a target memory array and a clone memory array. The read error detection includes the steps of reading the target memory unit of the target memory array to obtain target memory data: reading the clone memory unit of the clone memory array to obtain clone memory data, wherein the clone of the clone memory array The memory unit corresponds to the target memory unit of the target memory array; compares the target memory data with the cloned memory data to output a comparison signal; and judges whether the target memory data includes errors according to the comparison signal.

基於上述,克隆記憶體陣列用以儲存與目標記憶體陣列 中的資料相同的資料,故錯誤檢測方法可以比較儲存於目標記憶體陣列中的資料與儲存於克隆記憶體陣列中的資料,以檢測記憶體裝置中的錯誤。藉由這種方式,改善了儲存於記憶體裝置中的資料的可靠性。 Based on the above, the clone memory array is used to store and target the memory array The data in the data is the same, so the error detection method can compare the data stored in the target memory array with the data stored in the clone memory array to detect errors in the memory device. In this way, the reliability of the data stored in the memory device is improved.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100:記憶體裝置 100: memory device

112:記憶體組i 112: Memory group i

1121:克隆記憶體陣列 1121: Clone memory array

114:記憶體組j 114: Memory Group j

116:記憶體組k 116: Memory group k

118:記憶體組l 118: Memory group l

120:比較器 120: Comparator

130:周邊記憶體電路 130: peripheral memory circuit

140:記憶體控制器 140: memory controller

150:模組暫存器 150: module register

C、C1~C4:克隆記憶體陣列 C, C1~C4: clone memory array

D1:目標記憶體資料 D1: target memory data

D2:克隆記憶體資料 D2: Clone memory data

DQ、DQ1:資料輸出訊號 DQ, DQ1: data output signal

DM、DM1:資料遮罩訊號 DM, DM1: data mask signal

210a、210b、210c、310a、310b、310c、310d:記憶體陣列 210a, 210b, 210c, 310a, 310b, 310c, 310d: memory array

212a~218a、212b~218b、212c~218c、312a~318a、312b~318b、312c~318c、312d~318d、412a、414a、412b:記憶體組 212a~218a, 212b~218b, 212c~218c, 312a~318a, 312b~318b, 312c~318c, 312d~318d, 412a, 414a, 412b: memory group

420a、420b:比較器 420a, 420b: comparator

430a、430b:周邊記憶體電路 430a, 430b: peripheral memory circuit

CLK:時脈訊號 CLK: clock signal

DQS:資料選通訊號 DQS: data selection communication number

GND:接地電壓 GND: ground voltage

P51、P52、P60、P61、P62:脈衝訊號 P51, P52, P60, P61, P62: pulse signal

S710~S740:錯誤檢測方法的流程 S710~S740: Flow of error detection method

T、T1~T4:目標記憶體陣列 T, T1~T4: target memory array

本發明包括圖式以提供對本發明的進一步理解,且圖式被併入本說明書中並構成本說明書的一部分。圖式繪示了本發明的實施例,並與本說明書的揭示內容一起用以解釋本發明的原理。 The invention includes drawings to provide a further understanding of the invention, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate the embodiments of the present invention, and are used to explain the principles of the present invention together with the disclosure of this specification.

圖1是繪示根據本發明實施例的記憶體裝置的示意圖。 FIG. 1 is a schematic diagram illustrating a memory device according to an embodiment of the invention.

圖2A至圖3D是繪示根據本發明實施例的具有目標記憶體陣列及克隆記憶體陣列的記憶體裝置的示意圖。 2A to 3D are schematic diagrams illustrating a memory device having a target memory array and a clone memory array according to an embodiment of the invention.

圖4A是繪示根據本發明實施例的具有目標記憶體陣列及位於不同記憶體組中的克隆記憶體陣列的記憶體裝置的示意圖。 4A is a schematic diagram illustrating a memory device having a target memory array and clone memory arrays in different memory groups according to an embodiment of the present invention.

圖4B是繪示根據本發明實施例的具有位於同一記憶體組中的目標記憶體陣列及克隆記憶體陣列的記憶體裝置的示意圖。 4B is a schematic diagram illustrating a memory device having a target memory array and a clone memory array in the same memory group according to an embodiment of the present invention.

圖5A至圖5B是繪示根據本發明實施例的當禁用資料匯流排反轉演算法時記憶體裝置中的訊號的波形圖。 5A-5B are waveform diagrams illustrating signals in the memory device when the data bus inversion algorithm is disabled according to an embodiment of the present invention.

圖6A至圖6B是繪示根據本發明實施例的當啟用資料匯流排反轉演算法時記憶體裝置中的訊號的波形圖。 6A-6B are waveform diagrams illustrating signals in the memory device when the data bus inversion algorithm is enabled according to an embodiment of the present invention.

圖7是繪示根據本發明實施例的錯誤檢測方法的流程圖。 7 is a flowchart illustrating an error detection method according to an embodiment of the invention.

應當理解,在不脫離本發明的範圍的情況下,可以利用其他實施例,並且可以進行結構改變。還有,應該理解,這裡使用的措辭及術語是以描述為目的,不應該被認為是限制性的。本文中“包括”、“包含”或“具有”以及其變化的使用旨在涵蓋其後列出的項目、其等同物以及其附加項目。除非另有限制,否則本文中術語“連接”、“耦接”、“配置”以及其變化被廣泛使用,並且包括直接及間接連接、耦接以及配置。 It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it should be understood that the wording and terminology used herein are for the purpose of description and should not be considered limiting. The use of "including", "comprising" or "having" and variations thereof herein is intended to cover the items listed thereafter, equivalents thereof and additional items thereof. Unless otherwise limited, the terms "connected", "coupled", "configuration" and variations thereof are widely used herein and include direct and indirect connections, couplings and configurations.

請參考圖1,記憶體裝置100包括記憶體陣列110、比較器120、周邊記憶體電路130、記憶體控制器140以及模組暫存器150。記憶體陣列110包括記憶體組112、114、116以及118(也分別稱為記憶體組i、記憶體組j、記憶體組k以及記憶體組l)。記憶體組112、114、116以及118中的至少一個包括克隆記憶體陣列1121,其對應於位於記憶體陣列110中的目標記憶體陣列(未繪示)。克隆記憶體陣列1121儲存與儲存在目標記憶體陣列中的資料相同的資料。如圖1所示,克隆記憶體陣列1121位於記憶體陣列110的記憶體組112(記憶體組i)中,但本發明並不限於此。克隆記憶體陣列1121可以位於記憶體陣列110的任何記憶體組112、114、116以及118中。 Please refer to FIG. 1. The memory device 100 includes a memory array 110, a comparator 120, a peripheral memory circuit 130, a memory controller 140 and a module register 150. The memory array 110 includes memory groups 112, 114, 116, and 118 (also referred to as memory group i, memory group j, memory group k, and memory group 1, respectively). At least one of the memory groups 112, 114, 116, and 118 includes a clone memory array 1121, which corresponds to a target memory array (not shown) located in the memory array 110. The clone memory array 1121 stores the same data as the data stored in the target memory array. As shown in FIG. 1, the clone memory array 1121 is located in the memory group 112 (memory group i) of the memory array 110, but the present invention is not limited thereto. The clone memory array 1121 may be located in any memory group 112, 114, 116, and 118 of the memory array 110.

在本發明的實施例中,記憶體裝置100是動態隨機存取 記憶體(DRAM)裝置,且記憶體裝置100與聯合電子裝置工程委員會(Joint Electron Device Engineering Council,JEDEC)標準兼容。 In the embodiment of the present invention, the memory device 100 is dynamic random access A memory (DRAM) device, and the memory device 100 is compatible with the Joint Electron Device Engineering Council (JEDEC) standard.

比較器120耦接於記憶體陣列110,並且用以比較從記憶體陣列110讀取的資料。舉例而言,比較器120可比較目標記憶體資料D1及克隆記憶體資料D2,其中比較器120從目標記憶體陣列讀取目標記憶體資料D1,並且比較器120從克隆記憶體陣列讀取克隆記憶體資料D2。如圖1所示,比較器120是分離電路,但比較器120也可以結合到記憶體裝置110的其他電路中。比較器120將資料遮罩訊號DM1及資料輸出訊號DQ1輸出到周邊記憶體電路130。 The comparator 120 is coupled to the memory array 110 and used to compare the data read from the memory array 110. For example, the comparator 120 may compare the target memory data D1 and the clone memory data D2, where the comparator 120 reads the target memory data D1 from the target memory array, and the comparator 120 reads the clone from the clone memory array Memory data D2. As shown in FIG. 1, the comparator 120 is a separate circuit, but the comparator 120 can also be incorporated into other circuits of the memory device 110. The comparator 120 outputs the data mask signal DM1 and the data output signal DQ1 to the peripheral memory circuit 130.

資料遮罩訊號DM1可指示目標記憶體資料D1是否與克隆記憶體資料D2相同,且資料輸出訊號DQ1可以是目標記憶體資料D1,或者可以與目標記憶體資料D1相關。目標記憶體資料D1及克隆記憶體資料D2是N位元的資料,其中N例如是8、16、32、64的整數。資料D1及D2可以是利用錯誤更正碼(ECC)操作執行的資料,或者是直接從記憶體陣列110讀取的資料。 The data mask signal DM1 may indicate whether the target memory data D1 is the same as the clone memory data D2, and the data output signal DQ1 may be the target memory data D1, or may be related to the target memory data D1. The target memory data D1 and the clone memory data D2 are N-bit data, where N is an integer of 8, 16, 32, 64, for example. The data D1 and D2 may be data executed using an error correction code (ECC) operation, or data directly read from the memory array 110.

周邊記憶體電路130耦接於比較器120,以從比較器120接收資料遮罩訊號DM1及資料輸出訊號DQ1。周邊記憶體電路130可將資料遮罩訊號DM及資料輸出訊號DQ輸出到記憶體控制器140。資料遮罩訊號DM及資料輸出訊號DQ分別與資料遮罩訊號DM1及資料輸出訊號DQ1相同或相關。 The peripheral memory circuit 130 is coupled to the comparator 120 to receive the data mask signal DM1 and the data output signal DQ1 from the comparator 120. The peripheral memory circuit 130 can output the data mask signal DM and the data output signal DQ to the memory controller 140. The data mask signal DM and the data output signal DQ are the same as or related to the data mask signal DM1 and the data output signal DQ1, respectively.

對於記憶體裝置100,周邊記憶體電路130包括其他協同操作所需要的電路。例如:周邊記憶體電路130可以包括記憶體裝置100的列與行解碼器(Row and Column Decoders)(未繪示)、位元線預充電電路(Bit-line Pre-charge Circuits)(未繪示)、感測放大器(Sense Amplifiers)(未繪示)、時序控制器(timing controller)(未繪示)以及讀寫電路(Read-write Circuit)(未繪示)。這些電路對於在記憶體裝置100上執行操作是其必要性,且本領域技術人員可清楚地理解這些電路的功能,故在下文中省略關於這些電路的詳細描述。 For the memory device 100, the peripheral memory circuit 130 includes other circuits required for cooperative operation. For example, the peripheral memory circuit 130 may include Row and Column Decoders (not shown) and Bit-line Pre-charge Circuits (not shown) of the memory device 100 (not shown) ), sense amplifiers (Sense Amplifiers) (not shown), timing controllers (not shown) and read-write circuits (not shown). These circuits are necessary for performing operations on the memory device 100, and those skilled in the art can clearly understand the functions of these circuits, so detailed descriptions of these circuits are omitted below.

在本發明的實施例中,資料遮罩訊號DM被發送到記憶體裝置100的資料遮罩腳位(未繪示),並且資料輸出訊號DQ被輸出到記憶體裝置100的資料輸出腳位(未繪示)。在另一實施例中,資料遮罩訊號DM及資料輸出訊號DQ被傳輸到附加腳位,而不是被傳輸到記憶體裝置100的資料遮罩腳位及資料輸出腳位。 In the embodiment of the present invention, the data mask signal DM is sent to the data mask pin (not shown) of the memory device 100, and the data output signal DQ is output to the data output pin of the memory device 100 ( Not shown). In another embodiment, the data mask signal DM and the data output signal DQ are transmitted to the additional pins instead of the data mask pins and the data output pins transmitted to the memory device 100.

記憶體控制器140耦接於周邊記憶體電路130,以從周邊記憶體電路130接收資料遮罩訊號DM及資料輸出訊號DQ。基於接收的資料遮罩訊號DM及資料輸出訊號DQ,控制器140可以判斷儲存於記憶體陣列110中的目標記憶體資料D1是否包含錯誤。記憶體控制器140還用以通過命令控制記憶體裝置100的操作。 The memory controller 140 is coupled to the peripheral memory circuit 130 to receive the data mask signal DM and the data output signal DQ from the peripheral memory circuit 130. Based on the received data mask signal DM and data output signal DQ, the controller 140 can determine whether the target memory data D1 stored in the memory array 110 contains an error. The memory controller 140 is also used to control the operation of the memory device 100 through commands.

模組暫存器150用以設置記憶體裝置100中的目標記憶體陣列及克隆記憶體陣列的位置和大小。目標記憶體陣列及克隆記憶體陣列位於記憶體裝置100的同一記憶體組或不同記憶體組 中。此外,目標記憶體陣列及克隆記憶體陣列的大小是依據設計需要修改的。模組暫存器150也可選擇記憶體組地址及列地址,以存取目標記憶體陣列及克隆記憶體陣列中的單元。模組暫存器150也可以禁用(disable)克隆記憶體陣列的功能,或者禁用克隆記憶體陣列及目標記憶體陣列的功能。藉由這種方式,記憶體陣列110可以用作傳統的記憶體陣列。除了模組暫存器150之外,例如選項熔絲(Option Fuse)或內部佈線(Internal Wiring)的選擇性電路可以用以選擇目標記憶體陣列及克隆記憶體陣列。 The module register 150 is used to set the location and size of the target memory array and the clone memory array in the memory device 100. The target memory array and the clone memory array are located in the same memory group or different memory groups of the memory device 100 in. In addition, the size of the target memory array and the clone memory array are modified according to design requirements. The module register 150 can also select a memory group address and a row address to access the cells in the target memory array and the clone memory array. The module register 150 may also disable the function of cloning the memory array, or disable the function of cloning the memory array and the target memory array. In this way, the memory array 110 can be used as a conventional memory array. In addition to the module register 150, a selective circuit such as Option Fuse or Internal Wiring can be used to select the target memory array and the clone memory array.

請參考圖2A至2C,其繪示了關於包括目標記憶體陣列及位於不同記憶體組中的克隆記憶體陣列的記憶體陣列的示範性實施例。請參考圖2A,記憶體陣列210a包括目標記憶體陣列T1、T2及克隆記憶體陣列C1、C2,其中目標記憶體陣列T1、T2及克隆記憶體陣列位於不同的記憶體組中。 Please refer to FIGS. 2A to 2C, which illustrate exemplary embodiments of a memory array including a target memory array and clone memory arrays located in different memory groups. Referring to FIG. 2A, the memory array 210a includes target memory arrays T1, T2 and clone memory arrays C1, C2, wherein the target memory arrays T1, T2 and clone memory arrays are located in different memory groups.

具體而言,記憶體陣列210a包括位於記憶體組212a中的第一目標記憶體陣列T1、位於記憶體組214a中的第一克隆記憶體陣列C1、位於記憶體組216a中的第二目標記憶體陣列T2、以及位於記憶體組218a中的第二克隆記憶體陣列C2。第一克隆記憶體陣列C1具有與第一目標記憶體陣列T1相同的大小,並且儲存與第一目標記憶體陣列T1相同的資料。第二克隆記憶體陣列C2具有與第二目標記憶體陣列T2相同的大小,並且儲存與第二目標記憶體陣列T2相同的資料。圖1中所示的模組暫存器150控制克隆記憶體陣列C1、C2及目標記憶體陣列T1、T2的位置、大 小及存取地址。在圖2A中,克隆記憶體陣列C1及C2佔有50%的記憶體組212a至218a。 Specifically, the memory array 210a includes a first target memory array T1 in the memory group 212a, a first clone memory array C1 in the memory group 214a, and a second target memory in the memory group 216a Volume array T2, and a second clone memory array C2 located in the memory group 218a. The first clone memory array C1 has the same size as the first target memory array T1 and stores the same data as the first target memory array T1. The second clone memory array C2 has the same size as the second target memory array T2 and stores the same data as the second target memory array T2. The module register 150 shown in FIG. 1 controls the position and size of the clone memory arrays C1 and C2 and the target memory arrays T1 and T2. Small and access address. In FIG. 2A, the clone memory arrays C1 and C2 occupy 50% of the memory groups 212a to 218a.

請參考圖2B,記憶體陣列210b包括位於記憶體組212b中的目標記憶體陣列T1及位於記憶體組214b中的克隆記憶體陣列C1。克隆記憶體陣列C1具有與目標記憶體陣列T1相同的大小,並且儲存與目標記憶體陣列T1相同的資料。圖2A中所示的記憶體陣列210a與圖2B中所示的記憶體陣列210b之間的區別在於記憶體陣列210b包括記憶體組216b及218b,其中記憶體組216b及218b為一般記憶體組。換言之,一般記憶體組216b及218b不包括任何目標記憶體陣列或克隆記憶體陣列。在圖2B中,克隆記憶體陣列C1佔有25%的記憶體組212b至218b。 2B, the memory array 210b includes a target memory array T1 in the memory group 212b and a clone memory array C1 in the memory group 214b. The clone memory array C1 has the same size as the target memory array T1 and stores the same data as the target memory array T1. The difference between the memory array 210a shown in FIG. 2A and the memory array 210b shown in FIG. 2B is that the memory array 210b includes memory groups 216b and 218b, wherein the memory groups 216b and 218b are general memory groups. . In other words, the general memory groups 216b and 218b do not include any target memory array or clone memory array. In FIG. 2B, the clone memory array C1 occupies 25% of the memory groups 212b to 218b.

請參考圖2C,記憶體陣列210c包括記憶體組212c、214c、216c、218c、位於記憶體組212c中的目標記憶體陣列T1及位於記憶體組214c中的克隆記憶體陣列C1。圖2C中所示的記憶體陣列210c與圖2B中的記憶體陣列210b之間的區別在於,圖2B中的克隆記憶體陣列及目標記憶體陣列的大小與記憶體組的大小相同,而圖2C中的克隆記憶體陣列及目標記憶體陣列的大小小於記憶體組的大小。記憶體組212c包括目標記憶體陣列T1及一般記憶體陣列,記憶體組214c包括克隆記憶體陣列C1及一般記憶體陣列。克隆記憶體陣列C1佔有12.55%的記憶體組212c至218c。 2C, the memory array 210c includes memory groups 212c, 214c, 216c, 218c, a target memory array T1 in the memory group 212c, and a clone memory array C1 in the memory group 214c. The difference between the memory array 210c shown in FIG. 2C and the memory array 210b in FIG. 2B is that the size of the clone memory array and the target memory array in FIG. 2B is the same as the size of the memory group. The size of the clone memory array and the target memory array in 2C is smaller than the size of the memory group. The memory group 212c includes a target memory array T1 and a general memory array, and the memory group 214c includes a clone memory array C1 and a general memory array. The clone memory array C1 occupies 12.5% of the memory groups 212c to 218c.

圖2A至圖2C繪示了克隆記憶體陣列具有50%、25%及 12.5%的實施例。然而,本發明不限於此,並且可以根據設計需要調整克隆記憶體陣列與總記憶體陣列的比率。 2A to 2C show the clone memory array has 50%, 25% and 12.5% of the examples. However, the present invention is not limited to this, and the ratio of the clone memory array to the total memory array can be adjusted according to design needs.

請參考圖3A至3D,其繪示了關於包括目標記憶體陣列及位於同一記憶體組中的克隆記憶體陣列的記憶體陣列的示範性實施例。請參考圖3A,記憶體陣列310a包括記憶體組312a、314a、316a以及318a,其中記憶體組312a、314a、316a以及318a中的每一個包括目標記憶體陣列及對應於目標記憶體陣列的克隆記憶體陣列。具體而言,記憶體組312a包括目標記憶體陣列T1及與目標記憶體陣列T1對應的克隆記憶體陣列C1。記憶體組314a包括目標記憶體陣列T2及對應於目標記憶體陣列T2的克隆記憶體陣列C2。記憶體組316a包括目標記憶體陣列T3及對應於目標記憶體陣列T3的克隆記憶體陣列C3,以及記憶體組318a包括目標記憶體陣列T4及對應於目標記憶體陣列T4的克隆記憶體陣列C4。在圖3A所示的實施例中,克隆記憶體陣列C1~C4佔有50%的記憶體組312a至318a。 Please refer to FIGS. 3A to 3D, which illustrate exemplary embodiments of a memory array including a target memory array and a clone memory array located in the same memory group. Referring to FIG. 3A, the memory array 310a includes memory groups 312a, 314a, 316a, and 318a, wherein each of the memory groups 312a, 314a, 316a, and 318a includes a target memory array and a clone corresponding to the target memory array Memory array. Specifically, the memory group 312a includes the target memory array T1 and the clone memory array C1 corresponding to the target memory array T1. The memory group 314a includes a target memory array T2 and a clone memory array C2 corresponding to the target memory array T2. The memory group 316a includes the target memory array T3 and the clone memory array C3 corresponding to the target memory array T3, and the memory group 318a includes the target memory array T4 and the clone memory array C4 corresponding to the target memory array T4 . In the embodiment shown in FIG. 3A, the clone memory arrays C1 to C4 occupy 50% of the memory groups 312a to 318a.

請參考圖3B,記憶體陣列310b包括記憶體組312b、314b、316b以及318b,其中記憶體組312b及316b中的每一個包括目標記憶體陣列及對應於目標記憶體陣列的克隆記憶體陣列。記憶體組314b及318b僅包括一般記憶體陣列。記憶體組312b包括目標記憶體陣列T1及與目標記憶體陣列T1對應的克隆記憶體陣列C1。記憶體組316a包括目標記憶體陣列T3及與目標記憶體陣列T3相對應的克隆記憶體陣列C3。在圖3B所示的實施例中, 克隆記憶體陣列C1及C3佔有25%的記憶體組312b至318b。 Referring to FIG. 3B, the memory array 310b includes memory groups 312b, 314b, 316b, and 318b, wherein each of the memory groups 312b and 316b includes a target memory array and a clone memory array corresponding to the target memory array. The memory groups 314b and 318b include only general memory arrays. The memory group 312b includes a target memory array T1 and a clone memory array C1 corresponding to the target memory array T1. The memory group 316a includes a target memory array T3 and a clone memory array C3 corresponding to the target memory array T3. In the embodiment shown in FIG. 3B, The clone memory arrays C1 and C3 occupy 25% of the memory groups 312b to 318b.

請參考圖3C,記憶體陣列310c包括記憶體組312c、314c、316c以及318c,其中記憶體組312c包括目標記憶體陣列T1及對應於目標記憶體陣列T1的克隆記憶體陣列C1。記憶體組314c、316c以及318c僅包括一般記憶體陣列。在圖3C所示的實施例中,克隆記憶體陣列C1佔有12.5%的記憶體組312c至318c。 Referring to FIG. 3C, the memory array 310c includes memory groups 312c, 314c, 316c, and 318c, where the memory group 312c includes a target memory array T1 and a clone memory array C1 corresponding to the target memory array T1. The memory groups 314c, 316c, and 318c include only general memory arrays. In the embodiment shown in FIG. 3C, the clone memory array C1 occupies 12.5% of the memory groups 312c to 318c.

請參考圖3D,記憶體陣列310d包括記憶體組312d、314d、316d以及318d,其中記憶體組312d包括目標記憶體陣列T1、克隆記憶體陣列C1以及一般記憶體陣列。記憶體組314d、316d以及318d僅包括一般記憶體陣列。在圖3D所示的實施例中,克隆記憶體陣列C1佔有8.33%的記憶體組312d至318d。 Referring to FIG. 3D, the memory array 310d includes memory groups 312d, 314d, 316d, and 318d, wherein the memory group 312d includes a target memory array T1, a clone memory array C1, and a general memory array. The memory groups 314d, 316d, and 318d include only general memory arrays. In the embodiment shown in FIG. 3D, the clone memory array C1 occupies 8.33% of the memory groups 312d to 318d.

請參考圖4A,記憶體裝置400a包括記憶體組412a及記憶體組414a,其中記憶體組412a包括目標記憶體陣列T,記憶體組414a包括克隆記憶體陣列C。克隆記憶體陣列C具有與目標記憶體T相同的大小,並且儲存與目標記憶體T相同的資料。 4A, the memory device 400a includes a memory group 412a and a memory group 414a, wherein the memory group 412a includes a target memory array T, and the memory group 414a includes a clone memory array C. The clone memory array C has the same size as the target memory T, and stores the same data as the target memory T.

記憶體裝置400a還包括比較器420a及周邊記憶體電路430a。比較器420a用以比較資料D1及D2以輸出資料遮罩訊號DM1及資料輸出訊號DQ1。資料D1及D2可以是利用EEC操作執行的資料,或者是直接從目標記憶體陣列T及克隆記憶體陣列C讀取的資料。周邊記憶體電路430a耦接於比較器420,並用以依據接收的資料遮罩訊號DM1及資料輸出訊號DQ1輸出資料遮罩訊號DM及資料輸出訊號DQ。 The memory device 400a further includes a comparator 420a and a peripheral memory circuit 430a. The comparator 420a is used to compare the data D1 and D2 to output the data mask signal DM1 and the data output signal DQ1. The data D1 and D2 may be data executed by the EEC operation, or data directly read from the target memory array T and the clone memory array C. The peripheral memory circuit 430a is coupled to the comparator 420 and used to output the data mask signal DM and the data output signal DQ according to the received data mask signal DM1 and the data output signal DQ1.

在記憶體裝置400a的操作中,如果命令被施加在記憶體組412a中的目標記憶體陣列T上,則相同的命令也被應用於記憶體組414a的克隆記憶體陣列。 In the operation of the memory device 400a, if a command is applied to the target memory array T in the memory group 412a, the same command is also applied to the clone memory array of the memory group 414a.

例如,當記憶體裝置400a接收到用於將資料寫入目標記憶體陣列T的觸發命令及寫入命令時,兩個記憶體組412a及414a都被啟用(enable)。目標記憶體陣列T的所選擇的目標單元及克隆記憶體陣列C的對應的克隆單元同時被觸發,這樣,資料同時被寫入目標記憶體陣列T的目標單元及克隆記憶體陣列C的對應的克隆單元。 For example, when the memory device 400a receives a trigger command and a write command for writing data to the target memory array T, both memory groups 412a and 414a are enabled. The selected target unit of the target memory array T and the corresponding clone unit of the clone memory array C are simultaneously triggered, so that the data is simultaneously written to the target unit of the target memory array T and the corresponding one of the clone memory array C Clone the unit.

如果將觸發命令及寫入命令應用於在與目標記憶體陣列T不同的一般記憶體陣列上寫入資料,則僅僅啟用包含所選擇的一般記憶體陣列的記憶體組。因此,記憶體資料僅僅被寫入一般記憶體陣列。 If the trigger command and the write command are applied to write data on a general memory array different from the target memory array T, only the memory group containing the selected general memory array is activated. Therefore, the memory data is only written to the general memory array.

在另一實施例中,當記憶體裝置400接收到儲存在目標記憶體陣列T的目標單元中的讀取資料的讀取命令時,記憶體組412a及414a皆被啟用,並且目標記憶體陣列T中的所選擇的目標單元及克隆記憶體陣列C中的對應的克隆單元同時被觸發。讀取命令被應用於目標單元及對應的克隆單元,以獲得資料D1及D2。利用ECC操作,可以執行資料D1及D2。 In another embodiment, when the memory device 400 receives the read command of the read data stored in the target unit of the target memory array T, both the memory groups 412a and 414a are activated, and the target memory array The selected target unit in T and the corresponding clone unit in the clone memory array C are simultaneously triggered. The read command is applied to the target unit and the corresponding clone unit to obtain data D1 and D2. Using the ECC operation, data D1 and D2 can be executed.

資料D1及D2(有或沒有ECC操作)被輸出到比較器420a,且比較器420a比較資料D1及D2,以判斷資料D1是否與資料D2相同。如果資料D1及D2相同,則比較器420a將資料遮 罩訊號DM1設置為預設電壓(例如,接地電壓),以指示儲存在目標記憶體陣列T及克隆記憶體陣列C中的資料中沒有錯誤。如果資料D1及D2不同,則比較器420a在資料遮罩訊號上輸出脈衝訊號,以指示儲存在目標記憶體陣列T及克隆記憶體陣列C中的資料存在錯誤。因此,資料遮罩訊號可用於確定讀取資料中是否存在錯誤。 The data D1 and D2 (with or without ECC operation) are output to the comparator 420a, and the comparator 420a compares the data D1 and D2 to determine whether the data D1 is the same as the data D2. If the data D1 and D2 are the same, the comparator 420a hides the data The mask signal DM1 is set to a preset voltage (for example, a ground voltage) to indicate that there is no error in the data stored in the target memory array T and the clone memory array C. If the data D1 and D2 are different, the comparator 420a outputs a pulse signal on the data mask signal to indicate that there is an error in the data stored in the target memory array T and the clone memory array C. Therefore, the data mask signal can be used to determine whether there is an error in reading data.

表1及表2繪示了通過比較從記憶體組<i>的目標記憶體陣列中讀取的目標資料及從記憶體組<j>的對應的克隆記憶體陣列中讀取的克隆資料的錯誤檢測的實施例。目標資料的每個資料位元將與克隆資料的對應的位元進行比較。例如,將目標資料的Data0與對應的克隆資料的Data0進行比較,將目標資料的Data1與對應的克隆資料的Data1進行比較,並依此類推。表1及表2中繪示了128位元的目標資料及克隆資料,但本發明不限制資料為任何特定的位元數。 Table 1 and Table 2 show the comparison between the target data read from the target memory array of memory group <i> and the clone data read from the corresponding clone memory array of memory group <j> Examples of error detection. Each data bit of the target data will be compared with the corresponding bit of the cloned data. For example, compare the Data0 of the target data with the Data0 of the corresponding clone data, compare the Data1 of the target data with the Data1 of the corresponding clone data, and so on. Table 1 and Table 2 depict 128-bit target data and clone data, but the present invention does not limit the data to any specific number of bits.

當目標資料與對應的克隆資料相同時,資料遮罩訊號DM輸出第一邏輯值(例如,0),第一邏輯值用於指示目標資料及克隆資料中沒有錯誤。當目標資料與對應的克隆資料不同時,資料遮罩訊號DM輸出第二邏輯值(例如,1),用於指示目標資料及克隆資料中存在錯誤。 When the target data and the corresponding clone data are the same, the data mask signal DM outputs a first logical value (for example, 0), and the first logical value is used to indicate that there is no error in the target data and the clone data. When the target data is different from the corresponding clone data, the data mask signal DM outputs a second logical value (for example, 1) to indicate that there is an error in the target data and the clone data.

Figure 108110905-A0305-02-0015-1
Figure 108110905-A0305-02-0015-1

Figure 108110905-A0305-02-0016-2
Figure 108110905-A0305-02-0016-2

請參考圖4B,記憶體裝置400b包括記憶體組412b、比較器420b以及周邊記憶體電路430b,其中記憶體組412b包括目 標記憶體陣列T及對應於目標記憶體陣列T的克隆記憶體陣列C。換言之,目標記憶體陣列T及克隆記憶體陣列C皆位於同一記憶體組412b中。圖4B中所示的比較器420b及周邊記憶體電路430b類似於圖4A中所示的比較器420a和周邊記憶體電路430a,因此,在下文中省略關於比較器420b及周邊記憶體電路430b的詳細描述。 4B, the memory device 400b includes a memory group 412b, a comparator 420b, and a peripheral memory circuit 430b, wherein the memory group 412b includes a target The target memory array T and the clone memory array C corresponding to the target memory array T. In other words, the target memory array T and the clone memory array C are both located in the same memory group 412b. The comparator 420b and the peripheral memory circuit 430b shown in FIG. 4B are similar to the comparator 420a and the peripheral memory circuit 430a shown in FIG. 4A, therefore, the details about the comparator 420b and the peripheral memory circuit 430b are omitted in the following description.

在操作中,當觸發命令及寫入命令被應用於記憶體組412b的目標記憶體陣列T時,目標記憶體陣列T及克隆記憶體陣列C皆被啟用。目標記憶體陣列T的所選擇的目標單元及克隆記憶體陣列C所對應的克隆單元同時被觸發。這樣,要寫入的資料被寫入目標記憶體陣列T所選擇的目標單元及克隆記憶體陣列C的對應的克隆單元。 In operation, when the trigger command and the write command are applied to the target memory array T of the memory group 412b, both the target memory array T and the clone memory array C are activated. The selected target unit of the target memory array T and the clone unit corresponding to the clone memory array C are simultaneously triggered. In this way, the data to be written is written to the target cell selected by the target memory array T and the corresponding clone unit of the clone memory array C.

如果將觸發命令及寫入命令應用於與目標記憶體陣列T不同的一般記憶體陣列上的寫入資料,則不觸發克隆記憶體陣列C,並且一般記憶體陣列的寫入命令不會應用於另一個記憶體陣列。 If the trigger command and the write command are applied to write data on a general memory array different from the target memory array T, the clone memory array C is not triggered, and the write command of the general memory array is not applied Another memory array.

在另一實施例中,當記憶體裝置400b接收儲存在目標記憶體陣列T中的所選擇的目標單元中的讀取資料的讀取命令時,目標記憶體陣列T中的所選擇的目標單元及克隆記憶體陣列C中的對應的克隆單元同時被觸發。讀取命令被應用於目標單元及對應的克隆單元,以獲得資料D1和D2。資料D1及D2(有或沒有ECC操作)輸出到比較器420b,比較器420b比較資料D1及D2, 以確定儲存在目標記憶體陣列T及克隆記憶體陣列C中的資料是否存在錯誤。 In another embodiment, when the memory device 400b receives the read command of the read data stored in the selected target cell in the target memory array T, the selected target cell in the target memory array T And the corresponding cloning unit in the cloning memory array C is triggered at the same time. The read command is applied to the target unit and the corresponding clone unit to obtain data D1 and D2. The data D1 and D2 (with or without ECC operation) are output to the comparator 420b, and the comparator 420b compares the data D1 and D2, To determine whether there is an error in the data stored in the target memory array T and the clone memory array C.

在本發明的一些實施例中,可以在記憶體裝置中啟用資料匯流排反轉(DBI)演算法,以便降低記憶體裝置的功耗。DBI演算法用以基於來自先前發送的資料字元(Data Word)的當前資料字元的轉換次數,來判定當前資料字元是否要被反轉。通常地,如果來自先前發送的資料字元的當前資料字元的轉換次數大於或等於當前資料的一半的比特數,則當前資料字元被反轉。例如,如果資料字元是8位元資料,則當來自先前發送的資料字元的當前資料字元的轉換次數大於或等於4時,當前資料字元將被反轉。在DRAM記憶體裝置中,資料遮罩訊號用於指示資料字元是否被反轉。特別是,當資料遮罩訊號具有邏輯值“1”時,則資料字元被反轉,而當資料遮罩訊號具有邏輯值“0”時,則資料字元不被反轉。 In some embodiments of the present invention, a data bus inversion (DBI) algorithm may be enabled in the memory device to reduce the power consumption of the memory device. The DBI algorithm is used to determine whether the current data character is to be inverted based on the number of conversions of the current data character from the previously sent data word (Data Word). Generally, if the number of conversions of the current data character from the previously transmitted data character is greater than or equal to half the number of bits of the current data, the current data character is reversed. For example, if the data character is 8-bit data, when the number of conversions of the current data character from the previously sent data character is greater than or equal to 4, the current data character will be reversed. In DRAM memory devices, the data mask signal is used to indicate whether data characters are reversed. In particular, when the data mask signal has a logic value "1", the data character is inverted, and when the data mask signal has a logic value "0", the data character is not inverted.

圖5A及圖5B繪示了當禁用DBI演算法時記憶體裝置中的訊號波形。所示訊號包括時脈訊號CLK、資料選通訊號DQS、資料輸出訊號DQ以及資料遮罩訊號DM。當禁用DBI演算法時,僅資料遮罩訊號DM可用於確定從目標記憶體陣列讀取的資料是否存在錯誤。 5A and 5B illustrate the signal waveform in the memory device when the DBI algorithm is disabled. The signals shown include clock signal CLK, data selection signal DQS, data output signal DQ and data mask signal DM. When the DBI algorithm is disabled, only the data mask signal DM can be used to determine whether there is an error in the data read from the target memory array.

如圖5A所示,如果儲存的資料中沒有錯誤,則資料遮罩訊號DM以預設電壓(例如,接地電壓準位或邏輯值“0”)輸出。如圖5B所示,當在儲存的資料中檢測到錯誤時,在資料遮罩訊號 DM中產生脈衝訊號。在資料遮罩訊號DM上產生的脈衝訊號P51及P52表示從目標記憶體陣列讀取的資料是錯誤的。讀取資料的錯誤資料字元可以根據脈衝訊號P51及P52的位置來確定。 As shown in FIG. 5A, if there is no error in the stored data, the data mask signal DM is output at a preset voltage (for example, ground voltage level or logic value "0"). As shown in Figure 5B, when an error is detected in the stored data, the signal is masked in the data Pulse signals are generated in DM. The pulse signals P51 and P52 generated on the data mask signal DM indicate that the data read from the target memory array is wrong. The error data characters of the read data can be determined according to the positions of the pulse signals P51 and P52.

圖6A至圖6B繪示了當啟用DBI演算法時記憶體裝置中的訊號波形。類似於圖5A及圖5B,所示訊號包括時脈訊號CLK、資料選通訊號DQS、資料輸出訊號DQ以及資料遮罩訊號DM。 6A-6B illustrate the signal waveforms in the memory device when the DBI algorithm is enabled. Similar to FIGS. 5A and 5B, the signals shown include a clock signal CLK, a data selection signal DQS, a data output signal DQ, and a data mask signal DM.

由於資料遮罩訊號DM還用於通過DRAM裝置中的DBI演算法指示反轉的資料字元,故當啟用DBI演算法時,僅資料遮罩訊號DM是不足以檢測儲存在目標記憶體陣列中的資料的錯誤。請參考圖6A,即使讀取資料中沒有錯誤,資料遮罩訊號DM中也有兩個脈衝訊號P60。這些脈衝訊號僅僅指示通過DBI演算法反轉對應於這些脈衝訊號的資料字元。 Since the data mask signal DM is also used to indicate the inverted data characters through the DBI algorithm in the DRAM device, when the DBI algorithm is enabled, the data mask signal DM alone is not sufficient to detect storage in the target memory array Of the information. Please refer to FIG. 6A. Even if there is no error in reading data, there are two pulse signals P60 in the data mask signal DM. These pulse signals only instruct the data characters corresponding to these pulse signals to be inverted by the DBI algorithm.

當在記憶體裝置中啟用DBI演算法時,資料遮罩訊號DM及資料輸出訊號DQ皆用於檢測儲存在目標記憶體陣列中的資料的錯誤。當在資料遮罩訊號DM中產生脈衝訊號時,判斷對應於該脈衝訊號的當前資料字元,並計算具有當前資料字元的預設邏輯值(例如,邏輯值“1”)的位元數量。然後將具有預設邏輯值的位元數量與閾值(例如,資料總位元數量的一半)進行比較,以確定當前資料字元是否具有錯誤。例如,如果具有預設邏輯值的位元數量大於或等於閾值,則將當前資料字元被判斷為錯誤資料字元。否則,當前資料字元不是錯誤的。 When the DBI algorithm is enabled in the memory device, both the data mask signal DM and the data output signal DQ are used to detect errors in the data stored in the target memory array. When a pulse signal is generated in the data mask signal DM, the current data character corresponding to the pulse signal is determined, and the number of bits with a preset logical value (eg, logical value "1") of the current data character is calculated . The number of bits with a preset logical value is then compared with a threshold (for example, half of the total number of data bits) to determine whether the current data character has an error. For example, if the number of bits with a preset logical value is greater than or equal to the threshold, the current data character is determined to be an erroneous data character. Otherwise, the current data characters are not wrong.

請參考圖6B,對應於脈衝訊號P61及P62的資料字元具 有預設邏輯值大於閾值的位元數量(例如,所有高位元),因此,對應於脈衝訊號P61及P62的資料字元是錯誤資料。 Please refer to FIG. 6B, the data characters corresponding to the pulse signals P61 and P62 There are a number of bits whose preset logical value is greater than the threshold (for example, all high-order bits). Therefore, the data characters corresponding to the pulse signals P61 and P62 are erroneous data.

請參考圖7,繪示了依據本發明實施例的錯誤檢測方法。在步驟S710中,讀取目標記憶體陣列的目標記憶體單元以獲得目標記憶體資料。在步驟S720中,讀取克隆記憶體陣列的克隆記憶體單元以獲得克隆記憶體資料,其中克隆記憶體陣列的克隆記憶體單元對應於目標記憶體陣列的目標記憶體單元。克隆記憶體陣列的克隆記憶體單元和目標記憶體陣列的目標記憶體單元可以同時被觸發,使得步驟S710和S720可以同時被執行。 Please refer to FIG. 7, which illustrates an error detection method according to an embodiment of the present invention. In step S710, the target memory unit of the target memory array is read to obtain target memory data. In step S720, the clone memory unit of the clone memory array is read to obtain clone memory data, wherein the clone memory unit of the clone memory array corresponds to the target memory unit of the target memory array. The clone memory unit of the clone memory array and the target memory unit of the target memory array can be triggered at the same time, so that steps S710 and S720 can be executed simultaneously.

在步驟S730中將目標記憶體資料與克隆記憶體資料進行比較以輸出比較訊號,並且在步驟S740中依據比較訊號判斷目標記憶體資料是否包括錯誤。 In step S730, the target memory data and the clone memory data are compared to output a comparison signal, and in step S740, it is determined whether the target memory data includes errors according to the comparison signal.

綜上所述,本發明的實施例提供具有目標記憶體陣列及克隆記憶體陣列的記憶體裝置,以及其錯誤檢測方法。克隆記憶體陣列儲存與目標記憶體陣列相同的資料,並且克隆記憶體陣列及目標記憶體陣列可以位於相同的記憶體組或不同的記憶體組中。應用於目標記憶體陣列以執行操作的命令應用於克隆記憶體陣列。為了檢測目標記憶體陣列的資料中的錯誤,儲存在目標記憶體陣列中的目標記憶體資料及儲存在克隆記憶體陣列中的克隆記憶體資料被讀取並比較,以輸出比較訊號。輸出比較訊號用於判斷是否存在錯誤。 In summary, the embodiments of the present invention provide a memory device having a target memory array and a clone memory array, and an error detection method thereof. The clone memory array stores the same data as the target memory array, and the clone memory array and the target memory array may be located in the same memory group or different memory groups. Commands applied to the target memory array to perform operations are applied to the clone memory array. In order to detect errors in the data of the target memory array, the target memory data stored in the target memory array and the clone memory data stored in the clone memory array are read and compared to output a comparison signal. The output comparison signal is used to judge whether there is an error.

雖然本發明已以實施例揭露如上,然其並非用以限定本 發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed as above with examples, it is not intended to limit the Inventions, any person with ordinary knowledge in the technical field to which they belong, can make some changes and modifications without departing from the spirit and scope of the present invention. quasi.

100:記憶體裝置 100: memory device

112:記憶體組i 112: Memory group i

1121:克隆記憶體陣列 1121: Clone memory array

114:記憶體組j 114: Memory Group j

116:記憶體組k 116: Memory group k

118:記憶體組l 118: Memory group l

120:比較器 120: Comparator

130:周邊記憶體電路 130: peripheral memory circuit

140:記憶體控制器 140: memory controller

150:模組暫存器 150: module register

D1:目標記憶體資料 D1: target memory data

D2:克隆記憶體資料 D2: Clone memory data

DQ、DQ1:資料輸出訊號 DQ, DQ1: data output signal

DM、DM1:資料遮罩訊號 DM, DM1: data mask signal

Claims (18)

一種記憶體裝置,包括:記憶體陣列,包括至少一個記憶體組,其中所述至少一個記憶體組包括:目標記憶體陣列,用以儲存資料;以及克隆記憶體陣列,對應於所述目標記憶體陣列,用以克隆儲存在所述目標記憶體陣列中的資料;其中,應用於所述目標記憶體陣列以執行操作的命令被應用於所述克隆記憶體陣列,其中,透過比較所述目標記憶體陣列中的資料以及所述克隆記憶體陣列中的資料以判斷所述目標記憶體中的資料是否包括錯誤。 A memory device includes a memory array including at least one memory group, wherein the at least one memory group includes: a target memory array for storing data; and a clone memory array corresponding to the target memory A memory array to clone data stored in the target memory array; wherein a command applied to the target memory array to perform operations is applied to the cloned memory array, wherein, by comparing the targets The data in the memory array and the data in the clone memory array are used to determine whether the data in the target memory includes errors. 申請專利範圍第1項所述的記憶體裝置,其中所述至少一個記憶體組包括第一記憶體組及第二記憶體組,所述目標記憶體陣列位於所述第一記憶體組中,以及所述克隆記憶體陣列位於所述第二記憶體組中。 The memory device of claim 1, wherein the at least one memory group includes a first memory group and a second memory group, and the target memory array is located in the first memory group, And the clone memory array is located in the second memory group. 申請專利範圍第1項所述的記憶體裝置,還包括:模組暫存器,耦接於所述記憶體陣列,用以設置所述克隆記憶體陣列的大小及位置,其中,所述命令包含觸發命令,當所述觸發命令被應用於所述目標記憶體陣列時,所述模組暫存器啟用所述目標記憶體陣列及所述克隆記憶體陣列,並同時 觸發所述目標記憶體陣列的所選擇的目標單元及所述克隆記憶體陣列所對應的克隆單元,當所述觸發命令應用於與所述目標記憶體陣列不同的一般記憶體陣列上的寫入資料,所述模組暫存器不觸發所述克隆記憶體陣列。 The memory device described in item 1 of the patent application scope further includes: a module register, coupled to the memory array, for setting the size and position of the clone memory array, wherein the command Including a trigger command, when the trigger command is applied to the target memory array, the module register activates the target memory array and the clone memory array, and at the same time Trigger the selected target unit of the target memory array and the clone unit corresponding to the clone memory array, when the trigger command is applied to writing on a general memory array different from the target memory array Data, the module register does not trigger the clone memory array. 如申請專利範圍第1項所述的記憶體裝置,其中所述目標記憶體陣列及所述克隆記憶體陣列同樣位於所述至少一記憶體組中的一者。 The memory device according to item 1 of the patent application range, wherein the target memory array and the clone memory array are also located in one of the at least one memory group. 如申請專利範圍第1項所述的記憶體裝置,還包括:周邊記憶體電路;以及記憶體控制器,用以生成對所述目標記憶體陣列及所述克隆記憶體陣列執行操作的命令。 The memory device as described in item 1 of the patent application scope further includes: a peripheral memory circuit; and a memory controller for generating commands to perform operations on the target memory array and the clone memory array. 如申請專利範圍第5項所述的記憶體裝置,其中所述命令包括用於將記憶體資料寫入所述目標記憶體陣列的目標記憶體單元的寫入命令,響應於接收到所述寫入命令,所述周邊記憶體電路將所述記憶體資料同時寫入所述目標記憶體陣列的所述目標記憶體單元及所述克隆記憶體陣列的克隆記憶體單元,其中所述克隆記憶體單元對應於所述目標記憶體單元。 The memory device according to item 5 of the patent application range, wherein the command includes a write command for writing memory data to a target memory unit of the target memory array, in response to receiving the write Input command, the peripheral memory circuit simultaneously writes the memory data into the target memory unit of the target memory array and the clone memory unit of the clone memory array, wherein the clone memory The cell corresponds to the target memory cell. 如申請專利範圍第5項所述的記憶體裝置,其中所述命令包括用於讀取所述目標記憶體陣列的目標記憶體單元的讀取命令, 響應於接收到所述讀取命令,所述周邊記憶體電路讀取所述目標記憶體陣列的所述目標記憶體單元及所述克隆記憶體陣列的克隆記憶體單元以獲得目標記憶體資料及克隆記憶體資料,其中所述克隆記憶體陣列的所述克隆記憶體單元對應於所述目標記憶體陣列的所述目標記憶體單元。 The memory device according to item 5 of the patent application range, wherein the command includes a read command for reading a target memory unit of the target memory array, In response to receiving the read command, the peripheral memory circuit reads the target memory unit of the target memory array and the clone memory unit of the clone memory array to obtain target memory data and Clone memory data, wherein the clone memory unit of the clone memory array corresponds to the target memory unit of the target memory array. 如申請專利範圍第7項所述的記憶體裝置,還包括:比較器,耦接於所述記憶體陣列及所述周邊記憶體電路,用以將所述目標記憶體資料與所述克隆記憶體資料進行比較,以輸出比較訊號,其中當所述目標記憶體資料與所述克隆記憶體資料相同時,所述比較訊號被設置為預設電壓,以及當所述目標記憶體資料與所述克隆記憶體資料不同時,在所述比較訊號上設置脈衝訊號。 The memory device according to item 7 of the patent application scope further includes: a comparator, coupled to the memory array and the peripheral memory circuit, for storing the target memory data and the clone memory Volume data is compared to output a comparison signal, wherein when the target memory data is the same as the clone memory data, the comparison signal is set to a preset voltage, and when the target memory data and the When the clone memory data is different, a pulse signal is set on the comparison signal. 如申請專利範圍第8項所述的記憶體裝置,其中所述預設電壓為第一邏輯值,所述第一邏輯值用以指示所述目標記憶體資料不包括所述錯誤,其中所述脈衝訊號為第二邏輯值,所述第二邏輯值用以指示所述目標記憶體資料包括所述錯誤。 The memory device according to item 8 of the patent application range, wherein the preset voltage is a first logical value, and the first logical value is used to indicate that the target memory data does not include the error, wherein the The pulse signal is a second logical value, and the second logical value is used to indicate that the target memory data includes the error. 如申請專利範圍第8項所述的記憶體裝置,其中當所述比較訊號不包括所述脈衝訊號時,所述記憶體控制器判斷所述目標記憶體資料不包括所述錯誤;以及當所述比較訊號包括所述脈衝訊號時,所述記憶體控制器判斷所述目標記憶體資料包括所述錯誤。 The memory device according to item 8 of the patent application range, wherein when the comparison signal does not include the pulse signal, the memory controller determines that the target memory data does not include the error; and when When the comparison signal includes the pulse signal, the memory controller determines that the target memory data includes the error. 如申請專利範圍第8項所述的記憶體裝置,其中資料匯流排反轉演算法被應用以通過所述記憶體裝置中的匯流排傳送讀取資料,以及所述記憶體控制器還用以:計算具有預設邏輯值的所述目標記憶體資料中的位元數量;判斷具有預設邏輯值的所述目標記憶體資料中的所述位元數量是否大於閾值,當具有預設邏輯值的所述目標記憶體資料中的所述位元數量大於所述閾值且所述比較訊號包括所述脈衝訊號時,所述記憶體控制器判斷所述目標記憶體資料包括所述錯誤;當具有預設邏輯值的所述目標記憶體資料中的所述位元數量不大於所述閾值或者所述比較訊號不包括所述脈衝訊號時,所述記憶體控制器判斷所述目標記憶體資料不包括所述錯誤。 A memory device as described in item 8 of the patent application range, wherein a data bus inversion algorithm is applied to transmit read data through the bus in the memory device, and the memory controller is also used to : Calculate the number of bits in the target memory data with a preset logical value; determine whether the number of bits in the target memory data with a preset logical value is greater than a threshold, when there is a preset logical value When the number of bits in the target memory data is greater than the threshold and the comparison signal includes the pulse signal, the memory controller determines that the target memory data includes the error; when having When the number of bits in the target memory data of a preset logical value is not greater than the threshold or the comparison signal does not include the pulse signal, the memory controller determines that the target memory data is not Include the error. 如申請專利範圍第7項所述的記憶體裝置,其中所述周邊記憶體電路讀取所述目標記憶體單元以獲得第一資料,其中第一錯誤更正碼操作被執行於所述第一資料以獲得所述目標記憶體資料,以及所述周邊記憶體電路讀取所述克隆記憶體單元以獲得第二資料,其中第二錯誤更正碼操作執行於所述第二資料以獲得所述克隆記憶體資料。 The memory device according to item 7 of the patent application range, wherein the peripheral memory circuit reads the target memory unit to obtain first data, wherein a first error correction code operation is performed on the first data To obtain the target memory data, and the peripheral memory circuit reads the clone memory unit to obtain second data, wherein a second error correction code operation is performed on the second data to obtain the clone memory Body data. 一種錯誤檢測方法,適用於具有至少一記憶體組的記憶體裝置,所述記憶體裝置包括目標記憶體陣列及克隆記憶體陣列,所述錯誤檢測包括以下步驟:讀取所述目標記憶體陣列的目標記憶體單元以獲得目標記憶體資料;讀取所述克隆記憶體陣列的克隆記憶體單元以獲得克隆記憶體資料,其中所述克隆記憶體陣列的所述克隆記憶體單元對應於所述目標記憶體陣列的所述目標記憶體單元;將所述目標記憶體資料與所述克隆記憶體資料進行比較以輸出比較訊號;以及依據所述比較訊號判斷所述目標記憶體資料是否包括錯誤。 An error detection method is applicable to a memory device having at least one memory group. The memory device includes a target memory array and a clone memory array. The error detection includes the following steps: reading the target memory array The target memory unit to obtain target memory data; read the clone memory unit of the clone memory array to obtain clone memory data, wherein the clone memory unit of the clone memory array corresponds to the The target memory unit of the target memory array; comparing the target memory data with the clone memory data to output a comparison signal; and judging whether the target memory data includes an error according to the comparison signal. 如申請專利範圍第13項所述的錯誤檢測方法,其中將所述目標記憶體資料與所述克隆記憶體資料進行比較以輸出所述比較訊號的步驟包括:判斷目標記憶體資料是否與所述克隆記憶體資料相同;當所述目標記憶體資料與所述克隆記憶體資料不同時,在所述比較訊號上設置脈衝訊號;以及當所述目標記憶體資料與所述克隆記憶體資料相同時,將所述比較訊號設置為預設電壓。 The error detection method according to item 13 of the patent application scope, wherein the step of comparing the target memory data with the clone memory data to output the comparison signal includes: determining whether the target memory data is in accordance with the The clone memory data is the same; when the target memory data is different from the clone memory data, a pulse signal is set on the comparison signal; and when the target memory data is the same as the clone memory data , Set the comparison signal to a preset voltage. 如申請專利範圍第14項所述的錯誤檢測方法,其中依據所述比較訊號判斷所述目標記憶體資料是否包括所述錯誤的步驟包括: 當所述比較訊號不包括所述脈衝訊號時,判斷所述目標記憶體資料不包括所述錯誤;以及當所述比較訊號包括所述脈衝訊號時,判斷所述目標記憶體資料包括所述錯誤。 The error detection method according to item 14 of the patent application scope, wherein the step of determining whether the target memory data includes the error according to the comparison signal includes: When the comparison signal does not include the pulse signal, determine that the target memory data does not include the error; and when the comparison signal includes the pulse signal, determine that the target memory data includes the error . 如申請專利範圍第14項所述的錯誤檢測方法,其中資料匯流排反轉演算法被應用以通過所述記憶體裝置中的匯流排傳送讀取資料,以及依據所述比較訊號判斷所述目標記憶體資料是否包括所述錯誤的步驟包括:計算具有預設邏輯值的所述目標記憶體資料中的位元數量;判斷具有預設邏輯值的所述目標記憶體資料中的所述位元數量是否大於閾值,當具有預設邏輯值的所述目標記憶體資料中的所述位元數量大於所述閾值且所述比較訊號包括所述脈衝訊號時,判斷所述目標記憶體資料包括所述錯誤;當具有預設邏輯值的所述目標記憶體資料中的所述位元數量不大於所述閾值或者所述比較訊號不包括所述脈衝訊號時,判斷所述目標記憶體資料不包括所述錯誤。 An error detection method as described in item 14 of the patent application range, in which a data bus inversion algorithm is applied to transmit read data through the bus in the memory device, and determine the target based on the comparison signal The step of whether the memory data includes the error includes: calculating the number of bits in the target memory data having a preset logical value; determining the bits in the target memory data having a preset logical value Whether the number is greater than a threshold, when the number of bits in the target memory data with a preset logical value is greater than the threshold and the comparison signal includes the pulse signal, it is determined that the target memory data includes all The error; when the number of bits in the target memory data with a preset logical value is not greater than the threshold or the comparison signal does not include the pulse signal, it is determined that the target memory data does not include The error. 如申請專利範圍第13項所述的錯誤檢測方法,其中讀取所述目標記憶體陣列的所述目標記憶體單元以獲得所述目標記憶體資料以及讀取所述克隆記憶體陣列的所述克隆記憶體 單元以獲得所述克隆記憶體資料包括:讀取所述目標記憶體單元以獲得第一資料,並對所述第一資料執行第一錯誤更正碼操作,以獲得所述目標記憶體陣列的所述目標記憶體單元;以及讀取所述克隆記憶體單元以獲得第二資料,並對所述第二資料執行第二錯誤更正碼操作,以獲得所述克隆記憶體資料。 The error detection method according to item 13 of the patent application scope, wherein the target memory unit of the target memory array is read to obtain the target memory data and the clone memory array is read Clone memory The unit obtaining the cloned memory data includes: reading the target memory unit to obtain the first data, and performing a first error correction code operation on the first data to obtain the location of the target memory array The target memory unit; and reading the clone memory unit to obtain second data, and performing a second error correction code operation on the second data to obtain the clone memory data. 如申請專利範圍第13項所述的錯誤檢測方法,其中所述記憶體裝置還包括資料輸出腳位及資料遮罩腳位,以及所述比較訊號被傳送至所述資料遮罩腳位,而所述讀取資料被傳送至所述資料輸出腳位。 An error detection method as described in item 13 of the patent application range, wherein the memory device further includes a data output pin and a data mask pin, and the comparison signal is transmitted to the data mask pin, and The read data is sent to the data output pin.
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