六、發明說明： ， 【發明所屬之技術領域】 本發…關於-觀·^轉子電鱗能夠充電的充電電池的 2電池賴魏，特娜_—翻於充電電池髓電路的延 避Μ»路。 【先前技術】 極端子㈣'也的保護電路是與充電電池—起被收放在具有正 _ 、極端子的電池單元（電池組）内。在制時，電池單 Z正極端子和負極端子之間連接有作為負載的照相機等裝置， 放恭狀被連接_池單元時，電池單元内的充電1池就處於 電雷、 乍。另一方面，在對電池單元内的充 極維；了充电之際’充電器被連接在電池單⑽正極端子和負 知子之間，充電電池便處於充電的狀態。 、 而連’在被收放在電池單元内的充電電池上根據各種裝置 中，去匕3有鎳鑛電池、錄汞電池、瓣子電池等各種電池。其 即，1^"電池和鎳汞電池在電池容量未使_為G就充電的話， 此因放電與充電時’會降低具有的電親力特性，如 記憶效^的放電與充電所導致的電池能力下降的效應可稱之為 為充:::面’雖然鋰離子電池沒有上述的記憶效應，而適合作 .- 一/、因過放龟使得電池電壓比規定電壓更低 3 1328325 時’會使電池的構成物質變f;變成過放電狀態而使電池壽命變 Μ。另外，在鋰離子電池中，利用充電器充電的過程中，即使達 到充滿電的H電池電壓還持續上升，絲成為過充電狀態， 這樣’-旦成為過充電狀態，在麟子電池中，錄屬的析出電 極間就有可能發生短路，又，當雜子電池的正極端子和負極端 子之間處於鱗狀態時，往往流職大敝電電流，而會成為過 電流狀態。 在電池單兀裏和充電電池一起裝入的充電電池保護電路，特 別疋裡離子電池㈣充電電池保護電路具有保護充電電池的功 能’它可檢測上述的過充電狀態、過放電狀態及過電流狀態，一 旦分別檢測出這些狀態時’則通過斷開充電電流及放電電流來進 行保。蒦口此’充電電池保護電路包含了過充電檢測電路、過放 電檢測電路及過電流檢測電路。 另一方面，在充電或放電中，在短時間内電流或電壓有時會 因某種原因而雜大的變動，_會有上述短時間内的暫態變動 發生，但實際上其係不會成為過充電、過放電或過電流狀態，因 有必要預先將過充電檢啦路、過放電檢測電路及過電流檢測 =路置於不隨著a樣的短㈣的電流、錢的變動而動作的狀 所以在這些過充電檢測電路、過放電檢測電路及過電流檢測 電路中係分職置了處於不感應狀態的减應時間蚊電路，即 :_ ”不因電"IL電壓的短時間變動而進行保護動作，使各檢 測電路僅在特定_喊於不動作狀態，更具體地說，係為了這 ΙΪ28325 些不感應時㈣設置了延遲電路，上相特定時間雜設定為延 遲電路的延遲時間。 在乂些充電電池保護電路的過充電檢測電路、過放電檢測電 路及過1流檢測電路巾’作為麟過電流檢測電路的延遲電路有 專利文獻1日本專财請歷·顺7〇綱書巾所减的延遲電 路。所提出的延遲電路具有以下結構，當檢測過電流時，來自時 鐘振盪②的日横彳§號關始計數，對時鐘信號計數到規定的值， 即使計數到規定的值時仍檢測_電流的話，就輪出有效檢測信 ^。這時，過電流檢測電路被連制—電阻，此電阻制以檢測 流過負载的貞龍流，此貞载指的是被連接到電池單元的農置， 利用過電流檢測電路係可檢測出該電_兩端電壓以控制延遲時 間。在該結構中，即使過電流的檢測信號有暫態的變動，也能夠 正確地一直計數到規定的值。 請參照第6 ® ’顯_是财職設置在含有轉子電池等 充電電池的電池單元内的過電流檢測電路1G的其他的實施例。圖 中所示的電池單元u具有作為輸出埠的正極端子ι〇ι和負極端子 ⑽，在該正極端子101和負極端？搬之間放電時連接有照相機 等負載’充電時連接有充電器。 圖中所示的電池單元n的特徵在於：過電流檢測電路ι〇、鋰 離子電池等充電電池11、電流檢測電阻112及放電控制開關出， 然而’實際上，在過電流檢測電路1〇之外，在電池單元U内還 設置有圖絲示的過放電制電路及過充電檢_路。為了簡2 1328325 說明，這些過放電檢測電錢過充電檢測電路在第6圖中係被省 略。 在電池單元u的正極端子1〇1上連接有構成放電控綱關 的P通道FET的汲極，在其源極連接有充電電池⑴的陰極。 另方面，在充電電池lu的陽極和陰極端子碰之間連接有電 =檢測電請，在該電流檢戦阻m的兩端連接有過電流 電路10。 翥 具體地說，過電流檢測電路10是由過電流檢測部2〇和設定 了規定的延遲時間的延遲電路21所構成，過電流檢測部20被連 接在電流檢測電阻112的兩端，由過電流檢測部檢測流過該電 流檢測電阻112的電流所產生的電壓降。 。。過電流檢測部20具有將閾值電墨設定為基準電屋的電壓比較 為’在該電壓比較n中，將電流檢_且ιΐ2兩端的電壓降與基 _準電壓進行比較。在本例中，電流檢測電阻112兩端的電壓降比 基準電壓更小時’電壓比較器就向延遲電路Μ輸出邏輯‘‘〇，，的 電昼的輸出信號，另-方面，電流檢測電阻U2兩端的電鱗比 基準電壓更大時，判定為過電流，就向延遲電路21輸出邏輯丫 的電壓的輸出信號。 在這裏，在電池單元的正極端子1〇1和負極端子1〇2之間連 ，有負载時，充電電池m聽於放電的狀態。在該狀態，過電 流檢測部20向延遲電路21輸出邏輯“〇,，的電壓的輸出信號，來 自延遲電路21的低電壓錢被供給至構成放·關113的p通道 FET。結果，、Λ ° 在〉又有檢測到過電流的狀態下，放電控制開關u 處於接通的狀態。 、兩… 面，當流過負載的電流變大，電流檢測電阻112兩端 ^[降超過馳(thresh。—)時，過電流檢測部⑼就以高電 為輸出錢輸㈣延遲電路。延遲電路21，即使在經過了 ^的延遲時間的時刻還得到來自過電流檢測部如的高電壓^號 、广 ' 匕將问電壓抬號輸出到放電控制開關113,使放電控制開 知處於斷開狀態，結果放電就停止。 k樣’延遲電路2H更進行了監視過電流狀態在規定的延遲時 動作。_設置觀遲電路2ι，只要在未達到規定延 ^曰的時㈣’即使產生暫時的過電流狀態，延遲電路21也不 將南電壓信號輪出到放_刪丨13。換句話說，只要是過電流 狀態在規定_料間時魄齡It況下，放栖剛113處 於斷開的狀態，在該結射，即便過電餘態 ::輯控制開㈣不處於接通的狀態，^^ 出暫時產生的過電流。 這種作為負載連接在電池單元上的裝置負載，在裝置工作a ^不=作時之間變動鼓，結果會造成在放電狀態流過負載⑻ «•的又動有又大的傾向’在—些極·情況下，正極端子和負名 端子之間還會有短_情形產生。 弟6圖所示的電流檢測電阻112的電阻值，可以預測到㈣ 電控制開關113產生的損失_，續购_電錄測電阻⑴ 1328325 引起的損失。另一方面，第6圖所示的延遲電路的延遲時間與負 載電流的大小無關是—定的。這樣，在賴具有特定延遲時間的 L遲電路4 ’在特定的延遲時間内，大的貞载電流瞬間地流過構 成電池單元的放電控制開關113的FET。結果，對構成該放電控 制開關113的FET產生躺影響，根據情⑽不同，有時還會導 致FET的損壞。Sixth, the invention description: , [Technical field to which the invention belongs] The present invention... 2 batteries Lai Wei, Tina _ 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻 翻road. [Prior Art] The protection circuit of the terminal (four)' is also housed in a battery unit (battery pack) having positive _ and extreme terminals together with the rechargeable battery. At the time of manufacture, a device such as a camera as a load is connected between the positive terminal and the negative terminal of the battery unit, and when the cell unit is connected to the cell unit, the battery 1 in the battery cell is in an electric charge or a helium. On the other hand, in the charging of the battery unit; when the charging is performed, the charger is connected between the positive terminal of the battery unit (10) and the negative terminal, and the rechargeable battery is charged. In addition to the various devices in the rechargeable battery that is housed in the battery unit, there are various batteries such as a nickel ore battery, a mercury recording battery, and a petal battery. That is, 1^"battery and nickel-mercury batteries do not cause _ to be charged when the battery capacity is charged, which may reduce the electrical intrinsic characteristics due to discharge and charging, such as the discharge and charging of the memory effect The effect of the battery capacity drop can be called the charge::: face' Although the lithium ion battery does not have the above memory effect, it is suitable for use. - A /, due to over-the-turbine, the battery voltage is lower than the specified voltage 3 1328325 'The constituent material of the battery will be changed to f; the over-discharge state will become the battery life. In addition, in the lithium ion battery, during the charging process by the charger, even if the voltage of the fully charged H battery continues to rise, the wire becomes overcharged, so that it becomes an overcharged state, recorded in the lindible battery. A short circuit may occur between the deposition electrodes of the genus, and when the positive electrode terminal and the negative electrode terminal of the hybrid battery are in a scale state, the current is often increased and the current is overcurrent. The rechargeable battery protection circuit is installed in the battery unit together with the rechargeable battery, and the special battery (four) rechargeable battery protection circuit has the function of protecting the rechargeable battery. It can detect the above-mentioned overcharge state, overdischarge state and overcurrent state. Once these states are detected separately, 'protected by disconnecting the charging current and the discharging current. The rechargeable battery protection circuit includes an overcharge detection circuit, an overdischarge detection circuit, and an overcurrent detection circuit. On the other hand, in charging or discharging, the current or voltage may vary greatly for some reason in a short period of time, and _ there may be a transient change in the short time mentioned above, but in reality, it will not In the state of overcharging, overdischarging, or overcurrent, it is necessary to operate the overcharge detection circuit, the overdischarge detection circuit, and the overcurrent detection = path in advance with a short (four) current and money fluctuation. Therefore, in these overcharge detection circuits, overdischarge detection circuits, and overcurrent detection circuits, the ensoring time mosquito circuit in the non-inductive state is divided, that is, _ "not due to electricity" The protection operation is changed so that each detection circuit is only in a specific state, and more specifically, in order to prevent the 28325 from being inductive (4), a delay circuit is provided, and the upper phase is set to a delay of the delay circuit. The overcharge detection circuit, the overdischarge detection circuit, and the overcurrent detection circuit of the rechargeable battery protection circuit are used as the delay circuit of the lining overcurrent detection circuit. The delay circuit is reduced by the calendar. The proposed delay circuit has the following structure. When an overcurrent is detected, the day 彳 § from the clock oscillation 2 is counted off, and the clock signal is counted. The specified value, even if the _ current is detected when the value is counted, the valid detection signal is turned on. At this time, the overcurrent detection circuit is connected to a resistor, which is used to detect the turbulent flow flowing through the load. This load refers to the farm connected to the battery unit, and the overcurrent detection circuit can detect the voltage between the two ends to control the delay time. In this structure, even if the detection signal of the overcurrent has a transient state In addition, it is possible to accurately count up to a predetermined value. Please refer to the other example of the overcurrent detecting circuit 1G in which the battery is installed in a battery unit including a rechargeable battery such as a rotor battery. The battery unit u shown has a positive electrode terminal ι〇ι and a negative electrode terminal (10) as an output port, and a load such as a camera is connected when discharging between the positive electrode terminal 101 and the negative electrode terminal. The battery unit n shown in the figure is characterized in that the overcurrent detecting circuit ι, the rechargeable battery 11 such as a lithium ion battery, the current detecting resistor 112, and the discharging control switch are output, but 'actually, in the overcurrent detecting circuit In addition to 1〇, an overdischarge circuit and an overcharge detection circuit are provided in the battery unit U. These overdischarge detection money overcharge detection circuits are shown in Fig. 6 for the description of Jan. 2 1328325. The drain of the P-channel FET constituting the discharge control is connected to the positive terminal 1〇1 of the battery unit u, and the cathode of the rechargeable battery (1) is connected to the source. In addition, the anode of the rechargeable battery lu The electric current is connected to the cathode terminal, and the overcurrent circuit 10 is connected to both ends of the current detecting resistor m. Specifically, the overcurrent detecting circuit 10 is composed of an overcurrent detecting unit 2 The delay circuit 21 is provided with a predetermined delay time. The overcurrent detecting unit 20 is connected to both ends of the current detecting resistor 112, and the overcurrent detecting unit detects the electric current generated by the current flowing through the current detecting resistor 112. Drop. . . The overcurrent detecting unit 20 has a voltage comparison in which the threshold electro-ink is set as the reference electric house. In the voltage comparison n, the voltage drop across the current detection and ιΐ2 is compared with the base-quasi-voltage. In this example, the voltage drop across the current sense resistor 112 is less than the reference voltage. The voltage comparator outputs a logic ''〇', the output signal of the power, and the other, the current sense resistor U2. When the electric scale of the end is larger than the reference voltage, it is determined that the current is excessive, and the output signal of the voltage of the logical chirp is output to the delay circuit 21. Here, between the positive terminal 1〇1 and the negative terminal 1〇2 of the battery unit, when there is a load, the rechargeable battery m is in a state of being discharged. In this state, the overcurrent detecting unit 20 outputs an output signal of a logic "〇" to the delay circuit 21, and the low voltage money from the delay circuit 21 is supplied to the p-channel FET constituting the discharge/off 113. As a result, ° In the state where the overcurrent is detected, the discharge control switch u is in the ON state. When the current flowing through the load becomes larger, the current detecting resistor 112 is both ends [[Throws over) (thresh) In the case of -), the overcurrent detecting unit (9) outputs the (four) delay circuit with high power as the output. The delay circuit 21 obtains the high voltage ^ from the overcurrent detecting unit, even when the delay time has elapsed. When the voltage rise number is output to the discharge control switch 113, the discharge control is turned off, and the discharge is stopped. The k-type delay circuit 2H further monitors the overcurrent state to operate at a predetermined delay. _Set the watch circuit 2ι, as long as the specified delay is not reached (four) 'even if a temporary overcurrent condition occurs, the delay circuit 21 does not turn the south voltage signal out to the _ 丨 13. In other words, as long as Is overpowered When the state is between the predetermined conditions, the age of the release is 113, and the release is just off. In this case, even if the over-current state is over: (4) is not in the on state, ^^ The overcurrent generated. The load of the device connected to the battery unit as a load changes the drum between when the device operates a ^ not =, and the result is that the load is discharged in the discharge state (8) «• The tendency 'in the case of some poles, there will be a short _ situation between the positive terminal and the negative terminal. The resistance value of the current detecting resistor 112 shown in the figure 6 can be predicted to (4) the electric control switch 113 is generated. Loss_, renewed_Electric recording resistance (1) 1328325 caused loss. On the other hand, the delay time of the delay circuit shown in Figure 6 is independent of the magnitude of the load current. Thus, there is a specific delay The L-latency circuit 4' of time, during a specific delay time, a large load current instantaneously flows through the FETs constituting the discharge control switch 113 of the battery cell. As a result, the FET constituting the discharge control switch 113 is affected by the lie, according to Love (10) is different, there is It will lead to the destruction of the FET.
“曼第7 ®具體制上述之論點。第7圖表示第6圖所示的 過電流檢測電路1Q的特性，第7圖中，橫軸表示流經電流檢測電 阻112的電流1，縱軸表示延遲電路21的延遲時間T。從圖中可 以清楚看當流經電流制電阻m的電流〗超過設定電流水準 W時’延遲電路21具有僅使過電流檢測部20的輸出延遲一定的 延遲時間Td的特性。還有，流經電流檢測電阻ιΐ2的電流j，實 際j在過電流檢測部2〇中被變換到為電流檢測電阻I!]的兩端 電壓，以將該兩端電壓與閾值電壓比較。 八有圖示的特性的過電流檢測電路〗〇時，當超過設定 電流水準1d的電流暫時流經電流檢測電阻m，在特定的延遲時 回到原來的正常的電流轉時，放電控制關⑴與延 遲電Γ1的輸出相比在一定的時間内維持在接通狀態。因此，大 過放電控制開關113，結果，往往損壞 控制 開關113的FET。 @方面’如上述的日本專利旁請2⑽㈣說明堂中所述 的延遲電路，細彻物輪細時=計 1328325 數的形式的延遲電路中，可以設想埠過預先設定多個計數器的計· 數值’能夠使不感應時間數字式地臺階式變化。但是，這樣—來，- 在數字式地使不感應時間變化的延遲電路中，不能根據負載電流 即時地改變延遲關。，在有短料賴賴電流急劇I變 化時，上制延遲電路不能跟_變化，便不缺止構成放電控 制開關的元件的破壞。 【發明内容】 士本發明的目的是提供一種過電流檢測電路，該電路即使在電麝 流暫態並且急劇地變化時也能夠防止電池單㈣的内部元件的破 檢測電路 本發明的另—目的是提供-種電池單元，該電池單元具有即 ^產生急劇的電流變化也能夠防止放電控觸_破壞的過電流 據的再-目的是提供—種延遲電路，該延遲電路能夠根 據負載電流連續地使延遲特性變化。 採用本發明的第！方案，可 -對輸入輸出埠的，和上述充電電池、連接在上述 控制開關、連接在上述一對輸入輪出 池的另-個電極之間的電流檢另-個埠和上述充電電 路十，具有：連接在上述電流檢測電元的過電流檢測電 电阻的兩端、將該電流檢測電 1328325 阻的兩端電壓與規定的基準電壓進行比較並輸出比較結果的過電 流檢測部；當上述電流檢測電阻的兩端電壓顯示超過上述基準電 壓的信號作為上述比較結果被給出時，就使該比較結果僅延遲規 定的延遲時間，當超過該規定延遲時間、上述兩端電壓超過上述 基準電壓時’就使上述放電開關斷開的延遲電路；上述延遲電路 具有監視在上述放電控制開關的接通電阻的兩端所產生的電壓降 % 的監視裝置；和具有因上述接通電阻中流過的電流所產生的上述 接通電阻_賴降超過規定的電壓時，延遲咖具有隨著流過 上述接通電財的電流敎而從上述規定的延遲時_擬地減少 的特性的模擬延遲部。 、知用本發明的第2方案’可以獲得具有以下特徵的過電流檢 測電路’上述監視裝置由連接在上述放電控制開關兩端的、輸出 與上述接通電_電餅減的電流的鶴電路所構成；另一方 面，上述模擬延遲部具有，由來自上述 控制的雷、^/5 ^ 电抓進仃電流 爾嫩，職_和電容的 a ^的電壓與預定的進行比較的比較電路。 採用本發明的第3 制電路，上錢電關由啦構成㉞具有町特徵的過電流控 採用本發明的第4方案， 具有：—對輸人輪料、充特徵的電池單元， 的-個埠和上述充電電池的一個雷、在上述一對輪入輪出埠 在上述-對輸入輪出埠的另一個==:制開關、連接 过充電电池的另-個電極 之間的電流檢測電阻；連上 流檢測電阻的兩端電測電阻的兩端、將該電 規疋的基準電㈣行比較，並輸出比較 ，果的過電流檢測部；— 過上述基準— "^測電阻的兩端電壓顯示超 早僅延2 作為上耻較結賴給㈣，使該比較結 果僅延長規定的延遲 ^ 壓超過上述基準賴時規疋延遲時間、上述兩端電 述延遲1且古，就使上述放電開關斷開的延遲電路；上 產生的，I視在上述放電控制開關的接通電阻的兩端所 麝 流所產生^^2置，和具有因流過上述接通電電阻中的電 述接通電阻間的電壓降超過規定 =過上述接通電阻中的電流變大而從上述規定的延二 杈挺地減少的特性的模擬延遲部。 5方案，可以麟具有以下特_過電流檢 一-在5又置了具有—對輸入輸出埠、充電電池、連接在上述 對輸入輪出埠的一個痒和上述充電電池的一個電極之間的放電 控制開關、連接在上述—對輸人輸料的另—個埠和上述充電電 池的另一個電極之_電流檢測電阻的電池單㈣過電流檢測電 路中-有.連接在上電流檢測電阻的兩端、_電流檢測電 =兩端電壓與規定的鲜糕進行隨並輸姐較結果的過電 流檢測部；當上㈣流檢測電阻的兩端霞·超過上述基準電 壓的信號料上述比較結給㈣，賊該比較結果僅延遲規 定的延遲時間’當超過該規定延遲時間、上述兩端電㈣過上述 基準電壓時，就使上述放電開_開的延遲電路；上述延遲電路 11 1328325 •'、有皿視在上述測電阻的兩端所產生的電壓降的監視裝 置，和具有因流過上述電流檢财的電流所產生的上述電壓降超 過設定的電壓時’延遲時間隨著流過上述電流檢測電阻中的電流 變大而從上述規定魏遲時間模擬地減少的特性的模擬延遲部。 採用本發明的第6方案’可以獲得具有以下特徵的延遲電路， 具有：供給與規定的餘元件兩端的麵_對應的電流的電流 源’與該電流料連的電容，及將在該電流源和電容的共同連接 鲁點的電壓與預定的電壓進行比較的比較電路；可以模擬地改變延 遲時間。 【實施方式】 • 請參照第1圖，所示的是本發明的一個實施例的電池單元⑴ 的大致結構。第1圖所示的電池單元lla在使用具有檢測出由放 電控制開關m的接通電雜產生的降的功能的帶電壓檢測 _ 功能的延遲電路25作為過電流檢測電路2〇a這一點上，與第6圖 的過電流檢測電路20不同。如第i圖所示，帶電壓檢測功能的延 遲電路25被連接到由P通道FETW冓成的放電控制開mi3的輸 入輸出埠（即，P通道FET的源極、汲極檢測出由該p通道 FET的接通電電阻的電壓降’具有根據該電壓降使延遲時間類比 地，即連續地變化的特性。 請參照第2 ffi ’所示的是第1圖給出的帶電屢檢測功能的延 遲電路25的特性’橫軸是流過放電控制開關Π3的電流j，縱轴 12 «οοζ；) 2▼讀檢測功能的延遲電路25峡遲時間τ。從第2圖可以青 ^看出’當流過放電控制關113的電流I超過設定電流水準I 8守、’該延遲電路25就處於使過電流檢測部施的輪出延遲規 # 叼的狀態。還有，-旦電流1變大’帶電壓檢測功能的 匕…路25的延遲時間就根據電流〗水準的增加，從^至丁&模 =二連續地變短。通過使用具有這種特性的帶電壓檢測二 士*電路25，在大電流1短時間瞬間地流過放電控制開關m Z極短的延遲時間後’能夠使放電控制開_ 113處於斷開的狀 態，私果，能夠防以冓成放電開關113的FET的破壞。 山第1圖所示的構成放電開關113的P通道FET具有連接到正 =端子1〇1的祕、連接到充電電池lu陰極的源極及連接到帶 電壓檢測魏的延遲電路25的閘極，電流檢測電阻⑴ 子102連接。 % 另方面’放電控制開關113由N通道FET構成時，可以採 用源極連接在負極端子舰、汲極連接在域電池m的陽極的社 構’同時對於閘極給與與第1圖相反的極性的信號的結構。另外， 該場合’電流檢測電阻112被連接在正極端子1〇1和充電電池⑴ 的陰歡間。由於雜構本身已秘壯m林再詳述。 '其-人’晴參照第3圖，就第丨_示的帶龍檢測功能的延 遲宅路25的具舰構進行制。圖示的帶頓檢測魏的延遲電 路25具有作為監視由？通道航所構成的放電控制電路⑴的輸 入輸出埠_接通電電_電餅的監視電路的差動電路251。 13 1328325 即，差動電路251被連接在P通道FET的源極和汲極之間，監視 流過该FET的接通電電阻的電流所產生的電壓降，將監視到的電 壓降變換為電流，輸出到延遲部。第3圖所示的延遲部，由於具 有本如第2圖所示的模擬的延遲特性，在這裏就稱為模擬延遲部。 在這裏，P通道FET的源極及汲極的電壓分別為Vcc及cS。 圖不的類比延遲部具有由來自差動電路251的電流進行電流 控制的電流源252。電容253的一端與該電流源252串連，電容 253的另一端接地。另外，電流源252和電容253的共同連接點連 接在比較電路254的一端的輸入埠，在該比較電路254的另一端 的輸入埠連接有供給預定的電壓的電壓源255。在該構成中，電容 益253通過來自電流源252的電流充電，為此，比較電路254的 一端的輸入埠的電壓隨電流源252的電流而上升。 在這裏，在流過放電控制開關113的電流急劇地增加時，差 動電路251的電流也急劇地增加，結果從電流源252供給電容器 253的電流也急劇地增加。因此，電容器乃3的電壓快速地上升、 以短時間就超過電壓源255的電壓，在短時間内從比較電路⑼ 輸出輸出信號。 右結構為根據比較電路254的輪出健及過電流檢測部的輸 出k號，使放f控綱關113處於斷開狀態，則可—構成該放電 控制開關113在短時_從接通的狀態切換為斷開的狀態，具有 短的延遲時間的延遲電路。 另一方面，流過放電控制電路113的電流緩慢地增加時，差 13-28325 動電路=的電流也慢慢增加，從電流源252供給電容器⑸的 電流也恢㈣加。因此，由於電容器253的電壓也慢慢上升，因 而要超過電壓源255所設定的電壓f要較長㈣間。結果，可得 到如第2圖所示的電流j、延遲時間丁的特性。"Mann 7th specifically describes the above-mentioned argument. Fig. 7 shows the characteristics of the overcurrent detecting circuit 1Q shown in Fig. 6. In Fig. 7, the horizontal axis represents the current 1 flowing through the current detecting resistor 112, and the vertical axis represents The delay time T of the delay circuit 21. As is clear from the figure, when the current flowing through the current resistor m exceeds the set current level W, the delay circuit 21 has a delay time Td which delays only the output of the overcurrent detecting unit 20 by a certain amount. Further, the current j flowing through the current detecting resistor ι2 is actually converted to the voltage across the current detecting resistor I! in the overcurrent detecting portion 2A to apply the voltage between the both ends and the threshold voltage. Comparison. When the overcurrent detection circuit with the characteristics shown in Fig. 〇 is ,, when the current exceeding the set current level 1d temporarily flows through the current detection resistor m, and returns to the original normal current rotation at a specific delay, the discharge control The off (1) is maintained in the on state for a certain period of time compared to the output of the delay cell 1. Therefore, the overdischarge control switch 113 is large, and as a result, the FET of the control switch 113 is often damaged. @面' Please refer to 2(10)(4) for the delay circuit described in the church. In the delay circuit of the fine-grained wheel = 1328325, it is conceivable that the count-value of the multiple counters can be set to enable the non-induction time digital The step change of the ground. However, in this way, in the delay circuit that digitally causes the time change without induction, the delay off cannot be instantaneously changed according to the load current. When there is a sudden change in the current of the short-term current, the upper The delay circuit cannot be changed with _, and the destruction of the components constituting the discharge control switch is not missed. SUMMARY OF THE INVENTION The object of the present invention is to provide an overcurrent detection circuit that is transient and sharply It is also possible to prevent the internal component of the battery unit (four) from being broken and detecting the circuit. Another object of the present invention is to provide a battery unit having an overcurrent which can generate a sudden current change and prevent discharge control from being broken. A further object is to provide a delay circuit capable of continuously varying the delay characteristics in accordance with the load current. The first solution, the input and output 埠, and the above-mentioned rechargeable battery, the current check connected between the above control switch, the other electrode connected to the pair of input wheel outlets, and the above charging The circuit 10 includes: an overcurrent detecting unit that is connected to both ends of the overcurrent detecting resistor of the current detecting cell, compares the voltage between the two ends of the current detecting circuit 1328325 with a predetermined reference voltage, and outputs a comparison result; When a signal indicating that the voltage across the current detecting resistor exceeds the reference voltage is given as the comparison result, the comparison result is delayed by only a predetermined delay time, and when the predetermined delay time is exceeded, the voltage at both ends exceeds the above a delay circuit for turning off the discharge switch at the reference voltage; the delay circuit having a monitoring device for monitoring a voltage drop % generated at both ends of the on-resistance of the discharge control switch; and having a current due to the on-resistance When the above-mentioned on-resistance generated by the passing current exceeds a predetermined voltage, the delay coffee has to flow with the above The analog delay unit that turns on the current of the money and the characteristic that is artificially reduced from the predetermined delay. According to a second aspect of the present invention, an overcurrent detecting circuit having the following characteristics can be obtained. The monitoring device includes a crane circuit that is connected to both ends of the discharge control switch and outputs a current that is subtracted from the on-state electric cake. On the other hand, the analog delay unit has a comparison circuit for comparing the voltage of a ^ from the above-mentioned control, the voltage of the voltage, and the voltage of a ^ and the capacitor. According to the third system of the present invention, the overcurrent control having the characteristics of the line 34 is adopted, and the fourth aspect of the present invention is adopted, which has: - a battery unit for inputting a wheel and a charging feature埠 and one of the above-mentioned rechargeable batteries, a current detecting resistor between the pair of wheel-in and the other of the above-mentioned pair of input===: switch, and another electrode connected to the rechargeable battery Connect the two ends of the electric resistance of the upper limit of the upper sense resistor, compare the reference electric (four) lines of the electric gauge, and output the comparison, the overcurrent detection unit; - the above reference - " The terminal voltage display is only 2 times as long as the upper shame is given to the fourth (4), so that the comparison result is only extended by the specified delay. The pressure exceeds the delay time of the reference time, and the delay of the two ends is 1 and the old The delay circuit in which the discharge switch is turned off; the upper portion is generated by the turbulence generated at both ends of the on-resistance of the discharge control switch, and the electricity generated by flowing through the on-resistance The voltage drop between the on-resistances exceeds the gauge = Delay through the analog portion of the current on-resistance becomes large and the predetermined delay from two branches of a tree to reduce the very characteristics. In the 5th scheme, the lining has the following special _ overcurrent detection - at 5, there is again - between the input and output 埠, the rechargeable battery, an itch connected to the input wheel and an electrode of the above rechargeable battery The discharge control switch is connected to the battery cell (four) overcurrent detecting circuit of the other one of the other electrodes of the charging battery and the current detecting resistor of the other electrode of the rechargeable battery. Both ends, _ current detection electricity = the voltage across the two ends and the specified fresh cake to carry out the over-current detection part of the result of the transmission of the sister; when the upper end of the (four) flow detection resistance Xia · exceeds the above reference voltage signal material (4), the thief compares the result to only a predetermined delay time. When the predetermined delay time exceeds the predetermined delay time, the above-mentioned two-terminal power (four) passes the reference voltage, and the above-mentioned discharge open-open delay circuit; the delay circuit 11 1328325 • ' a monitoring device for reflecting a voltage drop generated at both ends of the resistance, and a voltage drop generated by a current flowing through the current detection exceeding a set voltage The time delay period is an analog delay portion that has a characteristic that is analogously reduced from the above-described predetermined delay time as the current flowing through the current detecting resistor increases. According to the sixth aspect of the present invention, it is possible to obtain a delay circuit having the following features: a current source that supplies a current corresponding to a surface _ at both ends of a predetermined remaining element, and a capacitance connected to the current source, and a current source to be used in the current source A comparison circuit that compares the voltage of the Lu point with the predetermined voltage and the capacitor; the delay time can be changed analogously. [Embodiment] Referring to Fig. 1, there is shown a schematic configuration of a battery unit (1) according to an embodiment of the present invention. The battery unit 11a shown in Fig. 1 is used as the overcurrent detecting circuit 2〇a using the delay circuit 25 having the function of detecting the voltage generated by the on-circuit of the discharge control switch m. This is different from the overcurrent detecting circuit 20 of FIG. As shown in the figure i, the delay circuit 25 with the voltage detection function is connected to the input/output port of the discharge control switch mi3 formed by the P-channel FET W (ie, the source and drain of the P-channel FET are detected by the p The voltage drop ' of the on-resistance of the channel FET has a characteristic that the delay time is analogously changed according to the voltage drop, that is, continuously changing. Please refer to the second ffi ' which is the charge detection function shown in FIG. The characteristic 'the horizontal axis of the delay circuit 25 is the current j flowing through the discharge control switch Π3, and the vertical axis 12 «οοζ;) 2 ▼ The delay circuit 25 of the read detection function 25 is delayed by τ. It can be seen from Fig. 2 that 'when the current I flowing through the discharge control switch 113 exceeds the set current level I8, the delay circuit 25 is in the state of the run-off delay gauge #叼 applied by the overcurrent detecting unit. . Further, the current 1 becomes large. The delay time of the circuit 25 with the voltage detecting function is continuously shortened from ^ to D & amp = 2 according to the increase in the current level. By using the band voltage detecting two-six circuit 25 having such a characteristic, after the large current 1 instantaneously flows through the discharge control switch m Z for a short delay time, the discharge control ON_113 can be turned off. , the private fruit, can prevent the destruction of the FET that is turned into the discharge switch 113. The P-channel FET constituting the discharge switch 113 shown in Fig. 1 has a connection to the positive = terminal 1 〇 1, a source connected to the cathode of the rechargeable battery, and a gate connected to the delay circuit 25 with voltage detection Wei. The current detecting resistor (1) is connected to the sub 102. In the other aspect, when the discharge control switch 113 is composed of an N-channel FET, a mechanism in which the source is connected to the negative terminal ship and the anode is connected to the anode of the domain battery m can be used, and the gate is opposite to the first one. The structure of the polar signal. Further, in this case, the current detecting resistor 112 is connected between the positive terminal 1〇1 and the negative battery of the rechargeable battery (1). Since the hybrid structure itself has been secretive, M Lin will be detailed. Referring to Fig. 3, the 'man-person' is made up of the ship's structure of the delayed home road 25 with the dragon detection function shown in the third. The illustrated delay circuit 25 with the detection of Wei has a monitoring effect? The input/output of the discharge control circuit (1) constituted by the channel hangar _ turns on the differential circuit 251 of the monitoring circuit of the electric galvanic cake. 13 1328325 That is, the differential circuit 251 is connected between the source and the drain of the P-channel FET, monitors the voltage drop generated by the current flowing through the on-resistance of the FET, and converts the monitored voltage drop into a current. , output to the delay section. The delay unit shown in Fig. 3 has an analog delay characteristic as shown in Fig. 2 and is referred to as an analog delay unit. Here, the voltages of the source and drain of the P-channel FET are Vcc and cS, respectively. The analog delay portion of the figure has a current source 252 that is current-controlled by a current from the differential circuit 251. One end of the capacitor 253 is connected in series with the current source 252, and the other end of the capacitor 253 is grounded. Further, a common connection point of the current source 252 and the capacitor 253 is connected to the input port of one end of the comparison circuit 254, and a voltage source 255 for supplying a predetermined voltage is connected to the input port of the other end of the comparison circuit 254. In this configuration, the capacitor 253 is charged by the current from the current source 252, and for this reason, the voltage of the input 一端 at one end of the comparison circuit 254 rises with the current of the current source 252. Here, when the current flowing through the discharge control switch 113 abruptly increases, the current of the differential circuit 251 also sharply increases, and as a result, the current supplied from the current source 252 to the capacitor 253 also sharply increases. Therefore, the voltage of the capacitor 3 rises rapidly, exceeds the voltage of the voltage source 255 in a short time, and outputs an output signal from the comparison circuit (9) in a short time. The right structure is based on the output of the comparison circuit 254 and the output k of the overcurrent detecting unit, so that the discharge control 113 is in the off state, then the discharge control switch 113 can be configured to be short-timed. The state is switched to the off state, and the delay circuit has a short delay time. On the other hand, when the current flowing through the discharge control circuit 113 is slowly increased, the current of the difference 13-28325 is gradually increased, and the current supplied from the current source 252 to the capacitor (5) is also increased (four). Therefore, since the voltage of the capacitor 253 also rises slowly, the voltage f set by the voltage source 255 is required to be longer (four). As a result, the characteristics of the current j and the delay time din as shown in Fig. 2 can be obtained.
請參照第4圖’所示的是第3圖給出的電流源252的具體的 結構例子。如第4圖所示，電流源252具有，供給與來自差動電 路251的輸出相應的電流的電流源電路，由pN^極管了小把、 Tr3所構成的第1電流鏡像線路’及由册^三極管制、π所構 成的第2電流反射鏡電路。三極管丁rl、招、及M的發射極分 別連接有電阻，通職電阻，可施加電壓Vee、cs及*。Referring to Fig. 4, a specific structural example of the current source 252 given in Fig. 3 is shown. As shown in Fig. 4, the current source 252 has a current source circuit for supplying a current corresponding to the output from the differential circuit 251, a first current mirror line ' composed of a pN^ pole, and a Tr3. The second current mirror circuit consisting of three poles and π. The emitters of the triodes dl, s, and M are connected with resistors, and the resistors are applied to apply voltages Vee, cs, and *.
當與來自差動電路251的輪出信號相應的電流從電流源電路 供給第i t歧職祕時，正崎流過三極管M㈣流的電 流就流過三極管Tr2、Tr3。另外，由於三極管M、Tr3連接在第 2電流反射鏡電路（Tr4、Tr5)上，在該三極管把、M中流過 互成比例的電流。結果’連接在三極管Tr3和仿的共同連接點的 電容器253就以對應於差動電路251的輸出信號的電流予以充電。 請參照第5圖來說明本發明的另一實施例的電池單元i丄b。圖 π的電池單元lib的過電流檢測電路應具有，有著和第丨圖同 _成的過電流檢測部20a，及連接在該過電流檢測部施、同時 退連接在電流檢測電阻112的兩端的帶電壓檢測功能的延遲電路 25a。這樣’在圖示的帶電壓檢測功能的延遲電路β上除了施加 電流檢測電阻U2的兩端電壓以外，還具有與第！圖所示的電池 15 1328325 • 單元Ua同樣的結構。第5圖所示的帶電壓檢測功能的延遲電路 • 25a具有與第3圖所示的電路25同樣的構成，也可以將差動電路 251的兩個輸入埠連接到電流檢測電阻η〗的兩端。 上述的實施例就主要以鋰離子電池作為充電電池使用時進行 了說明，然而本發明對此並沒有任何限定，也可以應用於鎳鎘電 池、鎳汞電池等。 採用本發明，根據FET或電流檢測電阻的兩端的電壓降，通 螓過使延遲時間模擬地可變，能夠防止因極短的時間内產生的急劇 的電流變化而使大電流流過FET，與數字式地使延遲時間變化時 相比，具有以高速檢測過電流，可防止FET的損壞的優點。 . 所述者，僅為本發明其中的較佳實施例而已，並非用來限定 本發明的實施範圍；即凡依本發明申請專利範圍所作的均等變化 與修飾’皆為本發明專利範圍所涵蓋。 _ 【圖式簡單說明】 第1圖是用於說明本發明的一個實施例的電池單元的構成的 方塊圖。 第2圖疋表7F帶有含在第1圖所示的電池單元的電壓 能的延遲電路的特性圖。 、 第3圖是具體地表示帛1圖所示的帶電廢檢測功能的延 路的一部分結構的電路圖。 第4圖疋詳細說明第3圖所示的電路的-部分的電路圖。 16 13-28325 第5圖是表示本發明的另一實施例的電池單元的構成的方塊 圖。 第6圖是說明現有的電池單元的構成的方塊圖。 第7圖是說明第6圖所示的過電流檢測電路的特性圖。 【圖式符號說明】 10 過電流檢測電路 10a 過電流檢測電路 10b 過電流檢測電路 11 電池單元 11a 電池單元 lib 電池單元 20 過電流檢測部 20a 過電流檢測電路 21 延遲電路 25 延遲電路 25a 延遲電路 101 正極端子 102 負極端子 111 充電電池 112 電流檢測電阻 113 放電控制開關When a current corresponding to the rounding signal from the differential circuit 251 is supplied from the current source circuit to the ith portion, the current flowing through the transistor M (four) flows through the transistors Tr2 and Tr3. Further, since the transistors M and Tr3 are connected to the second current mirror circuits (Tr4 and Tr5), a current proportional to each other flows through the transistors and M. As a result, the capacitor 253 connected to the common junction point of the transistor Tr3 and the dummy is charged with a current corresponding to the output signal of the differential circuit 251. Referring to Fig. 5, a battery unit i丄b according to another embodiment of the present invention will be described. The overcurrent detecting circuit of the battery unit lib of Fig. π should have an overcurrent detecting unit 20a which is the same as the first drawing, and is connected to the overcurrent detecting unit and simultaneously connected to both ends of the current detecting resistor 112. Delay circuit 25a with voltage detection function. Thus, in addition to the voltage across the current detecting resistor U2, the delay circuit β with a voltage detecting function shown in the figure has the same! Battery shown in the figure 15 1328325 • Unit Ua has the same structure. The delay circuit 25a with voltage detection function shown in Fig. 5 has the same configuration as the circuit 25 shown in Fig. 3, and the two input ports of the differential circuit 251 may be connected to two of the current detecting resistors η. end. The above embodiment has been described mainly when a lithium ion battery is used as a rechargeable battery. However, the present invention is not limited thereto, and can be applied to a nickel-cadmium battery, a nickel-mercury battery, or the like. According to the present invention, the delay time is analogously variable by the voltage drop across the FET or the current detecting resistor, so that a large current can be prevented from flowing through the FET due to a sharp current change occurring in a very short period of time. Digitally, when the delay time is changed, there is an advantage that the overcurrent is detected at a high speed to prevent damage of the FET. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; that is, the equivalent variations and modifications made by the scope of the present invention are covered by the scope of the present invention. . BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram for explaining the configuration of a battery unit according to an embodiment of the present invention. Fig. 2 is a characteristic diagram of a delay circuit with voltage energy of the battery cell shown in Fig. 1. Fig. 3 is a circuit diagram showing a part of the configuration of the extension of the charged waste detecting function shown in Fig. 1 . Fig. 4 is a circuit diagram showing in detail a portion of the circuit shown in Fig. 3. 16 13-28325 Fig. 5 is a block diagram showing the configuration of a battery unit according to another embodiment of the present invention. Fig. 6 is a block diagram showing the configuration of a conventional battery unit. Fig. 7 is a characteristic diagram for explaining the overcurrent detecting circuit shown in Fig. 6. [Description of Symbols] 10 Overcurrent Detection Circuit 10a Overcurrent Detection Circuit 10b Overcurrent Detection Circuit 11 Battery Unit 11a Battery Unit lib Battery Unit 20 Over Current Detection Unit 20a Over Current Detection Circuit 21 Delay Circuit 25 Delay Circuit 25a Delay Circuit 101 Positive terminal 102 negative terminal 111 rechargeable battery 112 current detecting resistor 113 discharge control switch
17 1328325 251 差動電路 252 電流源 253 電容 254 比較電路 255 電壓源 搴 _ 1817 1328325 251 Differential Circuit 252 Current Source 253 Capacitor 254 Compare Circuit 255 Voltage Source 搴 _ 18