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TWI303096B - - Google Patents

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Publication number
TWI303096B
TWI303096B TW095106813A TW95106813A TWI303096B TW I303096 B TWI303096 B TW I303096B TW 095106813 A TW095106813 A TW 095106813A TW 95106813 A TW95106813 A TW 95106813A TW I303096 B TWI303096 B TW I303096B
Authority
TW
Taiwan
Prior art keywords
semiconductor
substrate
wafer
wiring
connection
Prior art date
Application number
TW095106813A
Other languages
English (en)
Other versions
TW200636972A (en
Inventor
Masaki Hatano
Yuji Takaoka
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW200636972A publication Critical patent/TW200636972A/zh
Application granted granted Critical
Publication of TWI303096B publication Critical patent/TWI303096B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04C—STRUCTURAL ELEMENTS; BUILDING MATERIALS
    • E04C2/00—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels
    • E04C2/02—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials
    • E04C2/26—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials composed of materials covered by two or more of groups E04C2/04, E04C2/08, E04C2/10 or of materials covered by one of these groups with a material not specified in one of the groups
    • E04C2/284—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials composed of materials covered by two or more of groups E04C2/04, E04C2/08, E04C2/10 or of materials covered by one of these groups with a material not specified in one of the groups at least one of the materials being insulating
    • E04C2/292—Building elements of relatively thin form for the construction of parts of buildings, e.g. sheet materials, slabs, or panels characterised by specified materials composed of materials covered by two or more of groups E04C2/04, E04C2/08, E04C2/10 or of materials covered by one of these groups with a material not specified in one of the groups at least one of the materials being insulating composed of insulating material and sheet metal
    • E—FIXED CONSTRUCTIONS
    • E04—BUILDING
    • E04B—GENERAL BUILDING CONSTRUCTIONS; WALLS, e.g. PARTITIONS; ROOFS; FLOORS; CEILINGS; INSULATION OR OTHER PROTECTION OF BUILDINGS
    • E04B1/00—Constructions in general; Structures which are not restricted either to walls, e.g. partitions, or floors or ceilings or roofs
    • E04B1/38—Connections for building structures in general
    • E04B1/61—Connections for building structures in general of slab-shaped building elements with each other
    • E04B1/6108—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together
    • E04B1/612—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces
    • E04B1/6125—Connections for building structures in general of slab-shaped building elements with each other the frontal surfaces of the slabs connected together by means between frontal surfaces with protrusions on the one frontal surface co-operating with recesses in the other frontal surface
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

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Description

Ϊ303096 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置及其製造方法，其係裝載 數個半導體晶片構成一個封裝形態之所謂系統封裝，詳而 言之係使用半導體基板進行數個半導體晶片間之電性連接 之構造者。 【先前技術】
近年來，隨著電子機器之多功能化，其使用之半導體晶 片亦被要求多功能化。然而，一旦以在一個晶片上形成大 規模之功月匕系統之系統單晶片（S〇c : System on Chip)來實 現多功能化，則有需要大規模之晶片開發、開發期間長、 成本高等之間題。因此，提案系統級封裳（Sip : 沁
Package)，其係將數個半導體晶片裝載於介質基板上，將其 作為一個封裝零件。 例如於專利文獻i揭不：使用矽介層基板使數個晶片倒裝 晶片連接而平置裝載之構造之Sip。 (專利文獻1)日本特開2004-79745號公報。 關於此參照圖16進行說明’則矽介層基板53係具有表層 布線層及貫通通道部56。表層布線層5〇具有：連接數個 晶片間用之細微布線(例如次微米序(submicr〇n _…之線 間之布線）、晶片連接用之狹間距（例如Μ㈣間距以下）之 墊三貫通通道部56係於貫㈣介層基板此厚度方向形成 之貫通通道之内壁面，介士 、 土面；丨由絕緣膜例如以電鍍法充填其貫 通通道之方式形成之導辦立 风t导體。卩，擔負將轉換（再配置）為連接有 107583.doc 1303096 機介層基板57用之較粗之間距（例如100 μηι^ι距以上）之塾 49拉出至矽介層基板53下面（晶片裝載面之相反面）之作用。 於矽介層基板53之表層布線層50，介由焊錫凸塊51、51 將數個半導體晶片2a、2b倒裝晶片連接裝載於矽介層基板 53上’半導體晶片2a、2b與矽介層基板53之間充增有底部 填充樹脂材54。 石夕介層基板53係介由拉出至下面側之墊49、焊錫凸塊58 及有機介層基板57之平台59,電性連接有機介層基板57而 裝載，矽介層基板53與有機介層基板57之間充填有底部填 充樹脂材5 5。 另外，於專利文獻2揭示使用不具有貫通通道部之矽介層 基板之SiP。此係如圖17所示，數個半導體晶片62a、6几係 介由焊錫凸塊64連接於矽介層基板61，矽介層基板61係介 由焊錫凸塊65，將與半導體晶片62a、62b之裝載面相同之 面側連接有機介層基板63。 (專利文獻2)曰本特開平8_25〇653號公報。 (發明所欲解決之問題） 於上述專利文獻丨，貫通矽介層基板53正反面之貫通通道 之幵y成及充填其貫通通道之導體56之形成為必要，需要形 成八貝通通道用之矽蝕刻或以電鍍析出貫通通道内之導體 56之成本或時間’作為其結果，有半導體裝置整體之製造 成本提高之問題。 另外於石夕介層基板53 ’除配合半導體晶片2a、2b之設 計規則之細微設計規則之日日日片日日日連接布線層50之外，將符 107583.doc 1303096 . 合有機介層基板57之設計規則之較粗間距之墊49拉出至 .:側，石夕介層基板53之平面方向大小易變大，&亦為成: 南之主要原因。 另外，於專利文獻2，在矽介層基板61中與半導體晶片 • 62a、62b裝載面相同之面侧，拉出與有機介層基板^接 . 用之墊，半導體晶片62a、62b係經過形成於矽介層基板Ο 之布線後，連接於有機介層基板63之構成。因此，半導體 • 晶片62&、6孔與有機介層基板63間之布線長度容易變長， 容易導致半導體晶片62a、62b與有機介層基板63間之 傳送延遲。 " 再者，於矽介層基板61，除連接半導體晶片6h、間 之布線外，亦形成將半導體晶片.、心連接於外部（該情 況為有機介層基板63)用之布線，故藉由其拉出外部用之布 線，晶；^間連接布線之迴繞布置之自由度變小，連接晶片 間之布線長度容度變長，亦容易導致半導體晶片仏、曰曰㈣ φ 間之信號傳送延遲。 本發明係有鑑於上述之問題，作為其目的係提供一種半 導體裝，置及其製造方法，其價格便宜且可抑制信號傳送之 延遲。 【發明内容】 本發明為解決前述問題，採用以下之構成。 、亦即’本發用之半導體裝置具傷··數個半導體晶片、半 導體基板，其在相同面側形成電性連接該等數個半導體晶 片用之晶片間連接布線，與連接於該晶片間連接布線之數 107583.doc 1303096 片連接用墊、布線基板，其具有以比晶片連接用墊大 之間距配置之數個平台，·數個半導體晶片係介由第1連接端 子將八主面連接於晶片連接用墊，裝載於半導體基板，於 半導體晶片之主面，在不朝向半導體基板相合之部份形成 外部連接轉，該外部連接用墊㈣由第2連接端子連接布 線基板之平台。 ，另外，本發明之半導體裝置係具備：數個半導體晶片、 半導體基板，其在相同面侧形成與電性連接該等數個半導 體晶片間用之晶片間連接布線，與連接該晶片間連接布線 之數個晶片連接用墊；數個半導體晶片係介由連接端子將 其主面連接於晶片接連用墊，裝载於半導體基板，於半導 "片之主面在不朝向半導體基板相合之部份，形成以 比晶片連接用墊大之間距配置之數個外部連接用墊。 另外，本發明之半導體裝置之製造方法係具有以下步 驟.於半導體基板，在相同面侧形成晶片間連接布線及與 該晶片間連接布線連接之數個晶片連接用塾之步驟、於半 導體晶片之主面中不朝向半導體基板相合之部份，形成以 較晶片連接用墊大之間距配置之數個外部連接用墊之步 驟、於布線基板形成與外部連接用墊等間距之平台之步 驟、介由第1連接端子’使數個半導體晶片之主面連接於^ 導體基板之晶片連接詩’將數個半導體晶片裝载於半導 體基板之步驟、介由第2連接端子連接半導體晶片之外部連 接用墊與布線基板之平台之步驟。 上述數個半導體晶片係介由 形成於半導體基板之晶片 間 107583.doc 1303096 連接布線相互電性連接；再者，半導體晶片係對著布線基 板不經由半導體基板而直接連接。 上述半導體基板僅具有擔負連接數個半導體晶片間之功 能。於上述布線基板中，在與半導體晶片連接之平台之形 成面之相反面側，形成符合所謂母板之布線板之設計規則 之平台，布線基板係作為介層，擔負連接半導體晶片與其 母板之間之功能。 形成於半導體晶片主面之細微且窄間距之電極墊，係作 為配合母板之設計規則之大小及間距之外部連接用墊，而 拉出（再配置）。 於半導體基板，無需形成與布線基板連接用之符合其布 線基板之設計規則之大小及間距之墊，亦即，僅於半導體 基板’形成與半導體晶片連接用之大小及間距更細微之晶 片連接用墊即可，故可謀求半導體基板之平面方向大小之 小型化，謀求降低半導體基板所需之成本。 半導體晶片係無需經由半導體基板，呈介由從半導體晶 片直接拉出之外部連接用墊連接外部（布線基板）之構成，故 與經由半導體基板將半導體晶片連接於布線基板之上述專 利文獻2相比，可縮短半導體晶片與布線基板間之布線長 度，降低半導體晶片與布線基板間之信號傳送延遲。 再者，僅在半導體基板形成晶片間連接布線，不形成連 接半導體晶片與布線基板用之布線，故不受連接半導體晶 片與布線基板之布線之阻礙，可將晶片間連接布線集中於 某區域形成於半導體基板，可縮短該晶片間連接布線之布 107583.doc 1303096 線長度’藉此可降低半導體晶片間之信號傳送延遲。 另外’右將半導體基板配置在形成於布線基板中凹處 内，則可抑制半導體裝置整體厚度之增加。再者，若供應 樹脂材於其凹處内，將半導體基板固定於布線基板，則介 由上述第1連接端子、第2連接端子，可分散施加於接合部 之應力，提高其接合部之接合可靠性。 另外，接合半導體晶片與半導體基板前，若預先將半導 體基板配置在形成於布線基板中之凹處内，則既存之實裝 裝置可採用例如：使用真空吸著具將半導體晶片逐一拾 取、裝載於半導體基板之與既存之裝載方法相同之方法， 不易導致成本高或實裝效率降低。 根據本發明，半導體基板係僅具有電性連接數個半導體 晶片間之功能，不具有為使半導體晶片之電極墊與外部連 接而擴大拉出用之功能。因此，不需形成貫通半導體基板 正反面之貝通孔及充填其貫通孔之導體，可謀求削減其等 之加工成本及所需時間。其結果，可降低半導體裝置整體 所需成本。再者，半導體晶片係不經由半導體基板，介由 從半導體晶片直接拉出之外部連接用墊與外部（布線基板） 連接之構成，故可縮短半導體晶片與布線基板間之布線長 度，降低半導體晶片與布線基板間之信號傳送延遲。再者， 僅於半導體基板形成晶片間連接布線，不形成連接半導體 晶片與布線基板用之布線，故不被連接半導體晶片與布線 基板用之布線阻礙，可將晶片間連接布線集中於某區域形 成於半導體基板，而可縮短該晶片fa1連接布、線之布線長 107583.doc -10- 1303096 度，藉此可降低半導體晶片間之信號傳送延遲。 【實施方式】 以下，參照圖面詳細說明有關適用本發明之具體實施型 態。又，本發明並不限定於以下之實施型態，依據本發明 之技術性思想可做各種之變形。 [第1實施型態] 圖1係表示有關本發明之第丨實型態之半導體裝置丨之部 份剖面立體圖，圖2係表示其半導體裝置！之剖面圖。 半導體裝置1具備：半導體基板3、半導體晶片2a、2b， 其裝載於該半導體基板3、布線基板7，其與半導體晶片2 a、 2b連接。 於半導體基板3，於相同面側形成電性連接半導體晶片 2a、2b用之晶片間連接布線4，與連接於該晶片間連接布線 4之數個晶片連接用墊5。 半導體晶片2a、2b係介由第丨連接端子8、9,將其主面（積 體電路形成面）連接於半導體基板3之晶片連接用塾5。藉 此’半導體晶片2a、2b係介由形成於半導體基板3之晶片間 連接布線4相互電性連接。於該半導體晶片〜、以與半導體 土板3之接合部充填底部填充樹脂材， 二半導體晶片一主面中，在不朝向半導體基;:3相 :^形成數個外部連制墊13。於布線基板㈣成數個 比:導^等外部連接㈣13間之間距及平台6間之間距係 8 9門“反3之晶片連接用墊5間之間距(第1連接端子 9間之_大。外部連制㈣與平⑽、介由第2連接 107583.doc 1303096 端子12連接，藉此電性連接半導體晶片2a、^與布線基板 7。於該半導體晶片2a、2b與布線基板7之接合部充填底部 填充樹脂材15，保護其接合部。 其次，說明有關其半導體裝置i之製造方法之一例。 半導體基板3係例如為矽基板，如圖3所示，於其一面侧， 形成晶片間連接布線4及連接其之數個晶片連接用墊5。該 等晶片間連接布線4及晶片連接用墊5係使用一般之半導體 晶圓製程之技術及設備形成。晶片間連接布線4係例如為多 層，於各層之間介在絕緣層。作為晶片間連接布線4及晶片 連接用墊5之材料，例舉如銅、鋁等，作為絕緣層之材料係 例如半導體基板3為矽之情況，可用氧化矽、氮化矽形成， 或使用如聚醯亞胺之樹脂材料亦可。又，晶片間連接布線斗 亦可為單層。晶片間連接布線4之線間（最小線寬）係次微米 (〇·1 μπι〜1 μηι)程度，晶片連接用墊5間之間距係數^^〜的 μιη程度。如此之設計規則之布線及墊可容易以一般之半導 體製程形成矽基板之半導體基板3。 又，半導體基板3不限於矽基板，亦可為鍺、化合物半導 體等之半導體基板。於本實施型態，由於以矽晶片作為裝 載於半導體基板3之半導體晶片2a、2b，故為使其與線膨脹 係數一致，使用矽基板做為半導體基板3。半導體基板3與 裝載其之半導體晶片2a、2b之線膨脹係數若相同或相近， 則二者接受溫度圈時，可抑制於二者之接合部作用之廉 力，提咼接合可靠性。因此，半導體基板3與半導體晶片 2b使用相同材料或線膨脹係數相近之材料為佳。 107583.doc -12- 1303096 :次如圖4所示，於晶片連接用墊5之上形成第旧接端子 曰。第1連接端子9例如以電鐘法或印刷法等形成之半球狀之 烊錫凸塊。作為請接端子9,亦可使用焊錫以外之金屬 或合金’再者其形狀亦可為柱狀。 形成第1連接端子9後，將半導體基板3之背面（晶片間連 接布線4、晶片連接用墊5及第味接端子9之形成:之城 Z吏用背部研磨機研削背面’進行薄型化。再者，使用切 割鋸或雷射等方法，沿著厚度方向切斷’進行個片化。 其-人，對上述半導體基板3，如圖5所示介由第丨連接端 子 9接δ數個（於本實施型態係例如二個）半導體晶片 2a、2b。 3Β ,各半導體晶片2a、2b中，於主面（積體電路形成面）側分別 形成布線10及連接於該布線10之數個墊丨丨，半導體晶片 2a、2b之電極墊（未圖示）係介由布線1〇再配置於更加擴大間 距之墊11。該等布線10及墊u係以與形成於半導體基板3之 晶片間連接布線4及晶片連接用墊5相同之步驟形成，半導 體晶片2a、2b側之墊U與半導體基板3側之墊5分別以相同 之間距配置相同數量。 於半導體晶片2a、2b之墊丨丨上，形成與形成於上述半導 體基板3之晶片連接用墊5上之第丨連接端子9相同之第1連 接端子（例如焊錫&塊）8,以將該等連接端子8、9彼此互相 相合之狀態，用將該等連接端子8、9加熱熔融之方式接合 連接端子8、9彼此，藉此半導體晶片2a、2b之布線1〇與半 導體基板3之晶片間連接布線4電性連接。因此，通過半導 107583.doc -13- 1303096 . 體基板3之晶片間連接布線4,二個半導體晶片2a、2b間電 性連接。 於半導體基板3與各半導體晶片仏、孔之間，介由第工連 接端子8、9以包覆接合部份之方式充填底部填充樹脂材 14 ’保護其接合部份遠離應力或垃圾、水》等。底部填充 樹月曰材14係例如將液狀或膏狀之熱硬化性樹脂，以將半導 體基板3置於下，半導體晶片2a、2b置於上之狀態，供應於 φ 半導體基板3與各半導體晶片2a、2b之間後H熱硬化形 成。 另外，於各半導體晶片2a、2b，除於與半導體基板3連接 用之塾11以外’亦在與該墊丨1相同之面側形成數個外部連 接用墊13。外部連接用墊13係與上述墊u同時製入，與布 線1〇連接。外部連接用墊13係於半導體晶片2a、2b中不朝 向半導體基板3相合之部份，具體而言係靠近半導體晶片 a 2b之外緣部份，以比墊丨丨大之大小及間距（例如1 〇〇 修 以上之間距）配置。該外部連接用墊13係介由如圖6所示之 布線基板7與第2連接端子12而接合。 布線基板7係例如玻璃環氧布線基板等之有機布線機基 板於布線基板7之另一邊表面，形成數個平台6。平台6 二…形成於半導體晶片2a、2b之外部連接用墊13相同之 間距，配置相同數量。布線基板7中，於其平台形成面之相 反面，以比平A & 4* ^ 大之間距形成數個平台17。平台6與平台 係"由充填形成於布線基板中之通路之導電體1 8及布線 1 9電〖生連接。平台丨7係將平台6之間距更加擴大而再配置之 107583.doc -14- 1303096 平口平口 6 17、導電體18、布線19係例如鋼等金屬材料 組成。布線19為多層構造，各層間介在絕緣層。 布線19之線間或平台6、〗7夕 X卞口 6 17之間距係採用—般之有機布線 基板之設計規則。例如，平台6、17之間距為__上。 又，作為布線基板7，其他亦可使用氧化料之㈣布線基 板0 。於布線基板7之中央部份，將平面尺寸比半導體基板仏 平面尺寸大之凹處16貫通布線基板7之厚度方向作為貫通 孔而形成。該凹處16可用例如工作機械、雷射、姓刻等方 法形成。 於布線基板7之平台6上，例如形成焊錫凸塊作為第2連接 端子12。以例如使用錫球裝載機之轉印法等，於平台6上裝 載錫球後’藉由迴焊形成半球狀n亦可以電°鑛或^ 刷法等形成柱狀之金屬凸塊作為第2連接端子Η。 將半導體基板3位於布線基板7之凹處16内，且在第2連接 知子12與半導體晶片2a、以之外部連接用墊13相合之狀 心藉由加熱熔融第2連接端子12，介由第2連接端子以接 合半導體晶片2a、2b之外部連接用墊13與布線基板7之平台 6藉此，可獲得如圖1、2所示之半導體裝置i。 一個半導體晶片2a、2b係介由形成於半導體基板3之晶片 ，連接布線4相互電性連接，再者，半導體晶片對 著布線基板7不經由半導體基板3而直接連接。 布線基板7中，在與半導體晶片2a、2b接合之面之相反面 側，形成符合所謂母板之布線板之設計規則之平台17，布 107583.doc 1303096 線基板7係作為介層，擔負連接半導體晶片2a、2b與其母板 之間之功月b 〇半導體基板3僅具有擔負連接二個半導體晶片 2a、2b間之功能。 θθ 形成於半V體晶片2a、2b之主面之細微且窄間距之電極 墊係介由布線10,拉出（再配置）作為符合母板之設計規則之 大小及間距之墊13。 於布線基板7之平台17形成例如錫球、金屬塾等之連接端 子’"由其連接端子連接形成於母板之平台及布線。於母 板’除該半導體裝置外亦裝載其他多種零件（半導體裝 置、電阻、電容器、連接器等）’其等零件與半導體裝置丄 通過形成於母板之布線電性連接。 又，作為半導體裝置之構成，亦可為如圖15所示之無布 線基板7之構成。亦即，半導體晶片2a、孔之外部連接用墊 13介由錫球或金屬凸塊等之連接端子直接裝載於母板亦 可J而，形成於半導體晶片2a、2b之外部連接用墊13由 於党到半導體晶片大小之限制，故無法擴大大小及間距至 忒耘度，故有可旎無法與設計規則較粗略之母板相對應。 因此，將半導體晶片2a、2b之外部連接用墊13介由布線基 板7,再配置於更加擴大之間距17之構成，可避免於母板側 進行需要額外成本之細微加工，故佳。 又，不限於上述製造例，如圖7所示，將第丨連接端子8 及第2連接端子12全部分別形成於半導體晶片〜、沘之墊 11、13上，且亦可介由第1連接端子8接合半導體晶片、 2b與半導體基板3(圖8)，及介由第2連接端子12進行半導體 107583.doc κ 13〇3〇96 晶片2a、2b與布線基板7之接合。 如以上所述，於本實施型態之半導體裝置1，半導體基板 3僅具有電性連接數個半導體晶片2a、2b之功能，不具有為 了使半導體晶片2a、2b之電極墊與外部連接而擴大拉出用 之功能。因此，如圖16所示之以往之例，不需形成貫通半 導體基板3正反面之貫通孔及充填其貫通孔之導體，可謀求 削減其等之加工成本及所需時間。其結果，可降低半導體 裝置1整體之成本。 另外’不需為與布線基板7連接用，而於半導體基板3形 成符合其布線基板7之設計規則、大小及間距更加擴大之 塾’亦即，僅於半導體基板3形成與半導體晶片2a、2b連接 用之大小及間距更細微之墊即可，故可謀求半導體基板3 之平面方向之大小之小型化。其將降低半導體基板3所需成 本0 再者，半導體晶片2a、2b係不需經由形成於半導體基板3 之布線，呈介由直接從半導體晶片2a、孔拉出之外部連接 用墊13，連接布線基板7之構成，故如圖17所示，比起經由 半導體基板61將半導體晶片62a、6几連接於布線基板〇之 以往之例，可細短半導體晶片2a、2b與布線基板7間之布線 長度，可降低半導體晶片2a、2b與布線基板7間之信號傳送 延遲。 再者，於如上述之本實施型態之半導體基板3，僅形成晶 片間連接布線4’未形錢接半導體^2a、2b與布線基板 7用之布線’故不受連接半導體晶片2a、以與布線基板了用 107583.doc 1303096 • 之布線之阻礙，可集中於某區域形成晶片間連接布線4，可 縮短該晶片間連接布線4之布線長度，藉此亦可降低半導體 晶片2a、2b間之信號傳送延遲。 [第2實施型態] 其次，圖9係表示有關本發明之第2實施型態之半導體裝 置21之部份剖面立體圖，圖1〇係表示其半導體裝置η之部 面圖又，與上述第1貫施型態相同構成之部份賦與相同之 _ 符號，省略其詳細說明。 有關於本實施型態之半導體裝置21係具備：半導體基板 3、數個半導體晶片2a、孔，其裝載於該半導體基板3、布 線基板27，其與半導體晶片2a、2b連接。 於半導體基板3，在同一面側形成電性連接半導體晶片 2a、2b間用之晶片連接布線4,與連接於該晶片間連接布線 4之數個晶片連接用墊5。 半導體晶片2a、2b係介由第丨連接端子8、9，將其主面（積 • 體電路形成面）連接於半導體基板3之晶片ϋ接用墊5。藉 此’半導體晶片2a、2b介由形成於半導體基板3之晶片間^ 接布線4互相電性連接。 半導體晶片2a、213之主面中，在不與半導體基板3相合之 卩伤幵7成數個外部連接用墊13。於布線基板27形成數個平 •口 6。其等外部連接用塾13間之間距及平台6間之間距係比 半導體基板3之晶片連接用墊5間之間距(第!連接端子$ ” 1之間距大。外部連接用塾13與平台6係介由第2連接端子 連接猎此，電性連接半導體晶片2m與布線基板 107583.doc -18- 1303096 • 於半導體晶片2a、2b與半導體基板3之間，及半導體晶片 • 2a、2b與布線基板27之間充填底部填充樹脂材24，保護半 導體晶片2a、2b與半導體基板3之接合部，及半導體晶片 2a、2b與布線基板27之接合部。 使半導體基板3從凹處26露出，配置於其凹處26内，該凹 處係將晶片連接用塾5及形成此之第1連接端子9形成於布 線基板27者。凹處26形成作為有底之凹穴於凹處％之内壁 • 面，與半導體基板3之底面及側面間充填樹脂材，介由該樹 脂材半導體基板3固定於凹處26。其樹脂材亦可係將上述底 部填充樹脂材24流入半導體晶片2a、2b與半導體基板3之 間，及半導體晶片2a、2b與布線基板27之間時，兼供應至 凹處26内之方式，亦可於填充底部填充樹脂材以之前，將 凹處2 6供應用之樹脂材另外供應至凹處2 $。 如此於本實施型態，半導體基板3係呈埋入布線基板27 内與布線基板27—體化之構造。因此，與半導體晶片仏、 • 几及半導體基板3，僅以介由第2連接端子12接合之接合部 支撐布線基板7之構造之上述第〗實施型態相比，可分散施 加於介由第2連接端子12連接之接合部之應力（特別係，藉 由線膨脹係數大之有機布線基板27接受溫度圈形成之收縮 所產生之應力），可提高其接合部之連接可靠性。再者，藉 由將半導體基板3支撐於布線基板27之凹處26内，在介由2 微大小之第丨連接端子8、9連接之半導體晶片^、孔與半導 體基板3之接合部，亦可避免過多之應力作用，提高其接合 部之接合可靠性。其結果，半導體晶片以、以、半導體i 107583.doc -19- 1303096 板3及布線基板27互相之接合可靠性可比第ι實施型態高。 此外所獲得之效果與上述第！實施型態相同。 參照圖11、圖12說明有關該第2實施型態之半導體裝置21 之製造例。 如圖11所示，於布線基板27之中央部份，平面尺寸比半 導體基板3之平面尺寸大-些之凹處26，形成作為有底之凹 穴。該凹處26係可例如以工作機械、雷射、姓刻等方法形 成。 乂於其凹處26之底面及内壁面供應液狀或f狀之樹脂材 後，如圖12所示將半導體基板3配置於凹處^内，例如使樹 脂材熱硬化，將半導體基板3對著布線基板27固定。或者， 先將半導體基板3配置於凹處26内後，亦可於半導體基板3 與凹處2 6之縫隙間供應樹脂材使其硬化。 在八狀L，半導體基板3之晶片連接用墊5係位於較布線 基板27中平台6之形成面稍微上方’介由第丨連接端子8、9 於其晶片連接用塾5接合半導體晶#2a、2b。另外，於此同 時介由第2連接端子12，接合半導體晶片2&、2b之外部連接 用塾13與布線基板27之平台6。又，若適當設、第2 連接端子8、9、12之高度，則半導體基板3之晶片連接用墊 久〃、布線基板27中平台6之形成面對齊或稍微進入凹處％ 亦可。 、=此’接合半導體晶片2a、2b與半導體基板3前，若先將 半¥體基板3埋入布線基板27使其固定，則既存之實裝裝 置可例如使用真空吸著具逐一拾取半導體晶片&、冗裝 107583.doc -20- 1303096 載半導體基板3。 先接合半導體晶片2a、2b與半導體基板3之後，— 接。體對著布線基板27接合，則於數個半導體晶片2匕、 側進行真空吸著之際，為防止由晶片間之間隙之氣漏二孔 之吸著不良或於吸著狀離 、' ^成 次考狀L之偏斜，有必需統一數個 晶片2a、2b間厚度之問題。 導體 如上述，若先將半導體基板3埋入布線基板27,則可 其半導體基板3,使用既存之真空吸著具逐—拾取半導^ 片2a、2b，使用既存之裝載方式裝載。 曰曰 [第3實施型態] 其次，圖13係表示有關本發明之第3實施型態之半導體裝 置31。又’與上述第！、第2實施型態相同構成之部份賦與 相同之符號，省略其詳細之說明。 ^ 有關本實施型態之半導體纟置31係具備：I導體基 數個半導體晶片2a、2b’其裝載該半導體基板3、布線基板 37 ’其連接半導體晶片2a、2b。 於半導體基板3，在同一面側形成電性連接半導體晶片 2a、2b間用之晶片間連接布線4，與連接於該晶片間連接布 線4之數個晶片連接用墊5。 半導體晶片2a、2b係介由第1連接端子8、9，將其主面（積 體電路形成面）連接於半導體基板3之晶片連接用墊5。藉 此，半導體晶片2a、2b介由形成於半導體基板3之晶片間連 接布線4互相電性連接。 半導體晶片2a、2b之主面中，於不朝向半導體基板3相合 107583.doc -21 - 1303096 之邛饧形成數個外部連接用墊13。於布線基板37形成數個 平〇 6。其等外部連接用墊13間之間距，及平台6間之間距 係比半導體基板3之晶片連接用墊5間之間距（第丨連接端子 8、9間之間距）大。外部連接用墊13與平台6係介由第之連接 二子38連接’藉此電性連接半導體晶片仏、㉛與布線基板 半導體晶片2a、2b與半導體基板3之間，及半導體晶片 、2b與布線基板37之間充填有底部填充樹脂材36，保護 半導體曰曰片2a、2b與半導體基板3之接合部，及半導體晶片 2a、2b與布線基板37之接合部。 於本貫施型態，半導體基板3係不配置於布線基板37内， 裝載布線基板37中平台6之形成面上。因此，如上述第j、 弟只知型悲’無需於布線基板17、27形成凹處16、26，可 肖J減為此之加工成本及加工時間。然而，與將半導體基板3 配置於布線基板7、27内之上述第1、第2實施型態相比，不 利於半導體裝置整體之薄型化。 另外’需將半導體晶片2a、2b之外部連接用墊13，與布 線基板37之平台6之間之距離變大之部份，及將連接其等之 第2連接端子3 8之大小變大，為配合此，外部連接用墊13 及平台6之大小及間距亦變大。反而言之，比起第3實施型 悲’第1、第2實施型態可縮小第2連接端子丨2、外部連接用 墊13及平台6之大小及間距，可抑制平面方向中之尺寸增 加0 裝載半導體基板3之半導體晶片不限於二個，亦可為三個 107583.doc -22- 1303096 以上。例如於圖i 4 ’例示將四個半導體晶片7如〜而裝載於 半導體基板3。於數個半導體晶片7〇a〜观之中，例如 導體晶月係作為記憶元件發揮功能，其他之半導體晶片係 作為邏輯元件發揮功能。於其等數個半導體晶片7Ga〜7〇d， 亦可包含不直接與外部之布線基板連接之半導體晶片 7〇b僅而至乂 -個之半導體晶片與外部之布線基板連 可。
【圖式簡單說明】 圖1係關於本發明之篦！音& _ β 月之弟1貫靶型恶之半導體裝置之部份剖 面立體圖。 圖2係關於該第1實施型態之半導體裝置之剖面圖。 圖3係關於該第i實施型態之半導體裝置之製造步驟剖面 圖（其一）。 圖4係關於該第1實施型態之半導體裝置之製造㈣剖面 圖（其二）。
圖5係關於該第！實施型態之半導體裝置之製造步驟剖面 圖（其三）。 圖6係關於該第i實施型態之半導體裝置之製造步驟剖面 圖（其四）。 圖7係關於該第i實施型態之半導體裝置之製造步驟剖面 圖（其五）。 圖8係關於該第i實施型態之半導體裝置之製造步驟剖面 圖（其六）。 圖9係關於本發明之第2實施型態之半導體裝置之部份剖 107583.doc -23- 1303096 面立體圖。 圖10係關於該第2實施型態之半導體裝置之剖面圖。 圖11係關於該第2實施型態之半導體裝置之製造步驟剖 面圖（其一）。 圖12係關於該第2實施型態之半導體裝置之製造步驟剖 面圖（其二）。 圖13係關於本發明之第3實施型態之半導體裝置剖面圖。 圖14係表示於半導體基板上裝載數個半導體晶片之變形 例之平面圖。 圖15係本發明之變形例形成之半導體裝置之剖面圖。 圖16係第1以往之例之半導體裝置之剖面圖。 圖17係第2以往之例之半導體裝置之剖面圖。 【主要元件符號說明】 1 半導體裝置 2a、2b 半導體晶片 3 半導體基板 4 晶片間連接布 5 晶片連接用塾 6 平台 7 布線基板 8 第1連接端子 9 弟1連接端子 12 第2連接端子 13 外部連接用墊 107583.doc -24· 1303096 16 凹處 21 半導體裝置 26 凹處 31 半導體裝置 107583.doc -25-

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1303 γ 106813號專利申請案 文申请專利範圍替換本(97年4月）申請專利範圍：
—一____??年4 ?日修漫)正本 種半導體裝置，其特徵係具備·· 數個半導體晶片； 半導體基板’其於同-面側形成電性連接前述數個半 導體晶m用之晶片間連接布線、與連接於該晶片間連 接布線之數個晶片連接用墊； 布線基板，其具有以較前述晶片連接用墊大之間距所 配置之數個平台； 月’J述數個半導體晶片係介由第丨連接端子將其主面連 接於前述晶片連接用墊，裝載於前述半導體基板； 一别述半導體晶片之前述主面中，於不向半導體基板相 曰之邠伤幵> 成外部連接用墊，前述外部連接用塾係介由 第2連接端子與前述布線基板之前述平台連接。 2·如請求項1之半導體裝置，其中 前述半導體基板係位於形成於前述布線基板之凹處 内0 3·如請求項2之半導體裝置，其中 以包圍前述半導體基板之方式充填樹脂材於前述凹處 内’介由前述樹脂材接合前述半導體基板與前述布線基 板0 4· 一種半導體裝置，其特徵係具備： 數個半導體晶片； 半導體基板，其於同一面側形成電性連接前述數個半 導體晶片間用之晶片間連接布線、與連接於該晶片間連 107583-970407.doc 1303096 .. 接布線之數個晶片連接用墊； ·_ · 前述數個半導體晶片係介由連接端子將其主面連接於 . 前述晶片連接用墊，裝載於前述半導體基板； 前述半導體晶片之前述主面中，於不向半導體基板相 合之部份，形成以較前述晶片連接用墊大之間距所配置 之數個外部連接用墊。 • 5· 一種半導體裝置之製造方法，其特徵在於具有以下步驟： 於半導體基板，於同一面側形成與晶片間連接用布線 參 及該晶片間連接布線連接之數個晶片連接㈣之步驟； 於半導體晶片《主面中不向前述半導體基板相合之部 伤，形成以較前述晶片連接用墊大之間距所配置之數個 外部連接用墊之步驟； 於布線基板形成與前述外部連接用墊等間距之平台之 步驟； 於前述半導體基板之前述晶片連接用墊，介由第丨連接 端子連接數個前述半導體晶片之前述主面，將數個前述 瞻半導體晶片裝載於前述半導體基板之步驟； 介由第2連接端子，連接前述半導體晶片之前述外部連 接用墊與刖述布線基板之前述平台之步驟。 6·如請求項5之半導體裝置之製造方法，其中 於將前述半導體晶片裝載於前述半導體基板之前，使 前述晶片連接用墊露出於前述布線基板中之前述平台之 形成面侧，將前述半導體基板裝載於前布線基板上或配 置於前述布線基板中之後，使前述數個半導體晶片連接 於前述晶片連接用墊。 107583-970407.doc
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