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TWI246175B - Bonding structure of device packaging - Google Patents

Bonding structure of device packaging Download PDF

Info

Publication number
TWI246175B
TWI246175B TW093130750A TW93130750A TWI246175B TW I246175 B TWI246175 B TW I246175B TW 093130750 A TW093130750 A TW 093130750A TW 93130750 A TW93130750 A TW 93130750A TW I246175 B TWI246175 B TW I246175B
Authority
TW
Taiwan
Prior art keywords
substrate
bonding
metal
component
layer
Prior art date
Application number
TW093130750A
Other languages
English (en)
Other versions
TW200612534A (en
Inventor
Su-Tsai Lu
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to TW093130750A priority Critical patent/TWI246175B/zh
Priority to US11/047,646 priority patent/US7239027B2/en
Application granted granted Critical
Publication of TWI246175B publication Critical patent/TWI246175B/zh
Publication of TW200612534A publication Critical patent/TW200612534A/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81012—Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81232—Applying energy for connecting using an autocatalytic reaction, e.g. exothermic brazing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10659—Different types of terminals for the same component, e.g. solder balls combined with leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0285—Using ultrasound, e.g. for cleaning, soldering or wet treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
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1246175 玖、發明說明： 【發明所屬之技術領域】 本發明是關於一種接合結構，特別是關於一種元件 之構裝接合結構。 【先前技術】 由於半導體元件構裝技術對於增加元件可靠度、提 高接合密度以及減少元件尺寸方面的要求不斷提高，因 此傳統打線接合(wire bonding)逐漸被覆晶構果 (flip-chip)技術所取代。 覆晶構裝技術係於元件與基板的接合面形成接合 墊(pad)或疋凸塊(bump)以取代習知構裝技術所使用的 導線架（lead frame)，然後在基板表面塗佈接著劑。透 過直接壓合或焊接元件的凸塊與基板的接合墊來達成電 路導通，以完成覆晶構裝結構。相較於打線接合可降低 元件與基板間的電子訊號傳輸距離，適用於高速電子元 件的封裝。習知的覆晶構裝方法，由於塗佈於基板之接 著劑相對於元件兩者具有嚴重的熱膨脹係數差異，當溫 度產生變化時，熱應力的影響容易使元件及基板的凸塊 接點產生變形。 1246175 一般復μ構裝所使用的接著劑可分為非導電膜 (Non-conductive Film，NCF)及異方向性導電膜 (Anisotropic C〇ndUctlve Film，ACF)。傳統接合技術 係使用非導電膜，將料電薄驗佈於基板上，再使元 件與基板結合，並湘加壓與加熱程序使非導電薄膜融 溶，利用此薄膜固化完全後所產生㈣縮應力，將元件 與兀件接合在-起。此接合技術可提高較高之接合密 度，但元倾元件_合完全是依錢械力量維持，也 就是薄膜所產生的應力需轉接點導通的品質，一旦薄 膜所承X賴力過大時，又會使得細對於電路及基材 的其它接觸面上產生脫層（lamina1：iQn)的現象，導致接 合後的電阻升高。 ”方向丨生‘電膜接合技術係將一層含有導電粒子 之非等向性的導電薄膜置於元件與欲接合的元件之間， 利用域與加熱程序使_融溶，將元件與元件接合在 一起。使金屬接合墊、金屬凸塊與導電粒子來形成導電 通道。此雖合技術的缺點為：當金屬接合墊與金屬凸 塊的間距非常小時，目為加熱與加__會導致導電 /產生机動的現象’而使得相粦p的兩個導電點會發生 1246175 路勺見象，恶法符合微小化的需求，以致於接合密度 只能達到40微米("m)間距。 種，、日日擴散接合(diffusi〇n b〇nding)技術，係 利用高溫航件與基板之接點產生相互擴散的現象而進 仃接合’但因接合溫度往往需賴氏四百度以上，且兩 接點之金屬表面會形成金屬氧化物，其共價鍵會躅限住 金屬的自由電子，而使界關難以形成金屬鍵，且導電 見象來自於私子的穿隧效應，產生較高的接點阻抗，因 此也不適用於細間距（fine pitch)的應用。 【發明内容】 有鑑於此，本發明提供一種元件之難接合結構， 藉以達成結構改良與製程簡化的目的。 本發明揭露一種元件之構裝接合結構，主要包含第 -基板與第二基板；第一基板的表面具有複數個金屬墊 及第接合金屬層，第二基板的表面具有複數個電極及 第—接合金屬層，其中第—基板係接合於第二基板，第 接合金屬層與第二接合金屬層則互相接著固定，而複 數個金屬墊雜導通於複數個電極。_是，本發明之 第二基板可為—種可撓性基板，如高分子材質基板，用 1246175 以緩衝第-基板與第二基板接合所產生的應力。 另外，應用相同的原理，本發明另有一種元件之構 1接合結構，係使複數個電極及第二接合金屬層嵌入第 一基板僅露出頂端表面，同樣地，前述之第一基板的第 一接合金屬層接著固定於第二接合金屬層，而複數個金 屬墊電性導通於複數個電極。 並且’第一接合金屬層與第二接合金屬層間之接著 固定以及複數個電極之電性連接，可以直接以熱壓方 式、超音波接合或是表面活化處理來完成接合，亦可先 配合表面活化處理或超音波振聽再以麵方式進行接 石。將接合界面先經過表面活化或超音波處理，可降低 接合溫度，解決現有接合製程所面臨的高溫問題。 本發明的兀件之構裝接合結構可應用在如積體電路 晶片與基板的接合，無需使用非導電膜或異方向性導電 膜，相較於先前技術，可提高接合密度，達到細間距接 合，增加製程可靠度，並減少製程步驟以及降低製造成 本。 為使對本發明的目的、構造特徵及其功能有進一步 的了解，茲配合圖示詳細說明如下·· U46175 【實施方式】 為更加詳細說明本發明，請參考第丨圖，其為本發 明第一實施例的放大戴面示意圖。 如第1圖所示，其包含第一基板100與第二基板 ，第一基板的表面具有複數個金屬墊110、黏著金屬 14〇及第—接合金屬層13Q，保護層14〇 係t成於第-基板⑽的表面並露出複數個金屬塾 110 ’黏著金屬線路120係連接於金屬墊11〇並延伸覆蓋 《保善層140’以利於後續之電性連接，第一接合金屬層 130覆蓋於保護層刚上。第二基板·絲面具有複數 们电極210及第二接合金屬層220，其中第一基板1〇〇 係以面對面的方式接合$二基板12()，使第—接合金屬層 ⑽接著固定於第二接合金屬層22〇，而複數個金屬墊 110係導通於黏著金屬線路120 α電性連接於複數個電 極210,亚且第一基板1〇〇和第二基板·之接合邊緣係 填入J里接著劑230,以更穩固第一基板1〇〇與第二基板 2〇〇的接合，並防止水氣進入接合結構。 亚且’本發明之第—基板的金屬墊與第二基板之電 極可利用第-基板之黏著線路向外延伸以連接於第二基 9 1246175 板之電極處。請參考第2圖，其為本發明第二實施例的 放大截面示意圖。 才反200 ;第一基板 著金屬線路120、> 同樣地，包含第一基板100與第二基
屬墊11 〇，勒著金屬線路i20係連接於金屬墊i i 〇並延伸 设现於保4層14G，第-接合金屬層13G覆蓋於保護層 I40上。第二基板200的表面具有複數個電極210及第二 接合金屬層22G，第-基板⑽係接合於第二基板·， 使第-接合金屬層⑽接著固定於第二接合金屬層 220，然而第-基板1〇〇的金屬墊11〇並未對準於第二基 板200之電極210,第一基板之黏著線路12〇係延伸以連 接於第一基板2GG之電極21〇處’使複數個金屬墊11〇 導通於黏著金觀路12(Uxf性連接於複數個電極 210，且第一基板1〇〇和第二基板2〇〇之接合邊緣係填入 少量接著劑230。 此外，本發明亦可使複數個電極21〇及第二接合金 屬層220嵌入第二基板200僅露出頂端表面，請參考第3 圖，其為本發明第一實施例的放大截面示意圖。包含第 10 1246175 基板100與第二基板200;第一基板100之結構係如前 所述，而第一基板200的表面所設置之複數個電極 及第二接合金屬層220係嵌入第二基板2〇〇僅露出其頂 端表面，第一基板100係以面對面的方式接合第二基板 20〇 ’使第一接合金屬層13〇接著固定於第二接合金屬層 220而複數個金屬墊HQ係導通於黏著金屬線路以 兒性連接於複數個電極210,且第一基板1〇〇和第二基板 2〇〇之接合邊緣係填入少量接著劑230。藉由内嵌式的第 二基板結構，可以更進一步減少封裝的體積。 其中，内嵌式基板可藉由以下之步驟來製成，靖表 考第4A圖至第4D圖，其為内嵌式基板的製造流程示音 圖。 如第4A圖所示，先於承載基板401上沉積金屬層 400。 又如第4B圖所示，蝕刻金屬層4〇〇以形士〜 乂形成所需的電 極410與第二金屬接合層420。 如第4C圖所示，於承載基板上塗佈高八 刀子層3〇〇以 覆蓋電極410與第二金屬接合層420。 如第4D圖所示，去除承載基板4〇1，以％ 路出嵌入高 11 1246175 刀子層300之電極410與第二金屬接合層420的表面， 以形成内嵌式之第二基板。 亚且，第一接合金屬層與第二接合金屬層間之接著 口定以及複數個電極與黏著金屬電路或金屬墊之電性連 接’可以直接以錢方式、超音波接合或是表面活化處 理來完成接合，亦可先配合表面活化處輯超音波振盪 將接合界面進行表面活化或超音波處理，再以熱壓或是 直接接合方式進行接合。其中所配合之表面活化處理係 將第一金屬層、接合層和複數個電極之表面上的塵埃粒 子和乳化層去除，再進行後續接合製程，於接合界面形 成金屬鍵結 因此可使第一基板與第二基板索形成的元 件之構裝接合結構具有極佳之電氣特性。 本發明係以第-金屬接合層與第二金屬接合層之結 來進行第-基板與第二基板的接著固定，無需使用非 導電膜或異方向性導賴，且由於第—金屬接合層可以 铃第基板之金屬塾或黏著金屬電路同時形成，而第二 至屬接合層可以與第二基板的電極同時形成，因此，可 '咸^衣私步驟以及降低製造成本。再於接合製程中將接 合界面先經過表面活化或超音波處理，可降低接合溫 12 1246175 度’解決現有接合製程所面臨的高溫問題。 雖然本發明之較佳實施例揭露如上所述，然其並非 用以限定本發明，任何熟習相關技藝者，在不脫離本發 明之精神和範圍内，當可作些許之更動與潤飾，因此本 發明之專利保護範圍須視本說明書所附之申請專利範圍 所界定者為準。 【圖式簡單說明】 第1圖為本發明第一實施例的放大截面示意圖； 第2圖為本發明第二實施例的放大截面示意圖； 第3圖為本發明第一實施例的放大截面示意圖；及 第4A圖至第4D圖為内嵌式基板的製造流程示意圖。 【圖式符號說明】 100 110 120 130 140 200 210 220 230 300 400 401 410 弟一基板 金屬墊 黏著金屬線路 第一接合金屬層 保護層 第二基板 電極 第二接合金屬層 接著劑 局分子層 金屬層 承載基板 電極 13 1246175 420 第二金屬接合層 14

Claims (1)

1246175 拾、申請專利範圍： 1· 一種元件之構裝接合結構，其包含有. —第一基板，其表面具有複數個金屬墊及-第-接合 金屬層；及 -第二基板，絲面具有複_ f極及—第二接合金 屬層，該第二接合金屬層接著固定於該第一接合金屬層， 使為第-基板係接合於第二基板，該金屬墊電性導通於該 電極。 2. 如申請專利範圍第丨項所述之元件之構裝接合結構，其中 該第-基板包含-黏著金屬線路，係連接該金屬墊與該電 才亟。 3. 如申請細請第2 _述之元件之構裝接合結構，苴中 該電極與該黏著金屬線路間之接合，係以紐、超音波接 合及表面活化處理接合財之—方法來完成接合。 4·如申請專利範圍第2項所述之元件之構裝接合結構，其中 讀電極與該金屬墊間之接著固定，係先以超音波㈣及表 舌化處理其中之方法’處理該第一接合金屬層與該第 〜接合金屬層的欲接合面，再以熱壓與直接接合其中之一 方法進行接合。 15 1246175 5.如申請細刪1綱述之元件之騎接合結構，並中 該第-基板包含-保護層，係披覆於該第—基板並露出該 金屬墊。 ^ 6_如申請細|_酬叙元件之構餘合結構，其中 該第:基板包含-黏著金屬線路，係連接於該金屬塾且延 伸覆蓋於該保護層，並連接於該電極。 7. '申請專利範’項所述之元件之構裝接合結構，其中 該第-基板之黏著線路係延伸至連接於該第二基板之該 電極處。 請專利範圍第丨項所述之元件之構裝接合結構，其中 該第二基板為一可撓性基板。 9. 如申請專利範圍第8項所述之元件之構裝接合結構，其中 該可撓性基板為高分子材質基板。 10. 如/請專利範圍第！項所述之元件之構裝接合結構，其 中該第二基板為-後入式基板，該電極與該第二接合金屬 層係肷入於該第二基板僅露出其頂端表面。 11. 如申請專利範圍第10項所述之元件之構裝接合結構，其 中该嵌入式基板之製造步驟包含： 於—承載基板上沉積一金屬層； 16 1246175 钱刻D亥金屬層形成所需的該電極與該第二金屬接合 層； 塗佈一鬲分子層於該承載基板以覆蓋該電極與該第 一金屬接合層；及 去除該承載基板，露出嵌入於該高分子層之該電極與 該第二金屬接合層_端表面，以形成該纽式基板。 12·如申請專利範圍第}項所述之元件之構裝接合結構，其 中該第-接合金屬層與該第二接合金屬層間之接著固 定，係以熱壓、超音波接合及表面活化處理接合其中之一 方法來完成接合。 13.如申請專利範圍第！項所述之元件之構裝接合結構，其 愤第-接合金屬層與該第二接合金屬層間之接著固 定，係先以超音波振盪及表面活化處理其中之一方法，處 理該第-接合金屬層與該第二接合金屬層的欲接合面再 以熱墨與直接接合其中之一方法進行接合。 R如申請專利範圍第1項所述之元件之構餘合結構，其 令該電極與該金屬墊間之接著固定，係以熱壓、超音波接 合或是表面活化處理接合其中之—方法來完成接人。 15.如申請專利範圍第1項所述之元件之構裝接合結構，並 17 1246175 中該電極與該金屬墊間之接著固定，係先以超音波振盪及 表面活化處理其中之一方法，處理該第一接合金屬層與該 第一接合金屬層的欲接合面再以熱壓與直接接合其中之 一方法進行接合。 16 ·如申令主畜 明利範圍第1項所述之元件之構裝接合結 包含一技 缕 •制以結合該第—基板與該第二基板的邊 18
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US20060078715A1 (en) 2006-04-13

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